8051 Microcontroller
Sudip Nag
Department of E & ECE
IIT Kharagpur
Pin Diagram
Pin Diagram
Ground
Overview of 8051 Features
• ROM – 4K Bytes
• RAM – 128 B Bytes
tes
• Timer – 2
• I/O Pins
Pi – 32 (P0 tto P3)
• Serial Port – 1
• Interrupt sources – 6
Features (in detail)
Features (continued)
8051 Architecture (simplified)
(8 bit microcontroller)
(8-bit i t ll )
4 KB
128 Bytes
30 pF 30 pF
1.24-12 MHz
80051 A
Archittecturre (deetailed
d)
(88-bit miicrocon
ntrollerr)
Core Family Chips of 8051 Series
Nil
8051 Interfacing overview
Input and output
devices can be
directly
connected to the
available IO
ports/ pins
8051 Register Organization
• General purpose:
4 banks of 8-bit registers (R0-R7) – RAM address 00 –
07H 08H
07H; 08H-0FH;
0FH 10H10H-17H;
17H 18H
18H-1FH
1FH
• Special function register:
• A (8) – ACC; B (8) : Commonly used during /
operation
• DPH and DPL ((16)) : Data ppointer registers
g used for
external memory access
• Stack pointer - SP (8-bits)
• P0 – P3 (8-bits): I/O port registers
• Timer/Counter Registers: TMOD, TCON, TH0, TL0,
TH1 TL1 : Hold the count values of the two on-chip
TH1, on chip
timers/counters
Memory Organization
• Has separate program memory and
data memory.
• Program memory: 4 KB on-chip
memory; provision of having 64KB
externall program memory.
• For EA=1, access internal memory
f
from 0000
0000-000FH
000FH and d external
t l
memory for higher addresses. If it’s
0 all instructions are accessed from
0,
the external memory only.
Data Memory
• 128 bytes of on-chip RAM and the 21
SFRs.
• There is provision for having 64 KB
external data memory.
memory
RAM Allocation in 8051
Register banks and RAM addresses
8051 SFRs
• Address Range – RAM locations 80H to FFH
• Serial port registers: SCON – Control Register,
SBUF(T ) SBUF(Rx)
SBUF(Tx), SBUF(R ) – holdh ld the
th serial
i l data
d t to
t be
b
output/input.
• Interrupt Control: IE (Interrupt enable),
enable) IP (interrupt
priority)
• PSW Register:
g Flagg bits;; Register
g bank selection bits;;
Parity bit (0/1 E/O)
8051 Special Function Registers
8051 Special Function Registers (continued)
• PSW Register (similar to the flag register in 8085)
TCON
TMOD
Timer 0 storage registers
TH0
TL0
*Similarly, TH1 and TL1 registers are for timer 1
SCON
SCON
PCON
BDRCON
Multifunction I/O ports
• 32 out of 40 pins are used to provide 4 I/O ports (P0-
P3)
• These
Th are usedd
- As parallel bidirectional I/O ports
-To interface with internal memory
- As timer/counter
- As serial ports
p
- For interrupt processing
• The ports are initialized as input ports
• Write the first zero - becomes an output port
• Write an one – becomes input port
Port functionality
• P0: Used to output the lower order address byte (A0-
A7) whenh external
t l memory is
i interfaced;
i t f d otherwise,
th i
acts as simple I/O port. No pull up resistor.
• P1: Used as a simple I/O port.
port Has pull up resistor
resistor.
• P2: Used to output the higher order address byte
((A8-A15)) when external memoryy is interfaced;;
otherwise, acts as simple I/O port. Has pull-up
resistor.
• P3: Used as simple I/O ports or alternate functions.
Has a pull-up resistor.
Port circuitry
External program memory access
P1 AD7-AD0 D7-D0
A7-A0
P3 A15-A8
External data memory access
P1 AD7-AD0 D7-D0
A7-A0
P3 A10-A8
ALU Capability
•Arithmetic Operation:
ADD INC,
ADD, INC DEC
DEC, CMPZ
CMPZ, CMPNZ,
CMPNZ SUBB,
SUBB MUL,
MUL
DIV
•Logical Operation:
AND, OR, EX-OR, RL, RLC, RR, RRC, SWAP
•Boolean Processor- Provides rich bit manipulation
capability including Set,
capability, Set Clear,
Clear Complement,
Complement Jump-if-
Jump if
Set, J-if-NSet, J-if-Set-then-Clear.
These operations
p can be performed
p on a ppart of the data
RAM (128 bits) and 128 bits within the SFRs.
Bit addressable RAM and Registers
Registers
P0-P3, A, B, PSW,IP,IE
ACC, SCON, TCON
Bit addressable SFRs
Reset Operation
• Hold the RST pin to
a high level for at
least 2 cycles
• Power-on
P resett - can
be implemented by
connecting
ti a 10 uF F
capacitor between
RST pini andd
ground.
Interrupt Structure
• External Interrupt (2) – Generated by external
sources through and .
• Internal Interrupt
p ((3)) – From the on-chip
p
functional units
Interrupt Priority
• Set by writing to the special function interrupt priority
register (IP).
(IP)
Bits 7 6 5 4 3 2 1 0
X X X PS PT1 PX1PT0 PX0
PS: Serial port priority level (1/0)
PT1/PT0 Timer
PT1/PT0: Ti (1/0) Interrupt
I t t Priority
P i it level
l l (1/0)
PX1/PX0: External Interrupt 1/0 Priority level (1/0)
Internal polling sequence selects the interrupt to be
serviced if p
priorityy is same for received interrupts
p -
INT0 > T0 > INT2 > T1 > Serial port
Interrupt Masking
• IE – Register used to enable or disable interrupts
Bits 7 6 5 4 3 2 1 0
EA X X ES S ET1 EX1 ET0 0 EX00
EA=0 – Disable all the interrupts; EA=1 – set or reset the
corresponding masking bit to enable (=1) or disable (=0)
an interrupt.
Bits 7 6 5 4 3 2 1 0
EA X X ES ET1 EX1 ET0 EX0
Serial port
Timer External Intr.
Intr
Interrupt Structure (Contd.)
• INT0 and INT: External interrupt; Low level sensitive; Must be
active for at least 12 CC to be sensed by the processor; REI
instruction at the end of the ISS deactivates this signal.
• Can be configured in edge-triggered (high-low) mode by setting
th IT0 or IT1 bits
the bit in
i the
th TCON register.
it
TCON register:
Bits 7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
If IT0/IT1=1,
IT0/IT1 1, IE0/IE1 is set by H/W when 11-00
transition is detected on INT0 or INT1.
Event sequence
• Initialization: Configure different components/
registers by appropriate values
values.
•Polling: After initialization, application program is
executed. Active interruptsp are checked as per
p the
assigned priority levels and are serviced.
Summary
• Features of 8051 microcontroller.
• Register organization; SFRs; memory
organization/interfacing.
• Basic internal architecture of 8051.
8051
• Multifunction ports; timing diagram;
memory addressing;
dd i
• Interrupt structure
