Invited Paper

Gate Oxide Scaling Limits and Projection

Chenming Hu
Dept. of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720

Abstract is surprisingly predictable (2). Temperature effect (3), a

MOSFET gate oxide scaling limits are examined with physical interpretation and refinement for very thin
respect to time-dependent breakdown, defects, plasma oxide(4) have been presented. The model predicts the oxide
process damage, mobility degradation, poly-gate depletion, lifetime as a function of Tox and Vox very well (Fig. 1) (4).
inversion layer thickness, tunneling leakage, charge
trapping, and gate delay. It is projected that the operating
field will stay around 5MV/cm for reliability and optimum
speed. Tunneling leakage prevents scaling below 2nm,
which is sufficient for MOSFET scaling to 0.05µm.

Introduction
In order for a MOSFET to behave as a transistor, the gate
must exert greater control over the channel than the drain
dose, i.e., the gate to channel capacitance must be larger
than the drain to channel capacitance. A simple model
suggests (1)
Lmin ∝ Tox • Xj 1/3 [1]

A survey of the literature would reveal that the most Fig. 1 Oxide lifetime has been described by a hole-injection
thorough device physics studies of the late 1970’s pegged model.
the scaling limit of MOSFET at 0.5µm. In the mid 1980’s,
it was 0.25µm. Today, no device physics barrier is foreseen Both data extrapolation and the model predict that oxide
for scaling to at least 0.1µm. What fogged the crystal balls can have 20 years lifetime at 125°C up to oxide field of
of the yesteryears was the uncertainty over the minimum 7MV/cm, 8MV/cm for below 5V operation. In Fig. 2, for
acceptable Tox in Eq. [1]. The scaling limit of Tox is example, 5.5V operation can use 8nm, 3.6V operation
therefore of paramount importance. Besides suppressing requires only 4.5nm, and 2.75V requires 3.3nm.
the short channel effect, reducing Tox improves Id and
generally but not always raises circuit speed. Thinner
tunnel oxide would also be desirable for lowering the
program voltage of nonvolatile memory. Clearly, there are
many strong incentives to reduce Tox at each technology
generation. What, then, are the limits to oxide scaling?
This paper attempts to answer this critical question.

Oxide Breakdown
Oxide breakdown has historically been the limiting factor
in choosing Tox. The past pessimistic predictions of Lmin
can be directly attributed to a lack of understanding of the
oxide breakdown limit.

•Intrinsic Breakdown Field. If gross “defects” are not

present, i.e., if one studies oxide samples which are very Fig. 2 The maximum acceptable field for 30 year lifetime of
much smaller than 1mm2 in size, the lifetime of the oxide defect-free oxide is 7-8 MV/cm.

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•Derating of Breakdown Field due to Defects. A Fowler-Nordheim equation describes the oxide current, IFN.
manufacturable process must provide a soft margin above The intersections determine the stress currents and
the intrinsic breakdown limit. Recent production voltages in this plasma process equipment. Clearly, the
experiences suggest that ~30% derating to 5 to 5.5MV/cm oxide stress current hardly increases as Tox is reduced from
seems to be reasonable, i.e., 11nm for 5.5V, 6.5nm for 10 nm to 0 nm. To understand Fig. 3, one needs to also
3.6V, and 4.5nm for 2.75V. realize that thinner oxide (6.4nm) is more tolerant of the
For a given manufacturing line, one can use an “effective same current stress than thicker (11.6nm) oxide.
thickness” defect model to predict the product oxide yield,
reliability failure rate, optimal burn-in condition, etc. from Transistor Current and Speed
the statistical distribution of the breakdown voltage of All else being equal, MOSFET current always increases
oxide test samples (5). when Tox is reduced, although at a lower rate than a simple
model might suggest because of mobility reduction,
•Process Induced Damage. Fig. 3 shows that 18nm oxide polysilicon gate depletion, and finite inversion layer
with large “antenna” structure has low interface trap thickness. Gate speed, on the other hand, may slow down
density after plasma etch indicating little plasma-induced due to excessive Tox reduction.
damage. 11.6nm oxide has an order of magnitude more
interface traps, reflecting significant damage. Surprisingly, •Mobility. Electron and hole mobilities have been shown
the very thin 6.4nm oxide exhibits much less damage than to be highly predictable function of (Vg+Vt)/Tox as shown
the 11.6nm oxide. in Fig. 5 (7). Once Vg(=Vdd), Vt, and Tox are specified,
mobilities are known. See (7) for modification for buried
channel MOSFET.

Fig. 3 Plasma process antenna-effect actually causes less damage

to 6.4 nm oxide than 11.6 nm oxide.

This exciting trend had first been predicted by a model

illustrated in Fig. 4 (6). Langmuir equation describes the
plasma current (Ip) collected by the antenna (plasma
probe).

(Vgs+Vt)/6Tox (MV/cm)

Fig. 5 Carrier mobility remains unchanged, if Vdd, Vt, and Tox are
scaled in proportion.

•Polysilicon Gate Depletion and Inversion Layer

Quantization. Gate depletion can be simply modeled with
the usual MOS (polysilicon gate being S) depletion
equation (8). The big surprise, still unexplained, is that the
polysilicon doping concentration at the oxide interface
Fig. 4 Plasma charging (Ip) resembles a constant-current source seems to be only around 3x1019 cm-3. At Eox=5MV/cm, the
rather than a fixed voltage source, therefore does not devastate depletion layer thickness is about 0.6nm equivalent oxide
very thin oxides. Included are three data points.
thickness or 0.3V reduction in Vg. This is a significant

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“excess oxide thickness” as we reduce Tox to 6nm or
below. Even with the polysilicon gate biased into •Speed. Fig. 7 shows the projected inverter delay time
accumulation, the CV data would indicate an “electrical versus the Tox (7). For low Vdd operation, maximum speed
Tox” that is about 0.5nm thicker than the physical Tox as may dictate the use of an oxide that is thicker than what
determined by optical techniques or from tunneling IV the 5MV/cm breakdown limit would allow. While the
characteristics. This is because the inversion layer carriers optimal thickness should be thinner than what Fig. 7
are located at about 1.5nm (0.5nm effective oxide suggests if the circuit is more heavily loaded by the
thickness) below the Si/SiO2 interface. The middle curve in interconnect capacitance, anecdotal data of large CPUs
Fig. 6 (9) is the Idsat predicted by today’s standard 2D actually agree with Fig. 7 well.
device simulators for some future technologies. The bottom
curve is obtained when polygate depletion and inversion Oxide Leakage and Device Drift
layer quantization are included in the simulation. As an •Direct Tunneling. Whenever oxide voltage is lower than
important beside, the top curve includes polygate depletion, 3.2V (the Si/SiO2 barrier voltage), the electron tunneling
inversion layer quantization, and velocity overshoot barrier changes from being triangular to trapezoidal and
(energy balance) effect (9). the oxide current, known as the direct tunneling current,
remains high at even 1V and is very sensitive to Tox as
shown in Fig. 8 (4). Static logic circuits can tolerate large
gate leakage, e.g. 1A/cm2 (even though the junction
leakage is typically 1µA/cm2). For 1V operation, Fig. 8
would suggest 2 or 2.5nm as the scaling limit. DRAM can
tolerate less oxide leakage and typically bootstraps above
Vdd. 3nm may be the Tox limit for DRAM, making scaling
below 0.1µm difficult. This discrepancy needs a resolution.

Fig. 6 Middle and bottom curves show the effect of polysilicon

depletion and large inversion layer thickness due to quantization,
Some reasonable Vdd and Tox values are used.

Fig. 8 Direct tunneling may limit oxide scaling to around 2.5 nm.

•Stress Induced Leakage. High field stress of thin oxide

creates low-field leakage, apparently through the
generation of neutral oxide traps that facilitate electron
tunneling. Fig. 9 highlights the different behaviors of thick
and thin oxides (10). This leakage makes nonvolatile
memory tunneling oxide scaling much below 8nm difficult
Fig. 7 At low Vdd, e.g. 2 Volts and 0.25 µm, optimum speed may and perhaps impossible unless the 10 year charge retention
require a thicker Tox than that allowed by the 5 MV/cm limit. requirement is relaxed (11).

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•Charge Trapping and MOSFET Stability. Even if the Summary and Projection
static logic circuits can tolerate very large oxide leakage Fig. 10 and Fig. 7 summarize the consideration for
and therefore very thin oxide, will there be severe charge choosing Tox. 20 year intrinsic lifetime can be achieved at
trapping and MOSFET drift as a result of the huge charge 7MV/cm in 8nm oxide, rising gradually to 9MV/cm in
3nm oxide. 30% derating for defects puts the field limit at
5MV/cm rising to 6 MV/cm. Below 2.5V, oxide leakage
(Fig. 10) and circuit speed (Fig. 7), rather than oxide
breakdown, will dictate the choice of the oxide thickness.
(Oxide defects will still need to be vigilantly controlled.)
The optimal Tox are:
~12nm if 5V/0.5µm, limited by defect breakdown;
~6.5nm if 3.3V/0.35µm, limited by defect breakdown and
circuit speed;
~4.5nm if 2.5V/0.25µm, limited by defect breakdown and
circuit speed ;
~4nm if 1.5V/0.18µm, limited by circuit speed;
~3nm if 1.5V/0.1µm, limited by circuit speed and defect
breakdown;
~2nm if 1V/0.05µm, limited by leakage.
The above Tox values are the final physical thickness.
Electrical thickness would be 0.5nm thicker . Tox can be
Fig. 9 Stress-induced leakage is a transient current in thicker
up to 30% thinner than those listed above if only small
oxides but a continuous current in thinner oxides, preventing
NVM oxide scaling. area of oxide is used ( so that the margin allowance for
defects can be small), e.g. 3.3V I/O devices in 2.5V
fluence in 20 year’s time? Only preliminary studies have products, etc. (13). Excess oxide leakage will limit scaling
been reported (12) and early indication is that 3nm oxide just above 2nm, which makes 0.05µm MOSFET possible.
can tolerate at least 1000 coul/cm2, i.e. 20 years at 1V, of DRAM gate oxide thickness will reach limit earlier at
charge passage without significant drift. ~3nm. Plasma process damage will not become much more
serious with future oxide scaling.

Acknowledgment
This work is supported by SRC-IJ148, AFOSR, JSEP,
AMD, TI, IDT, and MICRO.

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Fig. 10 Scaling limits due to breakdown, tunneling leakage, and (13) C. Hu, et al, ISSCC, p.86, 1994
device stability (12).

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