ATPG LAB NOTES:
Inputs:
1) Netlist (Scan / SCAN + Compression)
2) Library (mdt format)
3) ATPG Setup files(from Scan insertion / from compression)
Atpg dofile ( Clocks and scan chains information)
Test procedure file
4) Dofile ( to perform pattern generation)
Outputs:
1) Testbench along with patterns
Chain patterns (to test scan path)
Serial
Parallel
Scan or capture patterns (Tests both scan path and capture path)
Serial
Parallel
2) Reports like scan chain, scan cells, coverage, DRC’s , faults, etc..
How to run the lab:
Create a run file and source it.
Useful commands:
tessent -shell -lib /home/sujith/scan_insertion_golden/library/atpg/tsmc13.mdt -dofile atpg.dofile -log
./log/atpg.log -replace
Observations:
1) Coverage number ( Calculate the coverage manually)
2) AU Faults
3) DRC’s
4) Scan flops/scan chains
5) Non-scan flops
ATPG DOFILE Commands:
For stuck-at :
/////////////////////////////////////////////////////////////////
// Generated by DFTAdvisor at Thu Feb 12 10:36:00 2009 //
/////////////////////////////////////////////////////////////////
// Save the Log //
/////////////////////////////////////////////////////////////////
set_context patterns -scan
read_verilog /home/sujith/atpg_labs/stuck_at/EDT/case1/inputs/netlist/DmaWr_edt_top_gate.v
Note : We can give scan / scan + compression netlist
/////////////////////////////////////////////////////////////////
// FastScan Version //
/////////////////////////////////////////////////////////////////
set_current_design DmaWr
dofile /home/sujith/atpg_labs/stuck_at/EDT/case1/inputs/dofile/DmaWr_edt.dofile
/////////////////////////////////////////////////////////////////
// Check the Contention //
/////////////////////////////////////////////////////////////////
set contention check capture_clock -atpg
/////////////////////////////////////////////////////////////////
// report Primary inputs all //
/////////////////////////////////////////////////////////////////
set system mode atpg
/////////////////////////////////////////////////////////////////
// Verify there are no DRC violations. //
/////////////////////////////////////////////////////////////////
report drc rules
/////////////////////////////////////////////////////////////////
// Define the Fault Model //
/////////////////////////////////////////////////////////////////
set fault type stuck
/////////////////////////////////////////////////////////////////
// Add All Faults //
/////////////////////////////////////////////////////////////////
add faults -all
/////////////////////////////////////////////////////////////////
// Run //
/////////////////////////////////////////////////////////////////
create_patterns
/////////////////////////////////////////////////////////////////
// Report //
/////////////////////////////////////////////////////////////////
report drc rules
report environment
report scan cells > /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/reports/scan_cells.rpt
report scan chains > /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/reports/scan_chains.rpt
report patterns > /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/reports/patterns.rpt
/////////////////////////////////////////////////////////////////
// Write Faults //
/////////////////////////////////////////////////////////////////
write faults /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/faults/DET.faults.rpt -r -c DS -c DI -c
RE -c UU -c TI -c BL
write faults /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/faults/UDET.faults.rpt -r -c AU -c UO -c
UC
/////////////////////////////////////////////////////////////////
// Save Patterns //
/////////////////////////////////////////////////////////////////
// chain Test serial Pattern
write_patterns /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/patterns/chaintest_serial.v -
pattern_sets chain -verilog -serial -replace
// scan capture patterns
write_patterns /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/patterns/scan_or_capture_serial.v
-pattern_sets scan -verilog -serial -replace
// chain Test parallel Pattern
write_patterns /home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/patterns/chaintest_parallel.v -
pattern_sets chain -verilog -parallel -replace
// scan capture parallel patterns
write_patterns
/home/sujith/atpg_labs/stuck_at/EDT/case1/outputs/patterns/scan_or_capture_parallel.v -
pattern_sets scan -verilog -parallel -replace
write_patterns ./patterns/scan_or_capture.wgl -pattern_sets scan -wgl -parallel -replace
write_patterns ./patterns/scan_or_capture.stil -pattern_sets scan -stil -parallel -replace
write_patterns ./patterns/scan_or_capture.ascii -pattern_sets scan -ascii -parallel -replace
/////////////////////////////////////////////////////////////////
// Exit //
/////////////////////////////////////////////////////////////////
//Exit
Atspeed Dofile commands:
/////////////////////////////////////////////////////////////////
// Generated by DFTAdvisor at Thu Feb 12 10:36:00 2009 //
/////////////////////////////////////////////////////////////////
// Save the Log //
/////////////////////////////////////////////////////////////////
set_context patterns -scan
read_verilog /home/sujith/ATPG_Training/case1/netlist/DmaWr_edt_top_gate.v
/////////////////////////////////////////////////////////////////
// FastScan Version //
/////////////////////////////////////////////////////////////////
report version data
set_current_design DmaWr
dofile ./DmaWr_edt.dofile
/////////////////////////////////////////////////////////////////
// Check the Contention //
/////////////////////////////////////////////////////////////////
set contention check capture_clock -atpg
set transition holdpi on
/////////////////////////////////////////////////////////////////
// report Primary inputs all //
/////////////////////////////////////////////////////////////////
set system mode atpg
/////////////////////////////////////////////////////////////////
// Verify there are no DRC violations. //
/////////////////////////////////////////////////////////////////
report drc rules
/////////////////////////////////////////////////////////////////
// Define the Fault Model //
/////////////////////////////////////////////////////////////////
set fault type transition -no_shift_launch
/////////////////////////////////////////////////////////////////
// Add All Faults //
/////////////////////////////////////////////////////////////////
add faults -all
/////////////////////////////////////////////////////////////////
// Run //
/////////////////////////////////////////////////////////////////
create_patterns
reset_au_faults
set pattern type -seq 2
create_patterns
/////////////////////////////////////////////////////////////////
// Report //
/////////////////////////////////////////////////////////////////
report drc rules
report environment
report scan cells > ./reports/scan_cells.rpt
report scan chains > ./reports/scan_chains.rpt
report patterns > ./reports/patterns.rpt
/////////////////////////////////////////////////////////////////
// Write Faults //
/////////////////////////////////////////////////////////////////
write faults ./reports/DET.faults.rpt -r -c DS -c DI -c RE -c UU -c TI -c BL
write faults ./reports/UDET.faults.rpt -r -c AU -c UO -c UC
/////////////////////////////////////////////////////////////////
// Save Patterns //
/////////////////////////////////////////////////////////////////
// chain Test serial Pattern
write_patterns ./patterns/chaintest_serial.v -pattern_sets chain -verilog -serial -replace
// scan capture patterns
write_patterns ./patterns/scan_or_capture_serial.v -pattern_sets scan -verilog -serial -replace
// chain Test parallel Pattern
write_patterns ./patterns/chaintest_parallel.v -pattern_sets chain -verilog -parallel -replace
// scan capture parallel patterns
write_patterns ./patterns/scan_or_capture_parallel.v -pattern_sets scan -verilog -parallel -replace
write_patterns ./patterns/scan_or_capture.wgl -pattern_sets scan -wgl -parallel -replace
write_patterns ./patterns/scan_or_capture.stil -pattern_sets scan -stil -parallel -replace
write_patterns ./patterns/scan_or_capture.ascii -pattern_sets scan -ascii -parallel -replace
/////////////////////////////////////////////////////////////////
// Exit //
/////////////////////////////////////////////////////////////////
//Exit
Atspeed Test Procedure file:
//
// Written by Tessent Shell 2016.3 on Sat Jun 30 08:56:54 2018
//
set time scale 1.000000 ns ;
set strobe_window time 10 ;
timeplate slow_clk = // 25 Mhz
force_pi 0 ;
measure_po 10 ;
pulse_clock 20 10 ;
pulse Reset 20 10;
pulse edt_clock 20 10;
pulse scan_reset 20 10;
pulse scan_set 20 10;
period 40 ;
end;
timeplate fast_clk = // 100 Mhz
force_pi 0 ;
measure_po 3 ;
pulse_clock 5 3;
pulse Reset 5 3;
pulse edt_clock 5 3 ;
pulse scan_reset 5 3;
pulse scan_set 5 3;
period 10 ;
end;
procedure test_setup =
timeplate slow_clk ;
// cycle 1 starts at time 0
cycle =
force edt_clock 0 ;
force scan_en 0 ;
force test_en 1 ;
end;
end;
procedure shift =
scan_group grp1 ;
timeplate slow_clk ;
// cycle 1 starts at time 0
cycle =
force_sci ;
force edt_update 0 ;
measure_sco ;
pulse FastClk ;
pulse edt_clock ;
end;
end;
procedure load_unload =
scan_group grp1 ;
timeplate slow_clk ;
// cycle 1 starts at time 0
cycle =
force FastClk 0 ;
force Reset 1 ;
force edt_bypass 0 ;
force edt_clock 0 ;
force edt_update 1 ;
force scan_en 1 ;
force scan_reset 0 ;
force scan_set 0 ;
force test_en 1 ;
pulse edt_clock ;
end ;
apply shift 15;
end;
procedure capture =
timeplate fast_clk ;
// cycle 1 starts at time 0
cycle =
force_pi ;
measure_po ;
pulse_capture_clock ;
end;
end;
procedure clock_sequential =
timeplate fast_clk ;
// cycle 1 starts at time 0
cycle =
force_pi ;
pulse_capture_clock ;
pulse_read_clock ;
pulse_write_clock ;
end;
end;
