DFT Quick Reference
Guide
Kavita Chaturvedi
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Outline
• Purpose
• DFT Basics
• DFT Issues & Fixes
• Scan Compression
• Tool Usage
– Scan Insertion Flow in RC
– Scan Compression Flow in RC
– ATPG Flow (For SAF) in ET
– ATPG Flow (For TDF) in ET
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Purpose
• The purpose of this document is to serve as a DFT guidelines for
beginners.
• This gives an overview of design-for-test (DFT) issues and shows the
use of Cadence tools usage as part of typical DFT design flow.
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DFT Basics: Why DFT?
• DFT is performed for manufacturing test which ensures that design
parts are manufactured correctly.
• Design needs to be testable to perform scan. A circuit is “testable” if all
internal nodes of interest can be set to logic 0 or 1, and any change in
the desired logic value at a node of interest, due to a fault, can be
observed externally.
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DFT Basics: Testability Measurement
• Quality of test is measured in terms of coverage.
• Coverage is calculated in two forms: test coverage and fault coverage.
– Test coverage is defined as the percentage of detected faults out of total
detectable faults. This coverage is a more meaningful evaluation for test
pattern quality.
– Fault coverage is defined as the percentage of detected faults out of all
faults, including the undetected faults.
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DFT Basics: Scan Process
Once the FFs are
Every flip-flop in the replaced, they are
design is replaced with stitched together to form
scan-able flop. a long shift register.
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DFT Basics: Scan Process Cont’d
Capture Mode: The
Scan Mode: The scan- design is in functional
mode and scan-enable mode (scan-enable is off)
pins are enabled to shift to capture the functional
data into and out of the response from the
scan cells combinational logic. 7
DFT Basics: Types of Fault
• Stuck-at Fault (SAF) : There are two types of stuck-at faults:
– ST1 fault when the output node is always at logic 1 value even if applied a
logic 0 on the input.
– ST0 fault when the line is applied a logic 1, it produces a logic 0.
• Transition Delay Fault (TDF): The transition-delay fault model is
similar to the stuck-at fault model, except that it attempts to detect slow-
to-rise and slow-to-fall nodes, rather than stuck-at-0 and stuck at-1
nodes.
– A slow-to-rise fault means that a transition from 0 to 1 on the node does not
produce the correct results at the maximum operating speed of the device.
– Similarly, a slow-to-fall fault means that a transition from 1 to 0 on a node
does not produce the correct results at the maximum operating speed of the
device.
– Two vectors (launch & capture) are required to detect slow-to-rise/fall fault;
the APTG process launches a transition with one clock edge and then
captures the effect of that transition with another clock edge.
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DFT Basics: SAF vs TDF
Stuck-at Fault Transition Delay Fault
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1a - DFT Issues & Fixes
>> Derived Clock : It is
generated by a flip-flop,
1a- Derived Clock
a latch, or any internal
clock generator-a PLL,
a frequency divider, or a
pulse generator—in the
circuit.
>> These clocks can
render a large part of
the design un-testable
because you cannot
control the flip-flops
from any primary
input—you cannot scan Example
in values.
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1a - DFT Issues & Fixes Cont’d
>> This problem can
be addressed by
1a- Derived Clock
adding a MUX in front
of the clock pin.
Fixes
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1b - DFT Issues & Fixes
>> Gated clocks are used
to reduce power
consumption by
1b- Gated Clock
temporarily “turning off”
part of the circuit when it
is not in use.
>> It is generated
internally from an external
clock. If the clocks of
these flip-flops cannot be
controlled from primary
inputs, the gated clocks
make it impossible to
scan in data.
>> Solution is ,ORed the
test_enable (TE) port with
enable which makes the Fixes
clock active during shift-
mode.
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2 - DFT Issues & Fixes
>> Internally
Generated
asynchronous set/reset
2 – Asynchronous
signals of scan cells
that are not directly
Set/Reset
controlled from primary
inputs can prevent
scan chains from
shifting data properly.
>> To avoid this
problem, these
asynchronous set/reset
signals are forced to
an inactive state during
the shift operation .
Fixes
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3 - DFT Issues & Fixes
>> Combinational loops
may lead to races, and
results in unpredictable
3 – Combinational
circuit behavior.
Feedback Loop
>> Since the value stored
in the loop cannot be
controlled or determined
during test, this can lead
to an increase in test
generation complexity or
fault coverage loss.
>> The best way is to
rewrite the RTL code.
>> If re-writing the RTL is
not possible then add
controllability in feedback-
loop. Fixes
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4 - DFT Issues & Fixes
>> Bus contention
4 – Bus Contention
occurs when two
drivers are driving
different values on the
same bus.
>> It can cause severe
damage to the chip.
Therefore, you must
prevent bus conflicts
during both normal
operation and scan
operation.
>> Make sure only one
tri-state gate is
selected at any given Example
time during normal
operation.
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4 - DFT Issues & Fixes Cont’d
>> During scan
operation, if the enable
4 – Bus Contention
signals are derived from
scan flip-flops, it is
possible that a scan
pattern may cause more
than one driver active at
the same time.
>> During the shift
operation, contention
can happen with
continuous 1’s
>> To avoid this problem,
combinational logic
gated with a Scan
Enable signal must be
added to the enable
logic.
When SE = 1 EN1=1, Fixes
EN2=0 and EN3=0 only
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D1 enabled
5 - DFT Issues & Fixes
>> Each bidirectional I/O
5-Bi-Directional IOs
port must be externally
controllable.
>> During the shift
operation, the input/output
tri-state buffer may
become active, resulting in
a conflict if BO and the I/O
port driven by the tester
have opposite logic
values.
>> Solution is to force bi-
directional port to input or
output during scan shift to
avoid contention with the Fixes
tester.
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Tool Usage: DFT Constraints File Format
Type of Ports In RTL Compiler (RC) In Encounter Test (ET)
Test Mode define_dft test_mode -name TM0 -active high assign pin=TM0 test_function= +TI;
scan_mode
Scan Enable define_dft shift_enable -name SE0 -active assign pin=SE0 test_function= +SE;
high scan_en
Asynchronous define_dft test mode -name SRst0 -active assign pin=SRst0 test_function= +SC;
Reset high scan_reset -scan_shift
Clock define_dft test_clock -name SClk0 -period assign pin=SClk0 test_function= -ES;
1000
Scan-in/out define_dft scan_chain -name c0 –sdi scanin\ assign pin=scanin test_function=
Ports –sdo scanout -shift_enable SE0 SI0;
assign pin=scanout test_function=
SO0;
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Tool Usage: Scan-Insertion Flow in RC
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Tool Usage: ATPG Flow (For SAF) in ET
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Tool Usage: ATPG Flow (For TDF) in ET
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Thank You
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