Scan and ATPG Training

Scan basics and DRCs violations

Prepared by
Dr. E.Lakshmi Prasad
DFT Engineer.
Sankalp Semiconductors.

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 Contents
❑ Recap of previous class
❑ Design for Testability Basics
❑ Scan Cells Designs
❑ Scan Architectures
❑ Scan Design Rules
❑ Summary
❑ Assignments

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 Yield and Defect levels

DL = 1 – Y(1-d) DL = defective parts sold

total parts sold
DL = Defect Level
Y = Yield Y = defect free fabricated
d = Test coverage total parts fabricated

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 Functional vs. Structural test
3 8

Functional
Package List
-- 3Declar
+ 5ations
=8
5 0

1 Bit adder with Carry

A
a
Fault list
G r
e s S a s-a-0 a s-a-1
f t b s-a-0 b s-a-1
G

B e s-a-0 e s-a-1
b
f s-a-0 f s-a-1
c C r s-a-0 r s-a-1
t s-a-0 t s-a-1
s s-a-0 s s-a-1
c s-a-0 c s-a-1
16 faults
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Stuck-At Fault Model

• Fault models are

logic targets for
defects.
• A fault is detected:
• When a difference is observed
between a “good” and “faulty”
circuit.

• Most common
fault model:
• Most defects are detected with
the stuck-at fault model.
• A terminal of a gate is
permanently stuck-at 0 or 1.
 What Is Testability? (Cont.)
• The ability to put a design into a known
initial state, and then control and observe
internal signal values

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What Is Testability? (Cont.)

• A highly testable design:

• A circuit that can be placed into a known initial state.
• PIs are controllable.
• POs are observable and measurable.

• Circuit with DFFs replaced with

MUX scan:
• A highly testable design.
 Design For Test (DFT)

➢The act of adding logic / features to

enhance the testability of the design

➢With the incorporation of DFT, the IC

has 2 modes of operation
➢Test mode
➢Functional mode

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 Why Design-for-Test?

• Increased Productivity:
• Shorter time-to-market
• Reduced design cycle
• Reduced cost

• Improved Quality:
• Reduced Defects per million (DPM)
• Improved quality of test

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 Design for Testability Basics
❑ Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
❑ Ad hoc DFT
▪ Effects are local and not systematic
▪ Not methodical
▪ Difficult to predict
❑A structured DFT
▪ Easily incorporated and budgeted
▪ Yield the desired results
▪ Easy to automate
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 Ad Hoc Approach
❑ Typical ad hoc DFT techniques
▪ Insert test points
▪ Avoid asynchronous set/reset for storage
elements
▪ Avoid combinational feedback loops
▪ Avoid redundant logic
▪ Avoid asynchronous logic
▪ Partition a large circuit into small blocks

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 Ad Hoc Approach – Test Point
Insertion
Logic circuit
.
Low-observability node B

.
Low-observability node A .
Low-observability node C

OP1 OP2 OP3

DI
DI DI OP2 shows the
SI SO SI 0 SO SI SO structure of an
1
1 D Q OP output
SE SE observation,
SE which is
SE . . . . composed of a
CK
Observation shiftregister multiplexer
(MUX) and a D
flip-flop.
Observation point insertion

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 Ad Hoc Approach – Test Point Insertion

Logic circuit A MUX is inserted

Low-controllability node B between the source
Source x Destination and destination ends.
Original connection
Low-controllability node C During normal
Low-controllability node A operation, TM = 0,
such that the value
CP1 CP2 CP3 from the source end
DI DI
0 DO DI drives the destination
DO DO end through the 0
1
CP_input SI SO
SI D
Q . SO SI SO port of the MUX.
TM TM TM

. . . During test, TM = 1
TM
CK . such that the value
Control shift register from the D flip-flop
drives the destination
end through the 1
Control point insertion port of the MUX.

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 Ad-Hoc DFT Methods
➢ Good design practices learnt through experience are used
as guidelines:
• Avoid asynchronous (unclocked) feedback.
• Make flip-flops initializable.
• Avoid redundant gates. Avoid large fanin gates.
• Provide test control for difficult-to-control signals.
• Avoid gated clocks.
• Consider ATE requirements (tristates, etc.)
➢ Design reviews conducted by experts or design auditing
tools.
➢ Disadvantages of ad-hoc DFT methods:
• Experts and tools not always available.
• Test generation is often manual with no guarantee of
high fault coverage.
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• Design iterations may be necessary.
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 Structured Approach
❑ Scan design
▪ Convert the sequential design into a scan design
▪ Three modes of operation
– Normal mode
• All test signals are turned off
• The scan design operates in the original functional configuration
– Shift mode
– Capture mode
• In both shift and capture modes, a test mode signal TM is
often used to turn on all test-related fixes

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 Structured Approach - Scan
Design
Assume that a stuck-at
X1 Combinational logic Y1 fault f in the combinational
X2 Y2
0 X3 logic requires the primary
f input X3, flip-flop FF2,
and flip-flop FF3, to be set
0 FF3 to 0, 1, and 0.
Q D
The main difficulty in
1 FF2
testing a sequential circuit
Q D stems from the fact that it
FF1
. is difficult to control and
observe the internal state
Q D
. of the circuit.
CK

Difficulty in testing a sequential circuit

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 Structured Approach - Scan Design
Test stimulus application
n
1 1
Test stimulus Shift register composed of n scan cells Test response

n
Test response upload

1. Converting How to detect stuck-at fault f :

selected storage (1)switching to shift mode and shifting in the desired test
elements in the design stimulus, 1 and 0, to FF2 and FF3, respectively
into scan cells. (2)driving a 0 onto primary input X3
2.. Stitching them (3)switching to capture mode and applying one clock
pulse to capture the fault effect into FF1
together to form scan (4)switching back to shift mode and shifting out the test
chains. response stored in FF1, FF2, and FF3 for comparison with
the expected response.

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 Scan Design
➢ Circuit is designed using pre-specified design rules.
➢ Test structure (hardware) is added to the verified design:
• Add a test control (TC) primary input.
• Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
• Make input/output of each scan shift register
controllable/observable from PI/PO.
➢ Use combinational ATPG to obtain tests for all testable faults in
the combinational logic.
➢ Add shift register tests and convert ATPG tests into scan
sequences for use in manufacturing test.

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 Scan Cell Design
❑A scan cell has two inputs: data input
and scan input
▪ In normal/capture mode, data input is selected to update the
output
▪ In shift mode, scan input is selected to update the output

❑ Three widely used scan cell designs

▪ Muxed-D Scan Cell
▪ Clocked-Scan Cell
▪ LSSD Scan Cell

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 Muxed-D Scan
Cell
This scan cell is composed of a D
DI 0
D Q Q/SO flip-flop and a multiplexer.
SI 1

SE CK
The multiplexer uses an additional
Edge-triggered scan enable input SE to select
muxed-D scan
cell
between the data input DI and the
scan input SI.

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 Muxed-D Scan
Cell In normal/capture mode,
SE is set to 0. The value
CK
present at the data input
DI is captured into the
SE internal D flip-flop when
a rising clock edge is
DI D1 D2 D3 D4 applied.
1 2 3 4

SI T1 T2 T3 T4 In shift mode, SE is set to

1. The scan input SI is
Q/SO D1 T3
used to shift in new data
1 to the D flip-flop, while
the content of the D flip-
Edge-triggered muxed-D scan cell flop is being shifted out.
design and operation

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 Muxed-D Scan
Cell
This scan cell is composed of a
DI
SI
0
1
D Q . Q
multiplexer, a D latch, and a D
flip-flop.
CK
SE D Q SO In this case, shift operation is
conducted in an edge-triggered
CK . manner, while normal operation
and capture operation is
conducted in a level-sensitive
manner.
Level-sensitive/edge-triggered
muxed-D scan cell design

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 Scan Flip-Flop (SFF)
SD Master latch Slave latch
SE
Logic Q
overhead

MUX
D Q

CK D flip-flop

CK Master open Slave open

t

SE Scan mode, SD selected Normal mode, D selected

t

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 Clocked-Scan Cell

DI In the clocked-scan
Q/SO
SI cell, input selection is
conducted using two
DCK SCK independent clocks,
DCK and SCK.
Clocked-scan cell

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 Clocked-Scan
Cell
In normal/capture mode,
the data clock DCK is used
to capture the contents
present at the data input DI
into the clocked-scan cell.

In shift mode, the shift

clock SCK is used to shift
in new data from the scan
input SI into the clocked -
scan cell, while the content
of the clocked-scan cell is
Clocked-scan cell design and being shifted out.
operation

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 LSSD Scan Cell
An LSSD scan cell is
used for level-sensitive
SRL latch base designs.
D . . .
L1
+L1
This scan cell contains
C . two latches, a master 2-
port D latch L1 and a slave
I . .
L2
+L 2 D latch L2. Clocks C,
A and B are used to select
A . . between the data input D
and the scan input I to
B drive +L1 and +L2. In an
LSSD design, either +L1
or +L2 can be used to
Polarity-hold SRL drive the combinational
(shift register latch) logic of the design.

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 LSSD Scan Cell
C In order to guarantee race-free
operation, clocks A, B, and C are
A applied in a non-overlapping
manner.
B

D D1 D2 D3 D4 The master latch L1 uses the system

1 2 3 4 clock C to latch system data from the
I T1 T2 T3 T4 data input D and to output this data
onto +L1. Clock B is used after clock
+L1 D1 T3 A to latch the system data from latch
1
L1 and to output this data onto +L2.
+L2 T3

Polarity-hold SRL design and

operation

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 Comparing three scan cell designs
Advantages Disadvantages

Muxed-D Scan Compatibility to modern Add a multiplexer

Cell designs delay
Comprehensive support provided
by existing design automation
tools
Clocked-Scan No performance degradation Require additional shift
Cell clock routing

LSSD Scan Insert scan into a latch-based Increase routing

Cell design complexity
Guarantee to be race-free

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 ScanArchitectures
❑ Full-Scan Design
▪ All or almost all storage element are converted into scan cells
and combinational ATPG is used for test generation
❑ Partial-Scan Design
▪ A subset of storage elements are converted into scan cells
and sequential ATPG is typically used for test generation
❑ Random-Access Scan Design
▪ A random addressing mechanism, instead of serial scan
chains, is used to provide direct access to read or write any
scan cell

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 Full-Scan Design
❑ All storage elements are replaced with scan cells
▪ All inputs can be controlled
▪ All outputs can be observed
❑ Advantage:
▪ Converts sequential ATPG into combinational ATPG
❑ Almost full-scan design
▪ A small percentage of storage elements are not replaced
with scan cells
– For performance reasons
• Storage elements that lie on critical paths
– For functional reasons
• Storage elements driven by a small clock domain that are
deemed too insignificant to be worth the additional scan
insertion effort

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 Muxed-D Full-Scan Design
X1 Y1
X2
X3 Combinational logic Y2 The three D flip-
FF1 FF2 FF3 flops, FF1, FF2 and
DQ D Q DQ FF3, are replaced
CK . . with three muxed-D
scan cells, SFF1,
SFF2 and SFF3,
respectively.
Sequential circuit example

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 Adding Scan Structure
PI PO

Combinational SFF SCANOUT

logic SFF

SFF

TC or TCK Not shown: CK or

SCANIN MCK/SCK feed all
SFFs.
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 Muxed-D Full-Scan Design
X1 Y1
To form a scan chain,
PI X2
Y2
PO the scan input SI of
X3 Combinational logic
SFF2 and SFF3 are
PPI PPO
connected to the output
Q of the previous scan
cell, SFF1 and SFF2,
SFF1 SFF2 SFF3
respectively. In
DI DI DI
SI SI Q . SI Q . SI Q . SO addition, the scan input
SE SE SE SI of the first scan cell
SE
CK
. . . . SFF1 is connected to
the primary input SI,
and the output Q of the
last scan cell SFF3 is
(a) Muxed-D full-scan circuit connected to the
primary output SO.

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 Muxed-D Full-Scan
Design
PI V1: PI V2: PI

SE
S H C H S H C
CK
SFF1.Q 0 1 1 1 L L 1 0 1 1 L
SFF2.Q X 0 1 1 H H L 1 0 0 L
SFF3.Q X X 0 0 L L H L 1 1 H

V1: PPI V2: PPI

PO PPO
observation observation

S: shift operation / C: capture operation / H: hold cycle

(b) Test operations

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 Muxed-D Full-ScanDesign
• Primary inputs (PIs) • Primary outputs (POs)
– the external inputs to the – the external outputs of the
circuit circuit
– can be set to any required logic – can be observed
values – are observed directly in
– set directly in parallel from the – parallel from the external
external inputs outputs
• Pseudo primary inputs
• Pseudo primary
(PPIs) outputs (PPOs)
– the scan cell outputs
– the scan cell inputs
– can be set to any required logic
values – can be observed
– are set serially through scan – are observed serially through
chain inputs scan chain outputs

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 Comb. Test Vectors

PI I1 I2 O1 O2 PO

Combinational
SCANIN SCANOUT
TC
logic
Present Next
S1 S2 N1 N2 state
state

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 Comb. Test Vectors
Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2
TC 0000000 1 0000000 1 0000000

PO O1 O2

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops
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 Testing Scan Register
➢ Scan register must be tested prior to application of
scan test sequences.
➢ A shift sequence 00110011 . . . of length nsff+4 in scan
mode (TC=0) produces 00, 01, 11 and 10 transitions in
all flip-flops and observes the result at SCANOUT
output.
➢ Total scan test length: (ncomb + 1) nsff + ncomb + nsff + 4 clock periods.
• Example: 2,000 scan flip-flops, 500 comb. vectors, total
scan test length ~ 106 clocks.
• Multiple scan registers reduce test length.

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 Multiple Scan Registers
➢ Scan flip-flops can be distributed among any
number of shift registers, each having a separate
scanin and scanout pin.
➢ Test sequence length is determined by the longest
scan shift register.
➢ Just one test control (TC) pin is essential.

PI/SCANIN PO/
Combinational M SCANOUT
logic U
SFF X

SFF
SFF
TC

CK
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 Scan Overheads
• IO pins: One pin necessary.
• Area overhead:
• Gate overhead = [4 nsff/(ng+10nsff)] x 100%, where ng =
comb. gates; nff = flip-flops; Example – ng = 100k gates,
nsff = 2k flip-flops, overhead = 6.7%.
• More accurate estimate must consider scan wiring and
layout area.
• Performance overhead:
• Multiplexer delay added in combinational path;
approx. two gate-delays.
• Flip-flop output loading due to one additional fanout;
approx. 5-6%.

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 Hierarchical Scan
• Scan flip-flops are chained within subnetworks
before chaining subnetworks.
• Advantages:
• Automatic scan insertion in netlist
• Circuit hierarchy preserved – helps in debugging and design
changes
• Disadvantage: Non-optimum chip layout.

Scanin Scanout
SFF1 SFF4
SFF1 SFF3
Scanin
Scanout
SFF2 SFF3 SFF4 SFF2
Hierarchical netlist Flat layout
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 Optimum Scan Layout
X’
X

IO SFF
pad cell

SCANIN
Flip-
flop
cell
Y Y’

TC SCAN
OUT

Routing
channels
Interconnects Active areas: XY and X’Y’

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 Scan Area Overhead
Linear dimensions of active area:
X = (C + S) / r y = track dimension, wire
X’ = (C + S + aS) / r width+separation
Y’ = Y + ry = Y + Y(1 – b) / T C = total comb. cell width
S = total non-scan FF cell
Area overhead width
X’Y’ – XY s = fractional FF cell area
= ─────── × 100% = S/(C+S)
XY a = SFF cell width fractional
increase
1–b
r = number of cell rows
= [(1+as)(1+ ─── ) – 1] x 100% or routing channels
T b = routing fraction in active
area
1–b T = cell height in track
dimension y
= (as + ──── ) x 100%
T
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 Example: Scan Layout
• 2,000-gate CMOS chip
• Fractional area under flip-flop cells, s = 0.478
• Scan flip-flop (SFF) cell width increase, a = 0.25
• Routing area fraction, b = 0.471
• Cell height in routing tracks, T = 10
• Calculated overhead = 17.24%
• Actual measured data:
Scan implementation Area overhead Normalized clock rate
______________________________________________________________________

None 0.0 1.00

Hierarchical 16.93% 0.87

Optimum layout 11.90% 0.91

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 ATPG Example: S5378
Original Full-scan

Number of combinational gates 2,781 2,781

Number of non-scan flip-flops (10 gates each) 179 0
Number of scan flip-flops (14 gates each) 0 179
Gate overhead 0.0% 15.66%
Number of faults 4,603 4,603
PI/PO for ATPG 35/49 214/228
Fault coverage 70.0% 99.1%
Fault efficiency 70.9% 100.0%
CPU time on SUN Ultra II, 200MHz processor 5,533 s 5s
Number of ATPG vectors 414 585
Scan sequence length 414 105,662

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 Timing and Power
• Small delays in scan path and clock skew
can cause race condition.
• Large delays in scan path require slower
scan clock.
• Dynamic multiplexers: Skew between TC
and TC signals can cause momentary
shorting of D and SD inputs.
• Random signal activity in combinational
circuit during scan can cause excessive
power dissipation.
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Muxed-D Full-Scan Design

Circuit Scan cell TM SE

Operation type mode

Normal Normal 0 0

Shift Shift 1 1
Operation

Capture Capture 1 0
Operation

Circuit operation type and scan cell mode

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 Clocked Full-Scan Design
In a muxed-D full-
X1 Y1 scan circuit, a scan
PI X2 PO enable signal SE is
X3 Combinational logic Y2
PPI PPO used.

In a clocked full-
scan design, two
SFF1 SFF2 SFF3 operations are
DI DI DI
SI SI Q . SI Q . SI Q . SO
distinguished by
DCK SCK DCK SCK DCK SCK properly applying
DCK . . . . the two independent
SCK clocks SCK and
DCK during shift
mode and capture
Clocked full-scan circuit mode.

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 LSSD Full-Scan Design
❑ Single-latch design
❑ Double-latch design

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 LSSD Full-Scan Design
X1 X3 The output port
Combinational logic 1 Combinational logic 2 Y2
X2 Y1 +L1 of the master
latch L1 is used to
SRL1 SRL2 SRL3
drive the
D D D combinational
SI I +L2 I +L2 I +L2 SO
C C C
logic of the
A +L1
B
A +L1
B
A +L1
B
design. In this
C1 .. .. case, the slave
A
B
. latch L2 is only
C2
used for scan
testing.
Single-latch design

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 In normal mode, the C1
LSSD Full-Scan Design and C2 clocks are used
in a non-overlapping
Manner.
During the shift
X1 Y1 operation, clocks A and
X2 Combinational logic
X3 Y2 B are applied in a non-
overlapping manner,
SRL1 SRL2 SRL3 the scan cells SRL1 ~
D D D SRL3 form a single
SI I +L2 . I +L2 . I +L2 . SO
scan chain from SI to
C C C
A +L1 A +L1 A +L1 SO.
B B B
During the capture
C1 .. .. operation, clocks C 1
A
C2 or B . . and C2 are applied to
load the test response
from the combinational
Double-latch design logic into the scan
cells.

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 LSSD Design Rules
❑ All storage elements must be polarity-hold latches.
❑ The latches are controlled by two or more non-
overlapping clocks.
❑ A set of clock primary inputs must follow three
conditions:
▪ All clock inputs to SRLs must be inactive when clock PIs are
inactive
▪ The clock input to any SRL must be controlled from one or
more clock primary inputs
▪ No clock can be ANDed with another clock or its
complement

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 LSSD Design Rules
❑ Clock primary inputs must not feed the data inputs to
SRLs either directly or through combinational logic.
❑ Each system latch must be part of an SRL, and each
SRL must be part of a scan chain.
❑ A scan state exists under certain conditions:
▪ Each SRL or scan out SO is a function of only the preceding
SRL or scan input SI in its scan chain during the scan
operation
▪ All clocks except the shift clocks are disabled at the SRL
clock inputs

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 Partial-Scan Design
❑ Was once used in the industry long before
full-scan design became the dominant scan
architecture.
❑ Can also be implemented using muxed-D
scan cells, clocked-scan cells, or LSSD scan
cells.
❑ Either combinational ATPG or sequential
ATPG can be used.

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 Partial-Scan Design
A scan chain is onstructed
X1 Y1 with two scan cells SFF1 and
PI X2 PO
X3 Combinational logic Y2 SFF3, while flip-flop FF2 is
PPI PPO left out.
It is possible to reduce the test
generation complexity by
SFF1
. FF2 SFF3
splitting the single clock into
DI DI
two separate clocks, one for
SI SI Q DI Q SI Q . SO controlling all scan cells, the
SE SE other for controlling all non-
SE
CK
. . . scan storage elements.
However, this may result in
additional complexity of
routing two separate clock
An example of muxed-D partial- trees during physical
scan design implementation.

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 Partial-Scan Design
❑ Scan cell selection
▪ A functional partitioning approach
– A circuit is composed of a data path portion and a control portion
– Storage elements on the data path are left out of the scan cell
replacement process
– Storage elements on the control path can be replaced with scan cells
▪ A pipelined or feed-forward partial-scan design approach
– Make the sequential circuit feedback-free by selecting the storage
elements to break all sequential feedback loops
– First construct a structure graph for the sequential circuit
▪ A balanced partial-scan design approach
– Use a target sequential depth to simply the test generation process for
the pipelined or feed-forward partial-scan design

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 Partial-Scan Design - Structure Graph
❑A feedback-free sequential circuit
▪ Use a directed acyclic graph (DAG)
▪ The maximum level in the structure graph
is referred to as sequential depth
❑A sequential circuit containing feedback
loops
▪ Use a directed cyclic graph (DCG)

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 Sequential circuit and its structure
graph
C1 FF3 C3 FF5 1 3 5
FF1

FF2 C2
2 4
FF4

(a) Sequential Circuit (b) Structure graph

Sequential depth is 3
The sequential depth of a circuit is equal to the maximum number of clock
cycles that needs to be applied in order to control and observe values to and
from all non-scan storage elements
• The sequential depth of a full-scan circuit is 0

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 Partial-Scan Design
❑ Advantage:
▪ Reduce silicon area overhead
▪ Reduce performance degradation
❑ Disadvantage:
▪ Can result in lower fault coverage
▪ Longer test generation time
▪ Offers less support for debug, diagnosis
and failure analysis

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 Random-Access Scan Design
❑ Advantages of RAS:
▪ Can control or observe individual scan cells without affecting
others
▪ Reduce test power dissipation
▪ Simplify the process of performing delay test
❑ Disadvantages of traditional RAS:
▪ High overhead in scan design and routing
▪ No guarantee to reduce the test application time
❑ Progressive Random-Access Scan( PRAS )
was proposed to alleviate the disadvantages
in traditional RAS

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 Traditional random-access scan
architecture
PI Combinational logic PO
All scan cells are
organized into a
SC SC … SC two-dimensional
Row (X) decoder CK array. A ┌ log2n ┐ -
SC SC … SC SI bit address shift
SCK register, where n is
…

…
…
SO the total number of
SC SC … SC scan cells, is used to
specify which scan
Column (Y) decoder cell to access.
Address shift register AI

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 Progressive Random-Access Scan
(PRAS)
Structure is similar to that of a static
SD SD
random access memory (SRAM) cell
or a grid addressable latch.
RE
Ф Ф In normal mode, all horizontal row
D Q enable (RE) signals are set to 0,
Ф Ф Ф Ф forcing each scan cell to act as a
normal D flip-flop.

In test mode, to capture the test

response from D, the RE signal is set
PRAS scan cell design to 0 and a pulse is applied on clock
Φ, which causes the value on D to be
loaded into the scan cell.

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 Progressive Random-Access Scan
(PRAS)
Sense-amplifiers & MISR PO
… Rows are enabled in a
… fixed order.

Row enable shift register

SC SC SC

Combinational logic
SC SC … SC
It is only necessary to
…
…

…
supply a column address
… SC
SC SC
to specify which scan cell
…
Column line drivers PI
in an enabled row to
TM
SI/SO
Test
control … access.
CK logic Column address decoder

CA

PRAS Architecture

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 PRAS - test procedure
for each test vector vi (i = 1, 2, …, N) {
/* Test stimulus application */
For each test
/* Test response compression */ vector, the test
enable TM;
for each row rj (j = 1, 2, …, m) {
stimulus
read all scan cells in rj / update MISR; application and
for each scan cell SC in rj
/* v(SC): current value of SC */
test response
/* vi(SC): value of SC in vi */ compression are
if v(SC)  vi(SC)
update SC;
conducted in an
} interleaving
/* Test response acquisition */
disable TM;
manner when the
apply the normal clock; test mode signal
}
scan-out MISR as the final test response;
TM is enabled.

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 Scan Design Rules

➢ Use only clocked D-type of flip-flops for all state

variables.
➢ At least one PI pin must be available for test; more
pins, if available, can be used.
➢ All clocks must be controlled from PIs.
➢ Clocks must not feed data inputs of flip-flops.

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Summary
• Scan area overhead and delay overhead after converting FFs into
scannable FFs
• Types of scan cells and its operation
• Types of scan insertions
• Hierarchal vs flat scan insertion
• Scan operations with examples
• Basic approach for scan design
• Understanding of test sequence length
• Full scan design vs partial scan design

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Assignment
1. Estimate the total number of test clock cycles for completing the scan
operation. Number of scan patterns are 10, number of FFs are 70.
2. Estimate the total number of test clock cycles for completing the scan
operation. Number of patterns (which includes both s@ and chain test
patterns) are 80, number of FFs are 200.
3. What are the essential inputs and outputs for scan?
4. Why clock must be used as primary input in DFT?
5. What is the role of scan enable?
6. What are the basic three operations of scan?
7. List out advantages and disadvantages of three types of scan cells.

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Assignment
1. Draw the waveform of Mux-D scan cell operation.
2. What is the importance test mode or scan mode?
3. Illustrate the complete scan operation with an example.
4. Why function clock frequency is not used as scan clock frequency for
measuring the S@ faults?
5. What is meant by sequential depth in DFT?
6. How to improve coverage in the partial scan designs?
7. Estimate the total number of shift cycles (load/unload) are required for
the following specifications:
Number of patterns= 45
Number of FFs=500.
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Conti..
• Estimate the number of clock cycles required for measuring the S@0
for the following diagram. Pattern=1100

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Conti…
• Identify the mismatch occur at which FF for the following
specifications ( hint: sequential test length cycle formula)
Number of patterns=5
Each test clock cycle period =100ns
Total scan chain length= 10 FF
Mismatch occurred at 1600ns pattern 1
Mismatch occurred at 1400ns pattern 1
Mismatch occurred at 3400ns pattern 3
Mismatch occurred at 4700ns pattern 4

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