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Ecl202 - Digital Circuits: Exercise No.4

The document outlines 14 exercises related to digital circuits including: 1. Designing a 4-bit magnitude comparator circuit to compare two 4-bit numbers and indicate which is greater. 2. Drawing the logic circuit of a 2x4 decoder with an enable input and explaining how it can be used to design a 3x8 decoder. 3. Explaining the working principle of a 4x1 multiplier and designing a 4x1 multiplexer. 4. Designing a circuit to generate the parity bit for BCD coded digits and produce an error signal for non-BCD digits using NAND-NAND logic.

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Shubham Chomal
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58 views2 pages

Ecl202 - Digital Circuits: Exercise No.4

The document outlines 14 exercises related to digital circuits including: 1. Designing a 4-bit magnitude comparator circuit to compare two 4-bit numbers and indicate which is greater. 2. Drawing the logic circuit of a 2x4 decoder with an enable input and explaining how it can be used to design a 3x8 decoder. 3. Explaining the working principle of a 4x1 multiplier and designing a 4x1 multiplexer. 4. Designing a circuit to generate the parity bit for BCD coded digits and produce an error signal for non-BCD digits using NAND-NAND logic.

Uploaded by

Shubham Chomal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ECL202 - DIGITAL CIRCUITS

Exercise No.4
1. Draw the complete logic circuit of 4-bit magnitude comparator using combinational circuit

which can compare two binary numbers R = R4R3R2R1 and S = S4S3S2S1 and give the result

whether R is greater than S or not.

2. Draw the logic circuit of a 2x4 decoder using enable input and briefly explain its operation.

Show how a 3x8 decoder can be designed using 2x4 decoders. Draw the truth tables. Discuss

the salient applications of decoder in digital circuits.

3. Draw the logic diagram of a 4x1 multiplier and explain its working principle. Hence, design a

multiplexer which can select one 4-bit input out of 4-bit inputs and directs the selected input

to the output terminals.

4. Design a combination of circuit to generate the parity bit for digits coded in BCD code. The

circuit should also have an additional output that produces an error signal if a non-BCD digit

is input to the circuit. Realize the circuit using NAND-NAND logic.

5. Show how 2 to 1 multiplexers can be used to implement a half-adder.

6. Design a look ahead carry full adder (4-bit).

7. Design a full Subtractor using two half adders.

8. Design a combinational circuit that accepts a three bit number and generates an output

binary equal to the square of the input number.

9. Show how a full-adder can be converted to a full-Subtractor with the addition of one inverter

circuit.

10. Design an excess-3 to BCD code converter using a 4-bit full adders MSI circuit.

11. Design a combinational circuit that generates the 9’s complement of a BCD digit.

12. Implement the following function using 4x1 multiplexer:


F(A,B,C) = ∑ (1,3,5,6)

13. Explain briefly the working principle of diode matrix.

14. Draw the logic diagram of a ROM built around OR gate encoder which can store the
following 6 binary words:

1 1 0 1

1 1 1 1

1 0 0 1

0 0 1 1

0 1 1 1

1 0 1 1

If a decoder is include, then what will be the number of address lines, required to read a word
from the memory? In the logic diagram, included decoder for addressing purposes.

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