19-3711; Rev 0; 5/05

High-Efficiency, Quad-Output, Main Power-

Supply Controllers for Notebook Computers
General Description Features

MAX8732A/MAX8733A/MAX8734A
The MAX8732A/MAX8733A/MAX8734A dual step-down, ♦ No Current-Sense Resistor Needed (MAX8734A)
switch-mode power-supply (SMPS) controllers generate ♦ Accurate Current Sense with Current-Sense
logic-supply voltages in battery-powered systems. The Resistor (MAX8732A/MAX8733A)
MAX8732A/MAX8733A/MAX8734A include two pulse- ♦ 1.5% Output Voltage Accuracy
width modulation (PWM) controllers, adjustable from 2V to
5.5V or fixed at 5V and 3.3V. These devices feature two ♦ 3.3V and 5V 100mA Bootstrapped Linear
linear regulators providing 5V and 3.3V always-on out- Regulators
puts. Each linear regulator provides up to 100mA output ♦ Internal Soft-Start and Soft-Stop Output
current with automatic linear-regulator bootstrapping to Discharge
the main SMPS outputs. The MAX8732A/MAX8733A/ ♦ Quick-PWM with 100ns Load Step Response
MAX8734A include on-board power-up sequencing, a ♦ 3.3V and 5V Fixed or Adjustable Outputs
power-good (PGOOD) output, digital soft-start, and inter- (Dual Mode™)
nal soft-stop output discharge that prevents negative volt-
ages on shutdown. Additionally, the outputs are high ♦ 4.5V to 24V Input Voltage Range
impedance when VCC falls below its UVLO set point while ♦ Enhanced Ultrasonic Pulse-Skipping Mode
the outputs are enabled. (25kHz min)
Maxim’s proprietary Quick-PWM™ quick-response, con- ♦ Power-Good (PGOOD) Signal
stant on-time PWM control scheme operates without ♦ Overvoltage Protection Enable/Disable
sense resistors and provides 100ns response to load tran-
sients while maintaining a relatively constant switching fre- Ordering Information
quency. The unique ultrasonic pulse-skipping mode 5V/3.3V
maintains the switching frequency above 25kHz, which PIN- SWITCHING
eliminates noise in audio applications. Other features PART TEMP RANGE
PACKAGE FREQUENCY
include pulse skipping, which maximizes efficiency in (kHz)
light-load applications, and fixed-frequency PWM mode, MAX8732AEEI+ -40°C to +85°C 28 QSOP 200/300
which reduces RF interference in sensitive applications.
MAX8732AEEI -40°C to +85°C 28 QSOP 200/300
The MAX8732A features a 200kHz/5V and 300kHz/3.3V MAX8733AEEI+ -40°C to +85°C 28 QSOP 400/500
SMPS for highest efficiency, while the MAX8733A fea-
tures a 400kHz/5V and 500kHz/3.3V SMPS for “thin and MAX8733AEEI -40°C to +85°C 28 QSOP 400/500
light” applications. The MAX8734A provides a pin- Ordering Information continued at end of data sheet.
selectable switching frequency, allowing either 200kHz/ +Denotes lead-free package.
300kHz or 400kHz/500kHz operation of the 5V/3.3V
SMPSs, respectively. The MAX8732A/MAX8733A/
Pin Configurations
MAX8734A are available in 28-pin QSOP packages and TOP VIEW
operate over the extended temperature range N.C. 1 28 BST3
(-40°C to +85°C). PGOOD 2 27 LX3
The MAX8732A/MAX8733A/MAX8734A are pin-for-pin ON3 3 26 DH3
upgrades to the MAX1777/MAX1977/MAX1999. ON5 4 25 LDO3
The MAX1999 evaluation kit (EV kit) can be used to ILIM3 5 24 DL3
evaluate the MAX8732A/MAX8733A/MAX8734A. SHDN 6
MAX8734A
23 GND

Applications FB3 7 22 OUT3

REF 8 21 OUT5
Notebook and Subnotebook Computers FB5 9 20 V+
PDAs and Mobile Communication Devices PRO 10 19 DL5

3- and 4-Cell Li+ Battery-Powered Devices ILIM5 11 18 LDO5

SKIP 12 17 VCC

TON 13 16 DH5
Quick-PWM and Dual Mode are trademarks of Maxim BST5 14 15 LX5
Integrated Products, Inc.
QSOP
Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
MAX8732A/MAX8733A/MAX8734A

V+, SHDN to GND ..................................................-0.3V to +25V LDO3, LDO5, REF Short Circuit to GND ....................Momentary
BST_ to GND ..........................................................-0.3V to +30V LDO3 Current (internal regulator) Continuous................+100mA
LX_ to BST_ ..............................................................-6V to +0.3V LDO3 Current (switched over to OUT3) Continuous ......+200mA
CS_ to GND (MAX8732A/MAX8733A only) .................-2V to +6V LDO5 Current (internal regulator) Continuous................+100mA
VCC, LDO5, LDO3, OUT3, OUT5, ON3, ON5, REF, LDO5 Current (switched over to OUT5) Continuous ......+200mA
FB3, FB5, SKIP, PRO, PGOOD to GND ...............-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
DH3 to LX3 ..............................................-0.3V to (VBST3 + 0.3V) 28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW
DH5 to LX5 ..............................................-0.3V to (VBST5 + 0.3V) Operating Temperature Range ...........................-40°C to +85°C
ILIM3, ILIM5 to GND...................................-0.3V to (VCC + 0.3V) Junction Temperature ......................................................+150°C
DL3, DL5 to GND....................................-0.3V to (VLDO5 + 0.3V) Storage Temperature Range .............................-65°C to +150°C
TON to GND (MAX8734A only) ................................-0.3V to +6V Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAIN SMPS CONTROLLERS
LDO5 in regulation 6 24
V+ Input Voltage Range V
V+ = LDO5, VOUT5 < 4.43V 4.5 5.5
3.3V Output Voltage in
V+ = 6V to 24V, FB3 = GND, V SKIP = 5V 3.285 3.330 3.375 V
Fixed Mode
V+ = 6V to 24V, FB5 = GND, V SKIP = 5V,
MAX8732A/MAX8734A (TON = VCC)
5V Output Voltage in Fixed Mode 4.975 5.050 5.125 V
V+ = 7V to 24V, FB5 = GND, V SKIP = 5V,
MAX8733A/MAX8734A (TON = GND)
Output Voltage in
V+ = 6V to 24V, either SMPS 1.975 2.00 2.025 V
Adjustable Mode
Output Voltage Adjust Range Either SMPS 2.0 5.5 V
FB3, FB5 Adjustable-Mode
Dual-Mode comparator 0.1 0.2 V
Threshold Voltage
Either SMPS, V SKIP = 5V, 0 to 5A -0.1
DC Load Regulation Either SMPS, SKIP = GND, 0 to 5A -1.5 %
Either SMPS, V SKIP = 2V, 0 to 5A -1.7
Line Regulation Either SMPS, 6V < V+ < 24V 0.005 %/V
Current-Limit Threshold ILIM_ = VCC, GND - CS_ (MAX8732A/MAX8733A),
93 100 107 mV
(Positive, Default) GND - LX_ (MAX8734A)

GND - CS_ VILIM_ = 0.5V 40 50 60

Current-Limit Threshold
(MAX8732A/MAX8733A), VILIM_ = 1V 93 100 107 mV
(Positive, Adjustable)
GND - LX_ (MAX8734A) VILIM_ = 2V 185 200 215
SKIP = GND, ILIM_ = VCC, GND - CS_
Zero-Current Threshold 3 mV
(MAX8732A/MAX8733A), GND - LX_ (MAX8734A)
Current-Limit Threshold SKIP = ILIM_ = VCC, GND - CS_
-120 mV
(Negative, Default) (MAX8732A/MAX8733A), GND - LX_ (MAX8734A)
Soft-Start Ramp Time Zero to full limit 1.7 ms

2 _______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)

MAX8732A/MAX8733A/MAX8734A
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAX8732A or MAX8734A 5V SMPS 200
(VTON = 5V), SKIP = VCC 3.3V SMPS 300
Operating Frequency MAX8733A or MAX8734A 5V SMPS 400 kHz
(VTON = 0), SKIP = VCC 3.3V SMPS 500
SKIP = REF 25 36
MAX8732A or MAX8734A VOUT5 = 5.05V 1.895 2.105 2.315
(VTON = 5V) VOUT3 = 3.33V 0.833 0.925 1.017
On-Time Pulse Width µs
MAX8733A or MAX8734A VOUT5 = 5.05V 0.895 1.052 1.209
(VTON = 0) VOUT3 = 3.33V 0.475 0.555 0.635
Minimum Off-Time 250 300 350 ns
MAX8732A or MAX8734A VOUT5 = 5.05V 94
(VTON = 5V) VOUT3 = 3.33V 91
Maximum Duty Cycle %
MAX8733A or MAX8734A VOUT5 = 5.05V 88
(VTON = 0) VOUT3 = 3.33V 85
INTERNAL REGULATOR AND REFERENCE
LDO5 Output Voltage ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO5 < 100mA 4.90 5.00 5.10 V
LDO5 Short-Circuit Current LDO5 = GND 190 mA
LDO5 Undervoltage-Lockout
Falling edge of LDO5, hysteresis = 1% 3.7 4.0 4.3 V
Fault Threshold
Falling edge of OUT5, rising edge at OUT5 regulation
LDO5 Bootstrap Switch Threshold 4.43 4.56 4.69 V
point
LDO5 Bootstrap
LDO5 to OUT5, VOUT5 = 5V 1.4 3.2 Ω
Switch Resistance
LDO3 Output Voltage ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO3 < 100mA 3.28 3.35 3.42 V
LDO3 Short-Circuit Current LDO3 = GND 180 mA
Falling edge of OUT3, rising edge at OUT3 regulation
LDO3 Bootstrap Switch Threshold 2.80 2.91 3.02 V
point
LDO3 Bootstrap Switch
LDO3 to OUT3, VOUT3 = 3.2V 1.5 3.5 Ω
Resistance
REF Output Voltage No external load 1.980 2.000 2.020 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current REF in regulation 10 µA
V+ Operating Supply Current LDO5 switched over to OUT5, 5V SMPS 25 50 µA
V+ Standby Supply Current V+ = 6V to 24V, both SMPSs off, includes ISHDN 150 250 µA
V+ Shutdown Supply Current V+ = 4.5V to 24V 6 15 µA
Both SMPSs on, FB3 = FB5 = SKIP = GND, VOUT3 =
Quiescent Power Consumption 3 4.5 mW
3.5V, VOUT5 = 5.3V
FAULT DETECTION
Overvoltage Trip Threshold FB3 or FB5 with respect to nominal regulation point +8 +11 +14 %

_______________________________________________________________________________________ 3
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
MAX8732A/MAX8733A/MAX8734A

(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Overvoltage Fault
FB3 or FB5 delay with 50mV overdrive 10 µs
Propagation Delay
FB3 or FB5 with respect to nominal output, falling edge,
PGOOD Threshold -12 -9.5 -7 %
typical hysteresis = 1%
PGOOD Propagation Delay Falling edge, 50mV overdrive 10 µs
PGOOD Output Low Voltage ISINK = 4mA 0.3 V
PGOOD Leakage Current High state, forced to 5.5V 1 µA
o
Thermal-Shutdown Threshold +160 C
Output Undervoltage
FB3 or FB5 with respect to nominal output voltage 65 70 75 %
Shutdown Threshold
Output Undervoltage
From ON_ signal 10 22 35 ms
Shutdown Blanking Time
INPUTS AND OUTPUTS
Feedback Input Leakage Current VFB3 = VFB5 = 2.2V -200 +40 +200 nA
Low level 0.6
PRO Input Voltage V
High level 1.5
Low level 0.8
SKIP Input Voltage Float level 1.7 2.3 V
High level 2.4
Low level 0.8
TON Input Voltage V
High level 2.4
Clear fault level/SMPS off level 0.8
ON3, ON5 Input Voltage Delay start level 1.7 2.3 V
SMPS on level 2.4
V PRO or VTON = 0 or 5V -1 +1
VON_ = 0 or 5V -2 +2
V SKIP = 0 or 5V -1 +1
Input Leakage Current µA
V SHDN = 0 or 24V -1 +1
VCS_ = 0 or 5V -2 +2
VILIM3, VILIM5 = 0 or 2V -0.2 +0.2
Rising edge 1.2 1.6 2.0
SHDN Input Trip Level V
Falling edge 0.96 1.00 1.04
DH_ Gate-Driver
DH3, DH5 forced to 2V 2 A
Sink/Source Current
DL_ Gate-Driver Source Current DL3 (source), DL5 (source), forced to 2V 1.7 A
DL_ Gate-Driver Sink Current DL3 (sink), DL5 (sink), forced to 2V 3.3 A
DH_ Gate-Driver On-Resistance BST - LX_ forced to 5V 1.5 4.0 Ω
DL_, high state (pullup) 2.2 5.0
DL_ Gate-Driver On-Resistance Ω
DL_, low state (pulldown) 0.6 1.5

4 _______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)

MAX8732A/MAX8733A/MAX8734A
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

OUT3, OUT5 Discharge-Mode
12 40 Ω
On-Resistance
OUT3, OUT5 Discharge-Mode
Synchronous Rectifier 0.2 0.3 0.4 V
Turn-On Level

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = V CC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAIN SMPS CONTROLLERS
LDO5 in regulation 6 24
V+ Input Voltage Range V
V+ = LDO5, VOUT5 < 4.41V 4.5 5.5
3.3V Output Voltage in
V+ = 6V to 24V, FB3 = GND, V SKIP = 5V 3.27 3.39 V
Fixed Mode
V+ = 6V to 24V, FB5 = GND, V SKIP = 5V,
MAX8732A/MAX8734A (TON = VCC)
5V Output Voltage in Fixed Mode 4.95 5.15 V
V+ = 7V to 24V, FB5 = GND, V SKIP = 5V,
MAX8733A/MAX8734A (TON = GND)
Output Voltage in
V+ = 6V to 24V, either SMPS 1.97 2.03 V
Adjustable Mode
Output Voltage Adjust Range Either SMPS 2.0 5.5 V
FB3, FB5 Adjustable-Mode
Dual-Mode comparator 0.1 0.2 V
Threshold Voltage
Current-Limit Threshold ILIM_ = VCC, GND - CS_ (MAX8732A/MAX8733A),
90 110 mV
(Positive, Default) GND - LX_ (MAX8734A)

GND - CS_ VILIM_ = 0.5V 40 60

Current-Limit Threshold
(MAX8732A/MAX8733A), VILIM_ = 1V 90 110 mV
(Positive, Adjustable)
GND - LX_ (MAX8734A) VILIM_ = 2V 180 220
MAX8732A or MAX8734A VOUT5 = 5.05V 1.895 2.315
(VTON = 5V) VOUT3 = 3.33V 0.833 1.017
On-Time Pulse Width µs
MAX8733A or MAX8734A VOUT5 = 5.05V 0.895 1.209
(VTON = 0) VOUT3 = 3.33V 0.475 0.635
Minimum Off-Time 200 400 ns
INTERNAL REGULATOR AND REFERENCE
LDO5 Output Voltage ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO5 < 100mA 4.90 5.10 V
LDO5 Undervoltage-Lockout
Falling edge of LDO5, hysteresis = 1% 3.7 4.3 V
Fault Threshold

_______________________________________________________________________________________ 5
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
MAX8732A/MAX8733A/MAX8734A

(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12.0.V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Falling edge of OUT5, rising edge at OUT5 regulation
LDO5 Bootstrap Switch Threshold 4.43 4.69 V
point
LDO5 Bootstrap Switch
LDO5 to OUT5, VOUT5 = 5V 3.2 Ω
Resistance
LDO3 Output Voltage ON3 = ON5 = GND, 6V < V+ < 24V, 0 < ILDO3 < 100mA 3.27 3.43 V
Falling edge of OUT3, rising edge at OUT3 regulation
LDO3 Bootstrap Switch Threshold 2.80 3.02 V
point
LDO3 Bootstrap
LDO3 to OUT3, VOUT3 = 3.2V 3.5 Ω
Switch Resistance
REF Output Voltage No external load 1.975 2.025 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current REF in regulation 10 µA
V+ Operating Supply Current LDO5 switched over to OUT5, 5V SMPS 50 µA
V+ Standby Supply Current V+ = 6V to 24V, both SMPSs off, includes ISHDN 300 µA
V+ Shutdown Supply Current V+ = 4.5V to 24V 15 µA
Both SMPSs on, FB3 = FB5 = SKIP = GND, VOUT3 =
Quiescent Power Consumption 4.5 mW
3.5V, VOUT5 = 5.3V
FAULT DETECTION
Overvoltage Trip Threshold FB3 or FB5 with respect to nominal regulation point +8 +14 %
FB3 or FB5 with respect to nominal output, falling edge,
PGOOD Threshold -12 -7 %
typical hysteresis = 1%
PGOOD Output Low Voltage ISINK = 4mA 0.3 V
PGOOD Leakage Current High state, forced to 5.5V 1 µA
Output Undervoltage Shutdown
FB3 or FB5 with respect to nominal output voltage 65 75 %
Threshold
Output Undervoltage Shutdown
From ON_ signal 10 40 ms
Blanking Time
INPUTS AND OUTPUTS
Feedback Input Leakage Current VFB3 = VFB5 = 2.2V -200 +200 nA
Low level 0.6
PRO Input Voltage V
High level 1.5
Low level 0.8
SKIP Input Voltage Float level 1.7 2.3 V
High level 2.4
Low level 0.8
TON Input Voltage V
High level 2.4

6 _______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)

MAX8732A/MAX8733A/MAX8734A
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12.0.V, ON3 = ON5 = VCC, V SHDN = 5V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Clear fault level/SMPS off level 0.8
ON3, ON5 Input Voltage Delay start level 1.7 2.3 V
SMPS on level 2.4
V PRO or VTON = 0 or 5V -1 +1
VON_ = 0 or 5V -1 +1
V SKIP = 0 or 5V -2 +2
Input Leakage Current µA
V SHDN = 0 or 24V -1 +1
VCS_ = 0 or 5V -2 +2
VILIM3, VILIM5 = 0 or 2V -0.2 +0.2
Rising edge 1.2 2.0
SHDN Input Trip Level V
Falling edge 0.96 1.04
DH_ Gate-Driver On-Resistance BST - LX_ forced to 5V 4.0 Ω
DL_, high state (pullup) 5.0
DL_ Gate-Driver On-Resistance Ω
DL_, low state (pulldown) 1.5
OUT3, OUT5 Discharge-Mode
40 Ω
On-Resistance

OUT3, OUT5 Discharge-Mode

Synchronous Rectifier 0.2 0.4 V
Turn-On Level
Note 1: Specifications to -40°C are guaranteed by design, not production tested.

_______________________________________________________________________________________ 7
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Typical Operating Characteristics
MAX8732A/MAX8733A/MAX8734A

(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
MAX8732A MAX8732A MAX8732A
5V OUTPUT EFFICIENCY 5V OUTPUT EFFICIENCY 5V OUTPUT EFFICIENCY
vs. LOAD CURRENT vs. LOAD CURRENT vs. LOAD CURRENT
100 100 100

MAX8732A/3A/4A toc01

MAX8732A/3A/4A toc03
MAX8732A/3A/4A toc02
PFM MODE
90 90 PFM MODE 90 PFM MODE
80 80 80
70 PWM MODE 70 70
EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)

60 60 PWM MODE 60 PWM MODE

50 ULTRASONIC MODE 50 50
ULTRASONIC MODE ULTRASONIC MODE
40 40 40
30 30 30
20 VIN = 7V 20 VIN = 12V 20 VIN = 24V
10 ON5 = VCC ON5 = VCC ON5 = VCC
10 10
ON3 = GND ON3 = GND ON3 = GND
0 0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)

MAX8733A MAX8732A MAX8733A

3.3V OUTPUT EFFICIENCY NO-LOAD BATTERY CURRENT NO-LOAD BATTERY CURRENT
vs. LOAD CURRENT vs. INPUT VOLTAGE vs. INPUT VOLTAGE
100 100 100
MAX8732A/3A/4A toc05
MAX8732A/3A/4A toc04

MAX8732A/3A/4A toc06
PFM MODE PWM MODE
90 PWM MODE

80
BATTERY CURRENT (mA)

BATTERY CURRENT (mA)

70 10 ULTRASONIC MODE
10
EFFICIENCY (%)

60 ULTRASONIC MODE
50 ULTRASONIC MODE
40
ON5 = VCC 1 1
30 PFM MODE PFM MODE
ON3 = VCC
20 VIN = 7V
VIN = 12V
10 PWM MODE VIN = 24V
0 0.1 0.1
0.001 0.01 0.1 1 10 7 10 13 16 19 22 25 7 10 13 16 19 22 25
LOAD CURRENT (A) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
MAX8732A
STANDBY INPUT CURRENT SHUTDOWN INPUT CURRENT 5V OUTPUT SWITCHING FREQUENCY
vs. INPUT VOLTAGE vs. INPUT VOLTAGE vs. LOAD CURRENT MAX8732A
190 10.0 250
MAX8732A/3A/4A toc07

MAX8732A/3A/4A toc08

MAX8732A/3A/4A toc09

VIN = 7V
188 9.5 225
SHUTDOWN INPUT CURRENT (µA)
STANDBY INPUT CURRENT (µA)

SWITCHING FREQUENCY (kHz)

186 9.0 200

PWM MODE
184 8.5 MAX8732A 175
MAX8732A
182 8.0 150
MAX8733A
180 7.5 125
178 7.0 100
176 MAX8733A 6.5 75
174 6.0 50 ULTRASONIC MODE
172 5.5 25
PFM MODE
170 5.0 0
7 10 13 16 19 22 25 7 10 13 16 19 22 25 0.001 0.01 0.1 1 10
INPUT VOLTAGE (V) INPUT VOLTAGE (V) LOAD CURRENT (A)

8 Idle Mode is a trademark of Maxim Integrated Products, Inc.

_______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers

MAX8732A/MAX8733A/MAX8734A
Typical Operating Characteristics (continued)
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)
MAX8732A MAX8732A
3.3V OUTPUT SWITCHING FREQUENCY 5V OUTPUT SWITCHING 3.3V OUTPUT SWITCHING
vs. LOAD CURRENT (MAX8732A) FREQUENCY vs. LOAD CURRENT FREQUENCY vs. LOAD CURRENT
360 250 360

MAX8732A/3A/4A toc11
MAX8732A/3A/4A toc10

MAX8732A/3A/4A toc12
VIN = 7V VIN = 24V VIN = 24V
320 225 320
SWITCHING FREQUENCY (kHz) PWM MODE PWM MODE
SWITCHING FREQUENCY (kHz)

SWITCHING FREQUENCY (kHz)

280 200 280
PWM MODE
175
240 240
150
200 200
125
160 160
100
120 75 120
80 50 ULTRASONIC MODE 80
ULTRASONIC MODE ULTRASONIC MODE
40 25 40
PFM MODE PFM MODE PFM MODE
0 0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
MAX8733A MAX8733A MAX8733A
5V OUTPUT SWITCHING 3.3V OUTPUT SWITCHING 5V OUTPUT SWITCHING
FREQUENCY vs. LOAD CURRENT FREQUENCY vs. LOAD CURRENT FREQUENCY vs. LOAD CURRENT
450 550 450
MAX8732A/3A/4A toc13

MAX8732A/3A/4A toc15
MAX8732A/3A/4A toc14

VIN = 7V VIN = 7V VIN = 24V

400 500 400
PWM MODE PWM MODE
450
SWITCHING FREQUENCY (kHz)

SWITCHING FREQUENCY (kHz)

SWITCHING FREQUENCY (kHz)

350 350 PWM MODE

400
300 300
350
250 300 250
200 250 200
150 200 150
150
100 100
ULTRASONIC MODE 100 ULTRASONIC MODE ULTRASONIC MODE
50 50
PFM MODE 50
PFM MODE PFM MODE
0 0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)

MAX8733A MAX8732A MAX8732A

3.3V OUTPUT SWITCHING OUT5 VOLTAGE REGULATION OUT3 VOLTAGE REGULATION
FREQUENCY vs. LOAD CURRENT vs. LOAD CURRENT vs. LOAD CURRENT
550 5.19 3.41
MAX8732A/3A/4A toc17

MAX8732A/3A/4A toc18
MAX8732A/3A/4A toc16

VIN = 24V ULTRASONIC

500 ULTRASONIC
5.17 3.40
450
SWITCHING FREQUENCY (kHz)

PWM MODE 3.39

400
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

5.15
350 3.38
5.13
300 IDLE MODE
3.37
250 IDLE MODE
5.11
200 3.36 FORCED-PWM
150 5.09
FORCED-PWM 3.35
100 ULTRASONIC MODE 5.07 3.34
50
PFM MODE
0 5.05 3.33
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
_______________________________________________________________________________________ 9
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
MAX8732A/MAX8733A/MAX8734A

Typical Operating Characteristics (continued)

(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)

LDO5 REGULATOR OUTPUT VOLTAGE LDO3 REGULATOR OUTPUT VOLTAGE REFERENCE VOLTAGE
vs. OUTPUT CURRENT vs. OUTPUT CURRENT vs. OUTPUT CURRENT
5.00 3.350 2.005
MAX8732A/3A/4A toc19

MAX8732A/3A/4A toc20

MAX8732A/3A/4A toc21
3.348 2.004
4.99 3.346 2.003
LDO5 OUTPUT VOLTAGE (V)

LDO3 OUTPUT VOLTAGE (V)

3.344 2.002
4.98 3.342 2.001

VREF (V)
3.340 2.000
4.97 3.338 1.999
3.336 1.998
4.96 3.334 1.997
3.332 1.996
4.95 3.330 1.995
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 -10 0 10 20 30 40 50 60 70 80 90 100
LDO5 OUTPUT CURRENT (mA) LDO3 OUTPUT CURRENT (mA) IREF (µA)

DELAYED-START WAVEFORMS DELAYED-START WAVEFORMS

REF, LDO3, AND LDO5 POWER-UP (ON3 = REF) (ON5 = REF)
MAX8732A/3A/4A toc22 MAX8732A/3A/4A toc23 MAX8732A/3A/4A toc24
V+
10V/div
10V ON5 5V
LDO5 5V ON3
5V/div
0 2V/div 5V/div
0 OUT5 0
2V/div
LDO3
2V/div
0 OUT5
2V/div
0 0 0
REF OUT3
1V/div 2V/div
OUT3
0 0 2V/div
0

400µs/div 100µs/div 100µs/div

MAX8732A/MAX8734A (TON = VCC)

5V PWM-MODE
SOFT-START WAVEFORMS SHUTDOWN WAVEFORMS LOAD TRANSIENT RESPONSE
MAX8732A/3A/4A toc25 MAX8732A/3A/4A toc26 MAX8732A/3A/4A toc27

5A IL5 5V ON3 VOUT,

5A/div 5V/div AC-
0 0 5V COUPLED
100mV/div
5A IL3 OUT3
5A/div 3.3V
5V/div
0 0 4A INDUCTOR
CURRENT
3.3V 5V OUT5 2A/div
OUT3 5V/div 1A
0 5V/div 0
SWITCHING 5V
5V 5V
OUT5 DL3 DL5
0 5V/div 0 5V/div 0 5V/div
200µs/div 10ms/div 20µs/div

10 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Typical Operating Characteristics (continued)

MAX8732A/MAX8733A/MAX8734A
(Circuit of Figure 1 and Figure 2, no load on LDO5, LDO3, OUT3, OUT5, and REF, V+ = 12V, ON3 = ON5 = VCC, SHDN = V+,
RCS = 7mΩ, VILIM_ = 0.5V, TA = +25°C, unless otherwise noted.)

MAX8733A/MAX8734A (TON = GND) MAX8732A/MAX8734A (TON = VCC) MAX8733A/MAX8734A (TON = GND)

5V PWM-MODE 3.3V PWM-MODE 3.3V PWM-MODE
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
MAX8732A/3A/4A toc30
MAX8732A/3A/4A toc28 MAX8732A/3A/4A toc29

VOUT, VOUT, VOUT,

AC- AC- AC-
5V 3.3V 3.3V COUPLED
COUPLED COUPLED
100mV/div 100mV/div 100mV/div

4A 4A 4A INDUCTOR
INDUCTOR INDUCTOR
CURRENT CURRENT CURRENT
2A/div 2A/div 2A/div
1A 1A 1A

5V 5V 5V
DL5 DL3 DL3
0 5V/div 0 5V/div 0 5V/div

10µs/div 20µs/div 10µs/div

MAX8733A MAX8733A
5V OUTPUT EFFICIENCY 3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT vs. LOAD CURRENT
100 100
MAX8732A/3A/4A toc31

MAX8732A/3A/4A toc32
90 90
80 80
PFM MODE PFM MODE
70 70
EFFICIENCY (%)

EFFICIENCY (%)

60 60
50 ULTRASONIC 50 ULTRASONIC
40 MODE MODE
40
30 ON5 = VCC 30 ON5 = VCC
ON3 = GND ON3 = VCC
20 VIN = 7V 20 VIN = 7V
10 VIN = 12V VIN = 12V
10
PWM MODE VIN = 24V PWM MODE VIN = 24V
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A)

______________________________________________________________________________________ 11
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Pin Description
MAX8732A/MAX8733A/MAX8734A

PIN
MAX8732A NAME FUNCTION
MAX8734A
MAX8733A
3.3V SMPS Current-Sense Input. Connect CS3 to a current-sensing resistor from the source
1 — CS3 of the synchronous rectifier to GND. The voltage at ILIM3 determines the current-limit
threshold (see the Current-Limit Circuit (ILIM_) section).
— 1 N.C. No Connection. Not internally connected.
Power-Good Output. PGOOD is an open-drain output that is pulled low if either output is
2 2 PGOOD
disabled or is more than 10% below its nominal value.
3.3V SMPS Enable Input. The 3.3V SMPS is enabled if ON3 is greater than the SMPS on level
and disabled if ON3 is less than the SMPS off level. If ON3 is connected to REF, the 3.3V
3 3 ON3
SMPS starts after the 5V SMPS reaches regulation (delay start). Drive ON3 below the clear
fault level to reset the fault latches.
5V SMPS Enable Input. The 5V SMPS is enabled if ON5 is greater than the SMPS on level and
disabled if ON5 is less than the SMPS off level. If ON5 is connected to REF, the 5V SMPS
4 4 ON5
starts after the 3.3V SMPS reaches regulation (delay start). Drive ON5 below the clear fault
level to reset the fault latches.
3.3V SMPS Current-Limit Adjustment. The GND-LX current-limit threshold defaults to 100mV if
ILIM3 is connected to VCC. In adjustable mode, the current-limit threshold is 1/10 the voltage
5 5 ILIM3
seen at ILIM3 over a 0.5V to 3V range. The logic threshold for switchover to the 100mV
default value is approximately VCC - 1V. Connect ILIM3 to REF for a fixed 200mV threshold.
Shutdown Control Input. The device enters its 6µA supply current shutdown mode if
V SHDN is less than the SHDN input falling-edge trip level and does not restart until V SHDN is
6 6 SHDN greater than the SHDN input rising-edge trip level. Connect SHDN to V+ for automatic
startup. SHDN can be connected to V+ through a resistive voltage-divider to implement a
programmable undervoltage lockout.
3.3V SMPS Feedback Input. Connect FB3 to GND for fixed 3.3V operation. Connect FB3 to a
7 7 FB3
resistive voltage-divider from OUT3 to GND to adjust the output from 2V to 5.5V.
2V Reference Output. Bypass to GND with a 0.22µF (min) capacitor. REF can source up to
8 8 REF 100µA for external loads. Loading REF degrades FB_ and output accuracy according to the
REF load-regulation error.
5V SMPS Feedback Input. Connect FB5 to GND for fixed 5V operation. Connect FB5 to a
9 9 FB5
resistive voltage-divider from OUT5 to GND to adjust the output from 2V to 5.5V.
Overvoltage and Undervoltage Fault Protection Enable/Disable. Connect PRO to VCC to
disable undervoltage, overvoltage protection, and discharge mode (DL = low in shutdown).
10 10 PRO
Connect PRO to GND to enable undervoltage and overvoltage protection (see the Fault
Protection section), and output discharge mode.
5V SMPS Current-Limit Adjustment. The GND-LX current-limit threshold defaults to 100mV if
ILIM5 is connected to VCC. In adjustable mode, the current-limit threshold is 1/10 the voltage
11 11 ILIM5
seen at ILIM5 over a 0.5V to 3V range. The logic threshold for switchover to the 100mV
default value is approximately VCC - 1V. Connect ILIM5 to REF for a fixed 200mV threshold.
Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping)
12 12 SKIP operation or to VCC for PWM mode (fixed frequency). Connect to REF or leave floating for
ultrasonic mode (pulse skipping, 25kHz min).

12 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Pin Description (continued)

MAX8732A/MAX8733A/MAX8734A
PIN
MAX8732A NAME FUNCTION
MAX8734A
MAX8733A
5V SMPS Current-Sense Input. Connect CS5 to a current-sensing resistor from the source of
13 — CS5 the synchronous rectifier to GND. The voltage at ILIM5 determines the current-limit threshold
(see the Current-Limit Circuit (ILIM_) section).
Frequency Select Input. Connect to VCC for 200kHz/300kHz operation and to GND for
— 13 TON
400kHz/500kHz operation (5V/3.3V SMPS switching frequencies, respectively).
Boost Flying Capacitor Connection for 5V SMPS. Connect to an external capacitor and diode
14 14 BST5 according to the typical application circuits (Figure 1 and Figure 2). See the MOSFET Gate
Drivers (DH_, DL_) section.
Inductor Connection for 5V SMPS. LX5 is the internal lower supply rail for the DH5 high-side
15 15 LX5
gate driver. LX5 is the current-sense input for the 5V SMPS (MAX8734A only).
16 16 DH5 High-Side MOSFET Floating Gate-Driver Output for 5V SMPS. DH5 swings from LX5 to BST5.
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage with a
17 17 VCC
series 50Ω resistor. Bypass to GND with a 1µF ceramic capacitor.
5V Linear-Regulator Output. LDO5 is the gate-driver supply for the external MOSFETs. LDO5
can provide a total of 100mA, including MOSFET gate-drive requirements and external loads.
The internal load depends on the choice of MOSFET and switching frequency (see the
18 18 LDO5 Reference and Linear Regulators (REF, LDO5, and LDO3) section). If OUT5 is greater than
the LDO5 bootstrap switch threshold, the LDO5 regulator shuts down and the LDO5 pin
connects to OUT5 through a 1.4Ω switch. Bypass LDO5 with a minimum of 4.7µF. Use an
additional 1µF per 5mA of load.
19 19 DL5 5V SMPS Synchronous Rectifier Gate-Drive Output. DL5 swings between GND and LDO5.
Power-Supply Input. V+ powers the LDO5/LDO3 linear regulators and is also used for the
20 20 V+ Quick-PWM on-time, one-shot circuits. Connect V+ to the battery input and bypass with a
0.1µF capacitor.
5V SMPS Output Voltage-Sense Input. Connect to the 5V SMPS output. OUT5 is an input to
the Quick-PWM on-time, one-shot circuit. It also serves as the 5V feedback input in fixed-
21 21 OUT5
voltage mode. If OUT5 is greater than the LDO5 bootstrap-switch threshold, the LDO5 linear
regulator shuts down and LDO5 connects to OUT5 through a 1.4Ω switch.
3.3V SMPS Output Voltage-Sense Input. Connect to the 3.3V SMPS output. OUT3 is an input
to the Quick-PWM on-time, one-shot circuit. It also serves as the 3V feedback input in fixed-
22 22 OUT3
voltage mode. If OUT3 is greater than the LDO3 bootstrap-switch threshold, the LDO3 linear
regulator shuts down and LDO3 connects to OUT3 through a 1.5Ω switch.
23 23 GND Analog and Power Ground
24 24 DL3 3.3V SMPS Synchronous-Rectifier Gate-Drive Output. DL3 swings between GND and LDO5.
3.3V Linear-Regulator Output. LDO3 powers up after REF is in regulation. LDO3 can provide
a total of 100mA to external loads. If OUT3 is greater than the LDO3 bootstrap-switch
25 25 LDO3
threshold, the LDO3 regulator shuts down and the LDO3 pin connects to OUT3 through a
1.5Ω switch. Bypass LDO3 with a minimum of 4.7µF. Use an additional 1µF per 5mA of load.
High-Side MOSFET Floating Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to
26 26 DH3
BST3.
Inductor Connection for 3.3V SMPS. LX3 is the current-sense input for the 3.3V SMPS
27 27 LX3
(MAX8734A only).
Boost Flying Capacitor Connection for 3.3V SMPS. Connect to an external capacitor and
28 28 BST3 diode according to the typical application circuits (Figure 1 and Figure 2). See the MOSFET
Gate Drivers (DH_, DL_) section.

______________________________________________________________________________________ 13
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Typical Application Circuits
MAX8732A/MAX8733A/MAX8734A

Table 1. Component Suppliers

The typical application circuits (Figures 1 and 2) gener- MANUFACTURER PHONE FAX
ate the 5V/5A and 3.3V/5A main supplies in a notebook
Central Semiconductor 516-435-1110 516-435-1824
computer. The input supply range is 7V to 24V. Table 1
lists component suppliers. Dale-Vishay 402-564-3131 402-563-6418
Fairchild 408-721-2181 408-721-1635
Detailed Description International Rectifier 310-322-3331 310-322-3332
The MAX8732A/MAX8733A/MAX8734A dual-buck,
NIEC (Nihon) 805-843-7500 847-843-2798
BiCMOS, switch-mode power-supply controllers gener-
ate logic supply voltages for notebook computers. The Sanyo 619-661-6835 619-661-1055
MAX8732A/MAX8733A/MAX8734A are designed pri- Sprague 603-224-1961 603-224-1430
marily for battery-powered applications where high effi- Sumida 847-956-0666 847-956-0702
ciency and low-quiescent supply current are critical. Taiyo Yuden 408-573-4150 408-573-4159
The MAX8732A is optimized for highest efficiency with a
5V/200kHz SMPS and a 3.3V/300kHz SMPS, while the TDK 847-390-4461 847-390-4405

VIN 7V TO 24V

5V ALWAYS ON

1µF 4.7µF
50Ω
VCC

LDO5 ILIM3 VCC 1µF

1/2
V+ ILIM5 D1
10µF 0.1µF 10µF 10µF
1/2 CMPSH-3A
D1
BST5 BST3
10Ω 10Ω
N1 N3
DH5 MAX8732A DH3
FDS6612A FDS6612A
0.1µF MAX8733A
0.1µF
L5 LX5 LX3 L3 3.3V
5V
C5 C3
D3
EP10QY03 DL5 DL3
N2 N4 D2
IRF7811AV IRF7811AV EP10QY03
CS5
CS3
OUT5 OUT3
VCC
RCS5 RCS3
20mΩ FB5 FB3 20mΩ
100kΩ
ON
SHDN
OFF PGOOD
VCC ON5

REF ON3 SKIP

FREQUENCY-DEPENDENT COMPONENTS
MAX8732A MAX8733A GND PRO
5V/3.3V SMPS
SWITCHING FREQUENCY REF LDO3
200kHz/300kHz 400kHz/500kHz 1MΩ
3.3V ALWAYS ON
L3 4.7µH 3.0µH
L5 7.6µH 5.6µH 0.22µF 4.7µF
C3 470µF 220µF
C5 330µF 150µF

Figure 1. MAX8732A/MAX8733A Typical Application Circuit

14 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers

MAX8732A/MAX8733A/MAX8734A
VIN 7V TO 24V
5V ALWAYS ON

1µF 4.7µF
50Ω
VCC

LDO5 ILIM3 VCC 1µF

1/2
V+ ILIM5 D1
10µF 0.1µF 10µF 10µF
1/2 CMPSH-3A
D1
BST5 BST3
10Ω 10Ω
N1 N3
DH5 DH3
FDS6612A MAX8734A FDS6612A
0.1µF 0.1µF
L5 LX5 LX3 L3
5V 3.3V
470pF* 470pF*
C5 SEE C3
TON
D3 TABLE
EP10QY03 DL5 DL3
N2 N4 D2
IRF7811AV IRF7811AV EP10QY03

OUT5 OUT3
VCC
FB5 FB3
100kΩ
ON
SHDN
OFF PGOOD
VCC ON5

REF ON3 SKIP

GND PRO
REF LDO3
1MΩ
3.3V ALWAYS ON

0.22µF 4.7µF

*OPTIONAL CAPACITANCE BETWEEN

LX AND PGND (CLOSE TO THE IC) ONLY
REQUIRED FOR ULTRASONIC MODE
FREQUENCY-DEPENDENT COMPONENTS
TON = VCC TON = GND
5V/3.3V SMPS
SWITCHING FREQUENCY 200kHz/300kHz 400kHz/500kHz

L3 4.7µH 3.0µH
L5 7.6µH 5.6µH
C3 470µF 220µF
C5 330µF 150µF

Figure 2. MAX8734A Typical Application Circuit

______________________________________________________________________________________ 15
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
MAX8732A/MAX8733A/MAX8734A

MAX8733A is optimized for “thin and light” applications with Each step-down, the power-switching circuit consists of
a 5V/400kHz SMPS and a 3.3V/500kHz SMPS. The two n-channel MOSFETs, a rectifier, and an LC output fil-
MAX8734A provides a pin-selectable switching frequency, ter. The output voltage is the average AC voltage at the
allowing either 200kHz/300kHz or 400kHz/500kHz operation switching node, which is regulated by changing the duty
of the 5V/3.3V SMPSs, respectively. cycle of the MOSFET switches. The gate-drive signal to
Light-load efficiency is enhanced by automatic Idle- the n-channel, high-side MOSFET must exceed the
Mode operation, a variable-frequency pulse-skipping battery voltage, and is provided by a flying-capacitor
mode that reduces transition and gate-charge losses. boost circuit that uses a 100nF capacitor connected
to BST_.

V+

PGOOD
MAX8732A PGOOD3
MAX8733A
MAX8734A
TON PGOOD5
(MAX8734 ONLY)

BST3 BST5

DH3 DH5

LX3
LX5
3.3V 5V
LDO5 SMPS PWM SMPS PWM LDO5
CONTROLLER CONTROLLER
DL3 DL5

CS3 CS5
(MAX8732A/ (MAX8732A/
MAX8733A) MAX8733A)

ILIM3 ILIM5
FB3
FB5
OUT3
OUT5

EN3 2.91V 4.56V EN5

LDO3 3V 5V LDO5
LINEAR LINEAR
REG REG

VCC

ON3

ON5 POWER-ON SEQUENCE/

CLEAR FAULT LATCH THERMAL
SHDN SHUTDOWN
2V REF
PRO REFERENCE

GND

Figure 3. Detailed Functional Diagram

16 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Each PWM controller consists of a Dual-Mode feedback block controls the power-up timing of the main PWMs and

MAX8732A/MAX8733A/MAX8734A
network and multiplexer, a multi-input PWM comparator, monitors the outputs for undervoltage faults. The
high-side and low-side gate drivers, and logic. The MAX8732A/MAX8733A/MAX8734A include 5V and 3.3V
MAX8732A/MAX8733A/MAX8734A contain fault-protection linear regulators. Bias generator blocks include the 5V
circuits that monitor the main PWM outputs for undervolt- (LDO5) linear regulator, 2V precision reference, and auto-
age and overvoltage conditions. A power-on sequence matic bootstrap switchover circuit.

V+

OUT
ON-TIME tOFF
TON (MAX8734A) COMPUTE Q TRIG
ONE SHOT
tON
TRIG Q R
ONE SHOT TO DH_ DRIVER
Q
REF
S

ILIM_ ERROR
AMPLIFIER

CURRENT
LIMIT

Σ TO DL_ DRIVER

CS_ (MAX8732A/8733A)
LX_ (MAX8734A)

ZERO
CROSSING S

SKIP

OUT_

PGOOD

0.9 x VREF

FB_

OV_FAULT
FAULT
UV_FAULT LATCH

1.1 x VREF

0.15V

PRO

20ms
BLANKING
0.7 x VREF

Figure 4. PWM Controller (One Side Only)

______________________________________________________________________________________ 17
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
MAX8732A/MAX8733A/MAX8734A

These internal blocks are not powered directly from the See Table 2 for approximate K-factors. The constant
battery. Instead, the 5V (LDO5) linear regulator steps 0.075V is an approximation to account for the expected
down the battery voltage to supply both internal circuit- drop across the synchronous-rectifier switch. Switching
ry and the gate drivers. The synchronous-switch gate frequency increases as a function of load current due
drivers are directly powered from LDO5, while the high- to the increasing drop across the synchronous rectifier,
side switch gate drivers are indirectly powered from which causes a faster inductor-current discharge ramp.
LDO5 through an external diode-capacitor boost cir- On-times translate only roughly to switching frequen-
cuit. An automatic bootstrap circuit turns off the 5V lin- cies. The on-times guaranteed in the Electrical
ear regulator and powers the device from OUT5 when Characteristics are influenced by switching delays in
OUT5 is above 4.56V. the external high-side power MOSFET. Also, the dead-
Free-Running, Constant On-Time PWM time effect increases the effective on-time, reducing the
Controller with Input Feed-Forward switching frequency. It occurs only in PWM mode (SKIP
The Quick-PWM control architecture is a pseudo-fixed- = VCC) and during dynamic output voltage transitions
frequency, constant on-time, current-mode type with when the inductor current reverses at light or negative
voltage feed-forward. The Quick-PWM control architec- load currents. With reversed inductor current, the
ture relies on the output ripple voltage to provide the inductor’s EMF causes LX to go high earlier than nor-
PWM ramp signal; thus, the output filter capacitor’s mal, extending the on-time by a period equal to the DH-
ESR acts as a current-feedback resistor. The high-side rising dead time.
switch on-time is determined by a one-shot whose peri- For loads above the critical conduction point, the actual
od is inversely proportional to input voltage and directly switching frequency is:
proportional to output voltage. Another one-shot sets a
minimum off-time (300ns typ). The on-time, one-shot VOUT + VDROP1
f=
triggers when the following conditions are met: the error t ON ( V + + VDROP2 )
comparator is low, the synchronous rectifier current is
below the current-limit threshold, and the minimum off- where VDROP1 is the sum of the parasitic voltage drops
time one-shot has timed out. in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
On-Time, One-Shot (tON)
the sum of the parasitic voltage drops in the charging
Each PWM core includes a one-shot that sets the high-
path, including high-side switch, inductor, and PC
side switch on-time for each controller. Each fast, low-
board resistances, and tON is the on-time calculated by
jitter, adjustable one-shot includes circuitry that varies
the MAX8732A/MAX8733A/MAX8734A.
the on-time in response to battery and output voltage.
The high-side switch on-time is inversely proportional to Automatic Pulse-Skipping Switchover
the battery voltage as measured by the V+ input, and (Idle Mode)
proportional to the output voltage. This algorithm results In Idle Mode (SKIP = GND), an inherent automatic
in a nearly constant switching frequency despite the switchover to PFM takes place at light loads. This
lack of a fixed-frequency clock generator. The benefit switchover is affected by a comparator that truncates
of a constant switching frequency is the frequency can the low-side switch on-time at the inductor current’s
be selected to avoid noise-sensitive frequency regions: zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
K(VOUT + 0.075V ) operation to coincide with the boundary between con-
t ON =
V+

Table 2. Approximate K-Factor Errors

SWITCHING FREQUENCY APPROXIMATE K-
SMPS K-FACTOR (µs)
(kHz) FACTOR ERROR (%)
MAX8732A/MAX8734A (tON = VCC), 5V 200 5.0 ±10
MAX8732A/MAX8734A (tON = VCC), 3.3V 300 3.3 ±10
MAX8733A/MAX8734A (tON = GND), 5V 400 2.5 ±10
MAX8733A/MAX8734A (tON = GND), 3.3V 500 2.0 ±10

18 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
tinuous and discontinuous inductor-current operation low-side switch on-time. Disabling the zero-crossing

MAX8732A/MAX8733A/MAX8734A
(also known as the critical conduction point): detector causes the low-side, gate-drive waveform to
become the complement of the high-side, gate-drive
K × VOUT _  V + − VOUT _  waveform. The inductor current reverses at light loads
ILOAD(SKIP) =   as the PWM loop strives to maintain a duty ratio of
2×L  V+ 
VOUT/V+. The benefit of forced-PWM mode is to keep
where K is the on-time scale factor (see the On-Time the switching frequency fairly constant, but it comes at
One-Shot (tON) section). The load-current level at which a cost: the no-load battery current can be 10mA to
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 50mA, depending on switching frequency and the
the peak-to-peak ripple current, which is a function of the external MOSFETs.
inductor value (Figure 5). For example, in the MAX8732A Forced-PWM mode is most useful for reducing audio-
Typical Application Circuit with VOUT2 = 5V, V+ = 12V, frequency noise, improving load-transient response,
L = 7.6µH, and K = 5µs, switchover to pulse-skipping providing sink-current capability for dynamic output
operation occurs at ILOAD = 0.96A or about 1/5 full load. voltage adjustment, and improving the cross-regulation
The crossover point occurs at an even lower value if a of multiple-output applications that use a flyback trans-
swinging (soft-saturation) inductor is used. former or coupled inductor.
The switching waveforms may appear noisy and asyn- Enhanced Ultrasonic Mode
chronous when light loading causes pulse-skipping (25kHz (min) Pulse Skipping)
operation, but this is a normal operating condition that Leaving SKIP unconnected or connecting SKIP to REF
results in high light-load efficiency. Trade-offs in PFM activates a unique pulse-skipping mode with a mini-
noise vs. light-load efficiency are made by varying the mum switching frequency of 25kHz. This ultrasonic
inductor value. Generally, low inductor values produce pulse-skipping mode eliminates audio-frequency mod-
a broader efficiency vs. load curve, while higher values ulation that would otherwise be present when a lightly
result in higher full-load efficiency (assuming that the loaded controller automatically skips pulses. In ultra-
coil resistance remains fixed) and less output voltage sonic mode, the controller automatically transitions to
ripple. Penalties for using higher inductor values fixed-frequency PWM operation when the load reaches
include larger physical size and degraded load-tran- the same critical conduction point (ILOAD(SKIP)) that
sient response (especially at low input-voltage levels). occurs when normally pulse skipping.
DC output accuracy specifications refer to the trip level of An ultrasonic pulse occurs when the controller detects
the error comparator. When the inductor is in continuous that no switching has occurred within the last 28µs.
conduction, the output voltage has a DC regulation higher Once triggered, the ultrasonic controller pulls DL high,
than the trip level by 50% of the ripple. In discontinuous turning on the low-side MOSFET to induce a negative
conduction (SKIP = GND, light load), the output voltage inductor current. After the inductor current reaches the
has a DC regulation higher than the trip level by approxi- negative ultrasonic current threshold, the controller
mately 1.5% due to slope compensation. turns off the low-side MOSFET (DL pulled low) and trig-
Forced-PWM Mode gers a constant on-time (DH driven high). When the on-
The low-noise, forced-PWM (SKIP = VCC) mode dis- time has expired, the controller reenables the low-side
ables the zero-crossing comparator, which controls the MOSFET until the controller detects that the inductor
current dropped below the zero-crossing threshold.
Starting with a DL pulse greatly reduces the peak out-
∆i V+ - VOUT put voltage when compared to starting with a DH pulse.
=
∆t L
-IPEAK The output voltage at the beginning of the ultrasonic
pulse determines the negative ultrasonic current thresh-
INDUCTOR CURRENT

old, resulting in the following equation:

ILOAD = IPEAK / 2 VISONIC = IL RON = ( VREF − VFB ) × 0.58

where VFB > VREF and RON is the on-resistance of the

synchronous rectifier (MAX8734A) or the current-sense
resistor value (MAX8732A/MAX8733A).
0 ON-TIME TIME

Figure 5. Pulse-Skipping/Discontinuous Crossover Point

______________________________________________________________________________________ 19
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Reference and Linear Regulators tery. Bootstrapping reduces power dissipation due to
MAX8732A/MAX8733A/MAX8734A

(REF, LDO5, and LDO3) gate charge and quiescent losses by providing power
The 2V reference (REF) is accurate to ±1% over tem- from a 90%-efficient switch-mode source, rather than
perature, making REF useful as a precision system from a much-less-efficient linear regulator.
reference. Bypass REF to GND with a 0.22µF (min)
capacitor. REF can supply up to 100µA for external Current-Limit Circuit (ILIM_)
loads. However, if extremely accurate specifications for The current-limit circuit employs a “valley” current-sens-
both the main output voltages and REF are essential, ing algorithm. The MAX8734A uses the on-resistance of
avoid loading REF. Loading REF reduces the LDO5, the synchronous rectifier, while the MAX8732A/
LDO3, OUT5, and OUT3 output voltages slightly MAX8733A use a discrete resistor in series with the
because of the reference load-regulation error. source of the synchronous rectifier as a current-sensing
element. If the magnitude of the current-sense signal at
Two internal regulators produce 5V (LDO5) and 3.3V CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) is above
(LDO3). LDO5 provides gate drive for the external the current-limit threshold, the PWM is not allowed to initi-
MOSFETs and powers the PWM controller, logic, refer- ate a new cycle (Figure 7). The actual peak current is
ence, and other blocks within the device. The LDO5 greater than the current-limit threshold by an amount
regulator supplies a total of 100mA for internal and equal to the inductor ripple current. Therefore, the exact
external loads, including MOSFET gate drive, which current-limit characteristic and maximum load capability
typically varies from 10mA to 50mA, depending on are a function of the current-limit threshold, inductor
switching frequency and the external MOSFETs. LDO3 value, and input and output voltage.
powers up when the reference (REF) is in regulation,
and supplies up to 100mA for external loads. Bypass For the MAX8732A/MAX8733A, connect CS_ to the
LDO5 and LDO3 with a minimum 4.7µF load; use an junction of the synchronous rectifier source and a cur-
additional 1µF per 5mA of internal and external load. rent-sense resistor to GND. With a current-limit threshold
of 100mV, the accuracy is approximately ±7%. Using a
When the 5V main output voltage is above the LDO5 lower current-sense threshold results in less accuracy.
bootstrap-switchover threshold, an internal 1.4Ω p-chan- The current-sense resistor only dissipates power when
nel MOSFET switch connects OUT5 to LDO5 while simul- the synchronous rectifier is on.
taneously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above the For lower power dissipation, the MAX8734A uses the
LDO3 bootstrap-switchover threshold, an internal 1.5Ω on-resistance of the synchronous rectifier as the cur-
p-channel MOSFET switch connects OUT3 to LDO3 while rent-sense element. Use the worst-case maximum
simultaneously shutting down the LDO3 linear regulator. value for RDS(ON) from the MOSFET data sheet, and
These actions bootstrap the device, powering the internal add some margin for the rise in RDS(ON) with tempera-
circuitry and external loads from the output SMPS volt- ture. A good general rule is to allow 0.5% additional
ages, rather than through linear regulators from the bat- resistance for each °C of temperature rise. The current
limit varies with the on-resistance of the synchronous
rectifier. The reward for this uncertainty is robust, loss-
less overcurrent sensing. When combined with the
40µs (MAX)

INDUCTOR
CURRENT -IPEAK

ILOAD
INDUCTOR CURRENT

ZERO-CROSSING
DETECTION
ILIMIT

ISONIC
ON-TIME (tON)
0 TIME

Figure 7. “Valley” Current-Limit Threshold Point

Figure 6. Ultrasonic Current Waveforms

20 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
undervoltage-protection circuit, this current-limit The logic threshold for switchover to the 100mV default

MAX8732A/MAX8733A/MAX8734A
method is effective in almost every circumstance. value is approximately VCC - 1V.
A negative current limit prevents excessive reverse Carefully observe the PC board layout guidelines to
inductor currents when VOUT sinks current. The nega- ensure that noise and DC errors do not corrupt the cur-
tive current-limit threshold is set to approximately 120% rent-sense signals at CS_. Mount or place the device
of the positive current limit and therefore tracks the close to the synchronous rectifier or sense resistor
positive current limit when ILIM_ is adjusted. (whichever is used) with short, direct traces, making a
The current-limit threshold is adjusted with an external Kelvin-sense connection to the sense resistor. The cur-
voltage-divider at ILIM_. The current-limit threshold rent-sense accuracy of Figure 8 is degraded if the
adjustment range is from 50mV to 300mV. In the Schottky diode conducts during the synchronous recti-
adjustable mode, the current-limit threshold voltage is fier on-time. To ensure that all current passes through
precisely 1/10th the voltage at ILIM_. The threshold the sense resistor, connect the Schottky diode in paral-
defaults to 100mV when ILIM_ is connected to VCC. lel with only the synchronous rectifier (Figure 9) if the
voltage drop across the synchronous rectifier and
sense resistor exceeds the Schottky diode’s forward
voltage. Note that at high temperatures, the on-resis-
tance of the synchronous rectifier increases and the
V+ forward voltage of the Schottky diode decreases.
MAX8732A
MAX8733A
DH_
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ gate drivers sink 2.0A and 3.3A,
respectively, of gate drive, ensuring robust gate drive for
LX_ high-current applications. The DH_ floating high-side
OUT_
MOSFET drivers are powered by diode-capacitor charge
DL_ pumps at BST_. The DL_ synchronous-rectifier drivers are
powered by LDO5.
The internal pulldown transistors that drive DL_ low
CS_ have a 0.6Ω typical on-resistance. These low on-resis-
tance pulldown transistors prevent DL_ from being
pulled up during the fast rise time of the inductor nodes
Figure 8. Current Sensing Using Sense Resistor due to capacitive coupling from the drain to the gate of
(MAX8732A/MAX8733A) the low-side synchronous-rectifier MOSFETs. However,
for high-current applications, some combinations of
high- and low-side MOSFETS may cause excessive
gate-drain coupling, which leads to poor efficiency and
V+ EMI-producing shoot-through currents. Adding a resis-
MAX8732A
MAX8733A tor in series with BST_ increases the turn-on time of the
DH_

5V VIN
LX_
OUT_
10Ω
BST

DL_
DH

CS_
LX

MAX8732A
MAX8733A
MAX8734A
Figure 9. More Accurate Current Sensing with Adjusted
Schottky Connection
Figure 10. Reducing the Switching-Node Rise Time

______________________________________________________________________________________ 21
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
high-side MOSFETs at the expense of efficiency, without Overvoltage Protection
MAX8732A/MAX8733A/MAX8734A

degrading the turn-off time (Figure 10). When the output voltage is 11% above the set voltage,
Adaptive dead-time circuits monitor the DL_ and DH_ the overvoltage fault protection activates. The synchro-
drivers and prevent either FET from turning on until the nous rectifier turns on 100% and the high-side MOSFET
other is fully off. This algorithm allows operation without turns off. This rapidly discharges the output capacitors,
shoot-through with a wide range of MOSFETs, minimiz- decreasing the output voltage. The output voltage may
ing delays and maintaining efficiency. There must be dip below ground. For loads that cannot tolerate a neg-
low-resistance, low-inductance paths from the gate dri- ative voltage, place a power Schottky diode across the
vers to the MOSFET gates for the adaptive dead-time cir- output to act as a reverse-polarity clamp. In practical
cuit to work properly. Otherwise, the sense circuitry applications, there is a fuse between the power source
interprets the MOSFET gate as “off” when there is actual- (battery) and the external high-side switches. If the
ly charge left on the gate. Use very short, wide traces overvoltage condition is caused by a short in the high-
measuring 10 to 20 squares (50 mils to 100 mils wide if side switch, turning the synchronous rectifier on 100%
the MOSFET is 1in from the device). creates an electrical short between the battery and
GND, blowing the fuse and disconnecting the battery
POR, UVLO, and Internal Digital from the output. Once an overvoltage fault condition is
Soft-Start set, it can only be reset by toggling SHDN, ON_, or
Power-on reset (POR) occurs when V+ rises above cycling V+ (POR).
approximately 2.4V, resetting the undervoltage, over-
voltage, and thermal-shutdown fault latches. LDO5 Undervoltage Protection
undervoltage-lockout (UVLO) circuitry inhibits switching When the output voltage is 30% below the set voltage for
when LDO5 is below 4V (typ). DL_ is low if PRO is dis- over 22ms (undervoltage shutdown blanking time), the
abled; DL_ is high if PRO is enabled. The output volt- undervoltage fault protection activates. Both SMPSs stop
ages begin to ramp up once VCC exceeds its 3.25V switching. The two outputs start to discharge (see the
(typ) UVLO threshold and REF is in regulation. The Discharge Mode (Soft-Stop) section). When the output
internal digital soft-start timer begins to ramp up the voltage drops to 0.3V, the synchronous rectifiers turn on,
maximum-allowed current limit during startup. The clamping the outputs to GND. Toggle SHDN or ON_, or
1.7ms ramp occurs in five steps: 20%, 40%, 60%, 80%, cycle V+ (POR) to clear the undervoltage fault latch.
and 100%. Thermal Protection
When LD05 falls below its 4V (typ) UVLO threshold, The MAX8732A/MAX8733A/MAX8734A have thermal
DH_ and DL_ are immediately forced low, and the out- shutdown to protect the devices from overheating.
puts are high impedance. REF is turned off when VCC Thermal shutdown occurs when the die temperature
falls below 3.25V (typ). DL_ is forced high again when exceeds +160°C. All internal circuitry shuts down during
VCC falls below its 1V (typ) POR threshold. thermal shutdown. The MAX8732A/MAX8733A/
MAX8734A may trigger thermal shutdown if LDO_ is not
Power-Good Output (PGOOD) bootstrapped from OUT_ while applying a high input
The PGOOD comparator continuously monitors both out- voltage on V+ and drawing the maximum current
put voltages for undervoltage conditions. PGOOD is (including short circuit) from LDO_. Even if LDO_ is boot-
actively held low in shutdown, standby, and soft-start. strapped from OUT_, overloading the LDO_ causes
PGOOD releases and digital soft-start terminates when large power dissipation on the bootstrap switches, which
both outputs reach the error-comparator threshold. may result in thermal shutdown. Cycling SHDN, ON3,
PGOOD goes low if EITHER output turns off or is 10% ON5, or a V+ (POR) ends the thermal-shutdown state.
below its nominal regulation point. PGOOD is a true
open-drain output. Note that PGOOD is independent of Discharge Mode (Soft-Stop)
the state of PRO. When PRO is low and a transition to standby or shut-
down mode occurs, or the output undervoltage fault
Fault Protection latch is set, the outputs discharge to GND through an
The MAX8732A/MAX8733A/MAX8734A provide internal 12Ω switch, until the output voltages decrease
over/undervoltage fault protection. Drive PRO low to to 0.3V. The reference remains active to provide an
activate fault protection. Drive PRO high to disable fault accurate threshold and to provide overvoltage protec-
protection. Once activated, the devices continuously tion. When both SMPS outputs discharge to 0.3V, the
monitor for both undervoltage and overvoltage conditions. DL_ synchronous rectifier drivers are forced high. The

22 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers

MAX8732A/MAX8733A/MAX8734A
Table 3. Operating-Mode Truth Table
MODE CONDITION COMMENT
Transitions to discharge mode after a V+ POR and after REF becomes valid.
Power-Up LDO5 < UVLO threshold
LDO5, LDO3, and REF remain active. DL_ is active if PRO is low.
SHDN = high, ON3 or ON5
Run Normal operation.
enabled
Overvoltage Either output > 111% of DL_ is forced high. LDO3, LDO5 active. Exited by a V+ POR or by toggling
Protection nominal level, PRO = low SHDN, ON3, or ON5.
Either output < 70% of
Undervoltage nominal after 22ms time- If PRO is low, DL_ is forced high after discharge mode terminates. LDO3,
Protection out expires and output is LDO5 active. Exited by a V+ POR or by toggling SHDN, ON3, or ON5.
enabled, PRO = low
PRO is low and either
Discharge switch (12Ω) connects OUT_ to PGND. One output may still run
SMPS output is still high in
Discharge while the other is in discharge mode. Activates when LDO_ is in UVLO, or
either standby mode or
transition to UVLO, standby, or shutdown has begun. LDO3, LDO5 active.
shutdown mode
ON5, ON3 < startup
Standby DL_ stays high if PRO is low. LDO3, LDO5 active.
threshold, SHDN = high
Shutdown SHDN = low All circuitry off.
Thermal Shutdown TJ > +160°C All circuitry off. Exited by V+ POR or cycling SHDN, ON3, or ON5.

synchronous rectifier drivers clamp the SMPS outputs drive SHDN above 2V (SHDN input rising-edge trip
to GND. When PRO is high, the SMPS outputs do not level). For automatic shutdown and startup, connect
discharge and the DL_ synchronous rectifier drivers SHDN to V+. If PRO is low, both SMPS outputs are dis-
remain low. charged to 0.3V through a 12Ω switch before entering
true shutdown. The accurate 1V falling-edge threshold
Shutdown Mode on SHDN can be used to detect a specific analog volt-
Drive SHDN below the precise SHDN input falling-edge age level and shut down the device. Once in shutdown,
trip level to place the MAX8732A/MAX8733A/MAX8734A the 1.6V rising-edge threshold activates, providing suffi-
in their low-power shutdown state. The MAX8732A/ cient hysteresis for most applications. For additional
MAX8733A/MAX8734A consume only 6µA of quiescent hysteresis, the undervoltage threshold can be made
current while in shutdown mode. When shutdown mode dependent on REF or LDO_, which go to 0V in shutdown.
activates, the reference turns off, making the threshold
to exit shutdown inaccurate. To guarantee startup,

Table 4. Power-Up Sequencing

SHDN VON3 VON5
LDO5 LDO3 5V SMPS 3V SMPS
(V) (V) (V)
Low X X Off Off Off Off
“> 2.4” => High Low Low On On (after REF powers up) Off Off
“> 2.4” => High High High On On (after REF powers up) On On
“> 2.4” => High High Low On On (after REF powers up) Off On
“> 2.4” => High Low High On On (after REF powers up) On Off
“> 2.4” => High High REF On On (after REF powers up) On (after 3V SMPS is up) On
“> 2.4” => High REF High On On (after REF powers up) On On (after 5V SMPS is up)

______________________________________________________________________________________ 23
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Power-Up Sequencing and When using the adjustable-output mode, set the 3.3V
MAX8732A/MAX8733A/MAX8734A

On/Off Controls (ON3, ON5) SMPS lower than the 5V SMPS. LDO5 connects to OUT5
ON3 and ON5 control SMPS power-up sequencing. through an internal switch only when OUT5 is above the
ON3 or ON5 rising above 2.4V enables the respective LDO5 bootstrap-switch threshold (4.56V). LDO3 con-
outputs. ON3 or ON5 falling below 1.6V disables the nects to OUT3 through an internal switch only when
respective outputs. OUT3 is above the LDO3 bootstrap switch threshold
Connecting ON3 or ON5 to REF forces the respective (2.91V). Bootstrapping is most effective when the fixed
outputs off while the other output is below regulation and output voltages are used. Once LDO_ is bootstrapped
starts after that output regulates. The second SMPS from OUT_, the internal linear regulator turns off. This
remains on until the first SMPS turns off, the device shuts reduces internal power dissipation and improves effi-
down, a fault occurs, or LDO5 goes into undervoltage ciency when LDO_ is powered with a high input voltage.
lockout. Both supplies begin their power-down sequence Design Procedure
immediately when the first supply turns off. Driving ON_
below 0.8V clears the overvoltage, undervoltage, and Establish the input voltage range and maximum load
thermal fault latches. current before choosing an inductor and its associated
ripple-current ratio (LIR). The following four factors dic-
Adjustable-Output Feedback tate the rest of the design:
(Dual-Mode FB) 1) Input Voltage Range. The maximum value (V+(MAX))
Connect FB_ to GND to enable the fixed, preset SMPS must accommodate the maximum AC adapter volt-
output voltages (3.3V and 5V). Connect a resistive volt- age. The minimum value (V+(MIN)) must account for
age-divider at FB_ between OUT_ and GND to adjust the lowest input voltage after drops due to connec-
the respective output voltage between 2V and 5.5V tors, fuses, and battery selector switches. Lower input
(Figure 11). Choose R2 to be approximately 10kΩ, and voltages result in better efficiency.
solve for R1 using the equation:
2) Maximum Load Current. The peak load current
V  (ILOAD(MAX)) determines the instantaneous compo-
OUT _
R1 = R2 ×  − 1 nent stress and filtering requirements, and thus dri-
 V 
 FB  ves output capacitor selection, inductor saturation
rating, and the design of the current-limit circuit.
where VFB = 2V nominal. The continuous load current (ILOAD) determines the
thermal stress and drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
V+
optimal frequency is largely a function of maximum
DH_ input voltage and MOSFET switching losses. The
MAX8732A has a nominal switching frequency of
VOUT_ 200kHz for the 5V SMPS and 300kHz for the 3.3V
MAX8732A SMPS. The MAX8733A has a nominal switching fre-
MAX8733A quency of 400kHz for the 5V SMPS and 500kHz for
DL_
MAX8734A the 3.3V SMPS. The MAX8734A has a pin-selec-
GND table switching frequency.
R1 4) Inductor Ripple Current Ratio (LIR). LIR is the
OUT_
ratio of the peak-to-peak ripple current to the aver-
FB_
age inductor current. Size and efficiency trade-offs
R2 must be considered when setting the inductor rip-
ple current ratio. Low inductor values cause large
ripple currents, resulting in the smallest size, but
poor efficiency and high output noise. The minimum
practical inductor value is one that causes the cir-
cuit to operate at critical conduction (where the
Figure 11. Setting VOUT_ with a Resistor-Divider inductor current just touches zero with every cycle

24 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
at maximum load).Inductor values lower than this ley of the inductor current occurs at ILOAD(MAX) minus

MAX8732A/MAX8733A/MAX8734A
grant no further size-reduction benefit. half of the ripple current; therefore:
The MAX8732A/MAX8733A/MAX8734As’ pulse-skip- ILIMIT(LOW) > ILOAD(MAX) - [(LIR / 2) x ILOAD(MAX)]
ping algorithm (SKIP = GND) initiates skip mode at the where ILIMIT(LOW) = minimum current-limit threshold
critical conduction point, so the inductor’s operating voltage divided by the RDS(ON) of N2/N4 (MAX8734A).
point also determines the load current at which For the MAX8732A/MAX8733A/MAX8734A, the mini-
PWM/PFM switchover occurs. The optimum point is mum current-limit threshold voltage is 93mV (ILIM_ =
usually found between 20% and 50% ripple current. VCC). Use the worst-case maximum value for RDS(ON)
Inductor Selection from the MOSFET N2/N4 data sheet and add some
The switching frequency (on-time) and operating point margin for the rise in RDS(ON) with temperature. A good
(% ripple or LIR) determine the inductor value as follows: general rule is to allow 0.5% additional resistance for
each °C of temperature rise.

L =
(
VOUT_ V + − VOUT_ ) Examining the 5A circuit example with a maximum
V + × f × LIR × ILOAD(MAX) RDS(ON) = 12mΩ at high temperature reveals the following:
ILIMIT(LOW) = 93mV / 12mΩ > 5A - (0.35 / 2) 5A
Example: ILOAD(MAX) = 5A, V+ = 12V, VOUT5 = 5V, f = 7.75A > 4.125A
200kHz, 35% ripple current or LIR = 0.35: 7.75A is greater than the valley current of 4.125A, so

L=
(
5V 12V − 5V ) = 8.3µH
the circuit can easily deliver the full-rated 5A using the
fixed 100mV nominal current-limit threshold voltage.
12V × 200kHz × 0.35 × 5A Connect the source of the synchronous rectifier to a
current-sense resistor to GND (MAX8732A/MAX8733A),
Find a low-loss inductor with the lowest possible DC and connect CS_ to that junction to set the current limit
resistance that fits in the allotted dimensions. Ferrite cores for the device. The MAX8732A/MAX8733A/MAX8734A
are often the best choice. The core must be large enough limit the current with the sense resistor instead of the
not to saturate at the peak inductor current (IPEAK): RDS(ON) of N2/N4. The maximum value of the sense
IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)] resistor can be calculated with the equation:
The inductor ripple current also impacts transient- ILIM_ = 93mV / RSENSE
response performance, especially at low V+ - VOUT_
differences. Low inductor values allow the inductor cur- Output-Capacitor Selection
rent to slew faster, replenishing charge removed from The output filter capacitor must have low enough equiv-
the output filter capacitors by a sudden load step. The alent series resistance (ESR) to meet output ripple and
peak amplitude of the output transient (VSAG) is also a load-transient requirements, yet have high enough ESR
function of the maximum duty factor, which can be cal- to satisfy stability requirements. The output capaci-
culated from the on-time and minimum off-time: tance must also be high enough to absorb the inductor
energy while transitioning from full-load to no-load con-
 V  ditions without tripping the overvoltage fault latch. In
(∆ILOAD(MAX) )
2 OUT _
× L K + t OFF(MIN)  applications where the output is subject to large load
 V+  transients, the output capacitor’s size depends on how
 
VSAG = much ESR is needed to prevent the output from dip-
  V+− V  
ping too low under a load transient. Ignoring the sag
2 × COUT × VOUT _ K − t OFF(MIN) 
OUT _

  V+ 
  due to finite capacitance:
 
VDIP
where minimum off-time = 0.350µs (max) and K is from RESR ≤
ILOAD(MAX)
Table 2.
Determining the Current Limit where VDIP is the maximum-tolerable transient voltage
The minimum current-limit threshold must be great drop. In non-CPU applications, the output capacitor’s
enough to support the maximum load current when the size depends on how much ESR is needed to maintain
current limit is at the minimum tolerance value. The val- an acceptable level of output voltage ripple:

______________________________________________________________________________________ 25
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
where LIR is the inductor ripple current ratio and ILOAD
MAX8732A/MAX8733A/MAX8734A

VP−P
RESR ≤ is the average DC load. Using LIR = 0.35 and an aver-
LIR × ILOAD(MAX) age load current of 5A, the ESR needed to support
50mVP-P ripple is 28mΩ.
where VP-P is the peak-to-peak output voltage ripple. Do not place high-value ceramic capacitors directly
The actual capacitance value required relates to the across the fast-feedback inputs (OUT_ to GND for inter-
physical size needed to achieve low ESR, as well as to nal feedback, FB_ divider point for external feedback)
the chemistry of the capacitor technology. Thus, the without taking precautions to ensure stability. Large
capacitor is usually selected by ESR and voltage rating ceramic capacitors can have a high-ESR zero frequency
rather than by capacitance value (this is true of tanta- and cause erratic, unstable operation. Adding a discrete
lum, OS-CON, and other electrolytic-type capacitors). resistor or placing the capacitors a couple of inches
When using low-capacity filter capacitors such as downstream from the junction of the inductor and OUT_
polymer types, capacitor size is usually determined by may improve stability.
the capacity required to prevent VSAG and VSOAR from Unstable operation manifests itself in two related but
tripping the undervoltage and overvoltage fault latches distinctly different ways: double pulsing and fast-feed-
during load transients in ultrasonic mode. back loop instability. Noise on the output or insufficient
For low input-to-output voltage differentials (VIN / VOUT ESR may cause double pulsing. Insufficient ESR does
< 2), additional output capacitance is required to main- not allow the amplitude of the voltage ramp in the output
tain stability and good efficiency in ultrasonic mode. signal to be large enough. The error comparator mistak-
enly triggers a new cycle immediately after the 350ns
The amount of overshoot due to stored inductor energy
minimum off-time period has expired. Double pulsing
can be calculated as:
results in increased output ripple, and can indicate the
presence of loop instability caused by insufficient ESR.
IPEAK 2 L
VSOAR = Loop instability results in oscillations or ringing at the
2COUT VOUT _ output after line or load perturbations, causing the out-
put voltage to fall below the tolerance limit.
where IPEAK is the peak inductor current.
The easiest method for checking stability is to apply a
Stability Considerations very fast zero-to-max load transient (refer to the
Stability is determined by the value of the ESR zero MAX8734A EV kit data sheet) and observe the output
(fESR) relative to the switching frequency (f). The point voltage-ripple envelope for overshoot and ringing.
of instability is given by the following equation: Monitoring the inductor current with an AC current
f probe can also provide some insight. Do not allow
fESR ≤ more than one cycle of ringing of under- or overshoot
π after the initial step response.
where:
Input-Capacitor Selection
1 The input capacitors must meet the input-ripple-current
fESR = (IRMS) requirement imposed by the switching current.
2π RESR COUT
The MAX8732A/MAX8733A/MAX8734A dual switching
regulators operate at different frequencies. This inter-
For a typical 300kHz application, the ESR zero frequen- leaves the current pulses drawn by the two switches and
cy must be well below 95kHz, preferably below 50kHz.
reduces the overlap time where they add together. The
Low-ESR capacitors (especially polymer or tantalum),
input RMS current is much smaller in comparison than
in widespread use at the time of publication, typically
with both SMPSs operating in phase. The input RMS cur-
have ESR zero frequencies lower than 30kHz. In the
design example used for inductor selection, the ESR rent varies with load and the input voltage.
needed to support a specified ripple voltage is found
by the equation:

VRIPPLE(P−P)
ESR =
LIR × ILOAD

26 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
The maximum input capacitor RMS current for a single Generally, a small high-side MOSFET reduces switch-

MAX8732A/MAX8733A/MAX8734A
SMPS is given by: ing losses at high input voltage. However, the RDS(ON)
required to stay within package power-dissipation limits

(
 VOUT _ V + − VOUT _
IRMS ≈ ILOAD 
)  often limits how small the MOSFET can be. The opti-
mum situation occurs when the switching (AC) losses

 V+  equal the conduction (RDS(ON)) losses.
  Switching losses in the high-side MOSFET can become
When V+ = 2 x VOUT_(D = 50%), IRMS has a maximum an insidious heat problem when maximum battery volt-
current of ILOAD / 2. age is applied, due to the squared term in the CV2 ✕ f
switching-loss equation. Reconsider the high-side
The ESR of the input capacitor is important for deter- MOSFET chosen for adequate RDS(ON) at low battery
mining capacitor power dissipation. All the power voltages if it becomes extraordinarily hot when subject-
(IRMS2 x ESR) heats up the capacitor and reduces effi- ed to V+(MAX).
ciency. Nontantalum chemistries (ceramic or OS-CON)
are preferred due to their low ESR and resilience to Calculating the power dissipation in NH (N1/N3) due to
power-up surge currents. Choose input capacitors that switching losses is difficult since it must allow for quan-
exhibit less than +10°C temperature rise at the RMS tifying factors that influence the turn-on and turn-off
input current for optimal circuit longevity. Place the times. These factors include the internal gate resis-
drains of the high-side switches close to each other to tance, gate charge, threshold voltage, source induc-
share common input bypass capacitors. tance, and PC board layout characteristics. The
following switching-loss calculation provides only a
Power-MOSFET Selection very rough estimate and is no substitute for bench eval-
Most of the following MOSFET guidelines focus on the uation, preferably including verification using a thermo-
challenge of obtaining high load-current capability couple mounted on NH (N1/N3):
(> 5A) when using high-voltage (> 20V) AC adapters.
Low-current applications usually require less attention. PD(NH Switching) =
Choose a high-side MOSFET (N1/N3) that has conduc- COSS (VIN(MAX) )2 fSW
tion losses equal to the switching losses at the typical +
battery voltage for maximum efficiency. Ensure that the 2
conduction losses at the minimum input voltage do not VIN(MAX)ILOADQG(SW)fSW
exceed the package thermal limits or violate the overall IGATE
thermal budget. Ensure that conduction losses plus
switching losses at the maximum input voltage do not where COSS is the output capacitance of NH (N1/N3),
exceed the package ratings or violate the overall ther- QG(SW) is the switch gate charge of NH, and IGATE is
mal budget. the peak gate-drive source/sink current.
Choose a synchronous rectifier (N2/N4) with the lowest For the synchronous rectifier, the worst-case power dis-
possible RDS(ON). Ensure the gate is not pulled up by the sipation always occurs at maximum battery voltage:
high-side switch turning on due to parasitic drain-to-gate
 VOUT _ 
PD (NL ) = 1−
capacitance, causing crossconduction problems. 2
Switching losses are not an issue for the synchronous  ILOAD RDS(ON)
 VIN(MAX) 
rectifier in the buck topology since it is a zero-voltage
switched device when using the buck topology. The absolute worst case for MOSFET power dissipation
MOSFET Power Dissipation occurs under heavy overloads that are greater than
Worst-case conduction losses occur at the duty-factor ILOAD(MAX) but are not quite high enough to exceed
extremes. For the high-side MOSFET, the worst-case the current limit and cause the fault latch to trip. To pro-
power dissipation (PD) due to the MOSFET’s RDS(ON) tect against this possibility, “overdesign” the circuit to
occurs at the minimum battery voltage: tolerate:
ILOAD = ILIMIT(HIGH) + (LIR / 2 ) x ILOAD(MAX)
 V  where I LIMIT(HIGH) is the maximum valley current
( )
OUT _ 2
PD (NH Re sis tan ce) =   ILOAD RDS(ON) allowed by the current-limit circuit, including threshold
 VIN(MIN)  tolerance and resistance variation.
 

______________________________________________________________________________________ 27
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Rectifier Selection (∆IUP). The ratio h = ∆IUP/∆IDOWN indicates the ability to
MAX8732A/MAX8733A/MAX8734A

Current circulates from ground to the junction of both slew the inductor current higher in response to
MOSFETs and the inductor when the high-side switch is increased load, and must always be greater than 1. As
off. As a consequence, the polarity of the switching h approaches 1, the absolute minimum dropout point,
node is negative with respect to ground. This voltage is the inductor current is less able to increase during each
approximately -0.7V (a diode drop) at both transition switching cycle and VSAG greatly increases unless
edges while both switches are off (dead time). The drop additional output capacitance is used.
is IL x RDS(ON) when the low-side switch conducts.
A reasonable minimum value for h is 1.5, but this can
The rectifier is a clamp across the synchronous rectifier be adjusted up or down to allow tradeoffs between
that catches the negative inductor swing during the dead V SAG , output capacitance, and minimum operating
time between turning the high-side MOSFET off and the voltage. For a given value of h, the minimum operating
synchronous rectifier on. The MOSFETs incorporate a voltage can be calculated as:
high-speed silicon body diode as an adequate clamp
diode if efficiency is not of primary importance. Place a
Schottky diode in parallel with the body diode to reduce
V + (MIN) =
(VOUT _ + VDROP1) + VDROP2 − VDROP1
the forward-voltage drop and prevent the N2/N4 MOSFET t 
body diodes from turning on during the dead time. OFF (MIN) × h
1−  
Typically, the external diode improves the efficiency by  K 
1% to 2%. Use a Schottky diode with a DC current rating  
equal to 1/3 of the load current. For example, use an
where VDROP1 and VDROP2 are the parasitic voltage
MBR0530 (500mA-rated) type for loads up to 1.5A, a
drops in the discharge and charge paths (see the On-
1N5819 type for loads up to 3A, or a 1N5822 type for
loads up to 10A. The rectifier’s rated reverse-breakdown Time, One-Shot section), tOFF(MIN) is from the EC table,
voltage must be at least equal to the maximum input volt- and K is taken from Table 2. The absolute minimum
age, preferably with a 20% derating factor. input voltage is calculated with h = 1.
Operating frequency must be reduced or h must be
Boost Supply Diode increased and output capacitance added to obtain an
A signal diode, such as a 1N4148, works well in most acceptable VSAG if calculated V+(MIN) is greater than
applications. Use a small (20mA) Schottky diode for the required minimum input voltage. Calculate VSAG to
slightly improved efficiency and dropout characteris- be sure of adequate transient response if operation
tics, if the input voltage can go below 6V. Do not use near dropout is anticipated.
large power diodes, such as 1N5817 or 1N4001, since
high-junction capacitance can force LDO5 to excessive Dropout Design Example
voltages. MAX8733A: With VOUT5 = 5V, fsw = 400kHz, K = 2.25µs,
tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and h = 1.5,
Applications Information
Dropout Performance
The output voltage-adjust range for continuous-conduc- MAX1658/
V+ MAX1659 12V
tion operation is restricted by the nonadjustable 350ns
LDO POSITIVE
(max) minimum off-time, one-shot. Use the slower 5V SECONDARY
SMPS for the higher of the two output voltages for best DH_ OUTPUT
dropout performance in adjustable feedback mode. The
duty-factor limit must be calculated using worst-case val-
ues for on- and off-times, when working with low input MAX8732A 5V
voltages. Manufacturing tolerances and internal propaga- MAX8733A MAIN
T1
tion delays introduce an error to the tON K-factor. Also, MAX8734A OUTPUT
10µH
keep in mind that transient-response performance of DL_
1:2.2
buck regulators operated close to dropout is poor, and
bulk output capacitance must often be added (see the
VSAG equation in the Output-Capacitor Selection section).
T1 = TRANSPOWER TECHNOLOGIES TTI-5870
The absolute point of dropout occurs when the inductor
current ramps down during the minimum off-time
(∆IDOWN) as much as it ramps up during the on-time Figure 12. Transformer-Coupled Secondary Output

28 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
the minimum V+ is:

MAX8732A/MAX8733A/MAX8734A
VOUT (VIN(MAX) − VOUT
LPRIMARY =

V + (MIN) =
(5V + 0.1V) + 0.1V − 0.1V = 6.65V
VIN(MAX) × ƒ × I TOTAL × LIR
VSEC + VFWD
 0.35µs × 1.5  N=
1−   VOUT(MIN) + VRECT
 2.25µs 
where LPRIMARY is the primary inductance, N is the
Calculating with h = 1 yields: transformer turns ratio, VSEC is the minimum-required
rectified secondary voltage, VFWD is the forward drop
across the secondary rectifier, VOUT(MIN) is the minimum

V + (MIN) =
(5V + 0.1V) + 0.1V − 0.1V = 6.04 V
value of the main output voltage, and VRECT is the on-
state voltage drop across the synchronous rectifier
 0.35µs × 1 MOSFET. The transformer secondary return is often con-
1−   nected to the main output voltage instead of ground to
 2.25µs 
reduce the necessary turns ratio. In this case, subtract
Therefore, V+ must be greater than 6.65V. A practical VOUT from the secondary voltage (VSEC - VOUT) in the
input voltage with reasonable output capacitance transformer turns-ratio equation above.
would be 7.5V. The secondary diode in coupled-inductor applications
must withstand flyback voltages greater than 60V, which
Use of Coupled Inductors to Create usually rules out most Schottky rectifiers. Common sili-
Auxiliary Outputs con rectifiers, such as the 1N4001, are also prohibited
A coupled inductor or transformer can be substituted for because they are too slow. This often makes fast silicon
the inductor in the 5V or 3.3V SMPS to create an auxiliary rectifiers such as the MURS120 the only choice. The fly-
output (Figure 12). The MAX8732A/MAX8733A/ back voltage across the rectifier is related to the VIN -
MAX8734A are particularly well suited for such applica- VOUT difference, according to the transformer turns ratio:
tions because they can be configured in ultrasonic or
VFLYBACK = VSEC + (VIN - VOUT) ✕ N
forced-PWM mode to ensure good load regulation when
the main supplies are lightly loaded. An additional where N is the transformer turns ratio (secondary wind-
postregulation circuit can be used to improve load regula- ings/primary windings), VSEC is the maximum secondary
tion and limit output current. DC output voltage, and VOUT is the primary (main) out-
put voltage. If the secondary winding is returned to VOUT
The power requirements of the auxiliary supply must be
instead of ground, subtract VOUT from VFLYBACK in the
considered in the design of the main output. The trans-
equation above. The diode’s reverse breakdown voltage
former must be designed to deliver the required current
rating must also accommodate any ringing due to leak-
in both the primary and the secondary outputs with the
age inductance. The diode’s current rating should be at
proper turns ratio and inductance. The power ratings of
least twice the DC load current on the secondary output.
the synchronous-rectifier MOSFETs and the current limit
in the MAX8732A/MAX8733A/MAX8734A must also be The optional linear postregulator must be selected to
adjusted accordingly. Extremes of low input-output dif- deliver the required load current from the transformer’s
ferentials, widely different output loading levels, and high rectified DC output. The linear regulator should be con-
turns ratios can further complicate the design due to par- figured to run close to dropout to minimize power dissi-
asitic transformer parameters such as interwinding pation and should have good output accuracy under
capacitance, secondary resistance, and leakage induc- those conditions. Input and output capacitors are cho-
tance. Power from the main and secondary outputs is sen to meet line regulation, stability, and transient
combined to get an equivalent current referred to the requirements. There is a wide variety of linear regulators
main output. Use this total current to determine the cur- appropriate for this application; consult the specific lin-
rent limit (see the Determining the Current Limit section): ear-regulator data sheet for details.
Widely different output loads affect load regulation. In
I TOTAL = PTOTAL / VOUT
particular, when the secondary output is left unloaded
where ITOTAL is the equivalent output current referred while the main output is fully loaded, the secondary out-
to the main output and PTOTAL is the sum of the output put capacitor may become overcharged by the leakage
power from both the main output and the secondary inductance, reaching voltages much higher than intend-
output: ed. In this case, a minimum load or overvoltage protec-

______________________________________________________________________________________ 29
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
MAX8732A/MAX8733A/MAX8734A

USE AGND PLANE TO: USE PGND PLANE TO:

- BYPASS VCC AND REF - BYPASS LDO_
- TERMINATE EXTERNAL FB - CONNECT PGND TO THE TOPSIDE STAR GROUND VIA TO PGND
DIVIDER (IF USED) VIA BETWEEN POWER OUT5 GROUND OUT3
- TERMINATE RILIM AND ANALOG GROUND
(IF USED) AGND VIA TO OUT5 C3 C4
- PIN-STRAP CONTROL
INPUTS
PGND VIA TO OUT3

ANALOG GROUND
L1 C1 C2

D2
L2

D1
PLANE ON INNER LAYER N4 N2

VIAS TO GROUND N3 N1

VIA TO LX5 V+ VIA TO LX3

CONNECT PGND TO AGND
BENEATH THE CONTROLLER AT NOTE: EXAMPLE SHOWN IS FOR DUAL I.C. n-CHANNEL MOSFET.
ONE POINT ONLY AS SHOWN.

Figure 13. PC Board Layout Example

tion may be required on the secondary output to protect full-load efficiency by 1% or more. Correctly routing
any device connected to this output. PC board traces must be approached in terms of
fractions of centimeters, where a single milliohm of
PC Board Layout Guidelines excess trace resistance causes a measurable effi-
Careful PC board layout is critical to achieve minimal ciency penalty.
switching losses and clean, stable operation. This is
especially true when multiple converters are on the • CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) and
same PC board where one circuit can affect the other. GND connections to the synchronous rectifiers for
The switching power stages require particular attention current limiting must be made using Kelvin-sense
(Figure 13). Refer to the MAX1999 EV kit I.C. data sheet connections to guarantee the current-limit accuracy.
for a specific layout example. With 8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
Mount all of the power components on the top side of copper layer, while connecting CS_/LX_ traces inside
the board with their ground terminals flush against one (underneath) the MOSFETs.
another, if possible. Follow these guidelines for good
PC board layout: • When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
• Isolate the power components on the top side from made longer than the discharge path. For example, it
the sensitive analog components on the bottom side is better to allow some extra distance between the
with a ground shield. Use a separate PGND plane input capacitors and the high-side MOSFET than to
under the OUT3 and OUT5 sides (called PGND3 and allow distance between the inductor and the syn-
PGND5). Avoid the introduction of AC currents into chronous rectifier or between the inductor and the
the PGND3 and PGND5 ground planes. Run the output filter capacitor.
power plane ground currents on the top side only, if
possible. • Ensure that the OUT_ connection to COUT_ is short and
direct. However, in some cases it may be desirable to
• Use a star ground connection on the power plane to deliberately introduce some trace length between the
minimize the crosstalk between OUT3 and OUT5. OUT_ connector node and the output filter capacitor
• Keep the high-current paths short, especially at the (see the Stability Considerations section).
ground terminals. This practice is essential for sta- • Route high-speed switching nodes (BST_, DH_, LX_,
ble, jitter-free operation. and DL_) away from sensitive analog areas (REF,
• Keep the power traces and load connections short. ILIM_, and FB_). Use PGND3 and PGND5 as an EMI
This practice is essential for high efficiency. Using shield to keep radiated switching noise away from the
thick copper PC boards (2oz vs. 1oz) can enhance IC’s feedback divider and analog bypass capacitors.

30 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
• Make all pin-strap control input connections (SKIP, very close to the device. Connect the AGND and

MAX8732A/MAX8733A/MAX8734A
ILIM_, etc.) to GND or VCC of the device. PGND planes together at the GND pin of the device.
Layout Procedure 5) On the board’s top side (power planes), make a
1) Place the power components first with ground ter- star ground to minimize crosstalk between the two
minals adjacent (N2/N4 source, CIN_, COUT_, D1 sides. The top-side star ground is a star connection
anode). If possible, make all these connections on of the input capacitors and synchronous rectifiers.
the top layer with wide, copper-filled areas. Keep the resistance low between the star ground
and the source of the synchronous rectifiers for
2) Mount the controller IC adjacent to the synchronous- accurate current limit. Connect the top-side star
rectifier MOSFETs, preferably on the back side to ground (used for MOSFET, input, and output
keep DH_, GND, and the DL_ gate drive lines short capacitors) to the small island with a single short,
and wide. The DL_ gate trace must be short and wide connection (preferably just a via).
wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1in from the controller device. Create PGND islands on the layer just below the
top-side layer (refer to the MAX1999 EV kit for an
3) Group the gate-drive components (BST_ diode and example) to act as an EMI shield if multiple layers
capacitor, V+ bypass capacitor) together near the are available (highly recommended). Connect each
controller device. of these individually to the star ground via, which
4) Make the DC-DC controller ground connections as connects the top side to the PGND plane. Add one
follows: near the device, create a small analog more solid ground plane under the device to act as
ground plane. Connect the small analog ground an additional shield, and also connect the solid
plane to GND (Figure 13) and use the plane for the ground plane to the star ground via.
ground connection for the REF and VCC bypass 6) Connect the output power planes (VCORE and system
capacitors, FB dividers, and ILIM resistors (if any). ground planes) directly to the output filter capacitor
Create another small ground island for PGND, and positive and negative terminals with multiple vias.
use the plane for the V+ bypass capacitor, placed
Table 5. MAX8732A/MAX8733A/MAX8734A and MAX1777/MAX1977/MAX1999 Differences
MAX8732A/MAX8733A/MAX8734A MAX1777/MAX1977/MAX1999

Improved line transient behavior requires only

a 0.1µF filter capacitor on V+. Allows fast A 4Ω/4.7µF filter capacitor is required on V+ to
Line Transient Behavior
rising-edge line transients of 10V/µs and limit the dV/dt on the V+ pin.
falling-edge line transients of 5V/µs.

Original “W” pattern conducts through the high-

Simplified Z pattern offers better efficiency
side MOSFET’s body diode, reducing efficiency.
Ultrasonic Mode and smoother transition into continuous-
Transition between ultrasonic mode and
conduction mode.
continuous-conduction mode is not as smooth.

LDO3 starts only after LDO5 is in regulation, LDO3 and LDO5 start up together at the current
LDO3 and LDO5 Sequencing reducing the inrush current when SHDN goes limit of each LDO, causing large inrush currents
high. through the 4Ω series resistor at V+.
Soft-shutdown (10Ω discharge feature) is
Soft-shutdown (10Ω discharge feature) is
enabled only after the 22ms (typ) startup
enabled immediately when an output is
Soft-Shutdown Enable Delay undervoltage blanking time. This causes DL_ to
enabled, and is not dependent on the 22ms
be driven high if the part is commanded to turn
(typ) startup undervoltage blanking timer.
off before the 22ms timer.
When LDO5 falls below its 4V (typ) UVLO
When LDO5 falls below its 4V (typ) UVLO
threshold, DH_ and DL_ are immediately
threshold, DH_ is immediately pulled low and
High-Output Impedance in UVLO pulled low, and the outputs are high
DL_ forced high to clamp the output rails. This
impedance. The outputs are discharged by
causes the outputs to swing below ground.
the load.

______________________________________________________________________________________ 31
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Ordering Information (continued) Pin Configurations (continued)
MAX8732A/MAX8733A/MAX8734A

5V/3V
PIN- SWITCHING TOP VIEW
PART TEMP RANGE
PACKAGE FREQUENCY
CS3 1 28 BST3
(kHz)
PGOOD 2 27 LX3
200/300 or
MAX8734AEEI+ -40°C to +85°C 28 QSOP ON3 3 26 DH3
400/500
ON5 4 25 LDO3
MAX8734AEEI -40°C to +85°C 28 QSOP 400kHz/500 ILIM3 5 24 DL3
MAX8732A
+Denotes lead free package. SHDN 6 MAX8733A 23 GND

FB3 7 22 OUT3

REF 8 21 OUT5

FB5 9 20 V+

PRO 10 19 DL5

ILIM5 11 18 LDO5

SKIP 12 17 VCC

CS5 13 16 DH5

BST5 14 15 LX5

QSOP

Chip Information
TRANSISTOR COUNT: 8335
PROCESS: BiCMOS

32 ______________________________________________________________________________________
 High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Package Information

MAX8732A/MAX8733A/MAX8734A
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055 E 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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