19-0767; Rev 2; 10/09

3A, 2MHz Step-Down Regulator

with Integrated Switches
General Description Features

MAX8643A
The MAX8643A high-efficiency switching regulator o Internal 37mΩ RDSON MOSFETs
delivers up to 3A load current at output voltages from o Continuous 3A Output Current
0.6V to (0.9 x VIN). The IC operates from 2.35V to 3.6V,
making it ideal for on-board point-of-load and postregu- o ±1% Output Accuracy Over Load, Line,
lation applications. Total output error is less than ±1% and Temperature
over load, line, and temperature. o Operates from 2.35V to 3.6V Supply
The MAX8643A features fixed-frequency PWM mode o Adjustable Output from 0.6V to (0.9 x VIN)
operation with a switching frequency range of 500kHz o Soft-Start Reduces Inrush Supply Current
to 2MHz set by an external resistor. High-frequency o 500kHz to 2MHz Adjustable Switching Frequency
operation allows for an all-ceramic capacitor design.
The high operating frequency also allows for small-size o Compatible with Ceramic, Polymer, and
external components. Electrolytic Output Capacitors
The low-resistance on-chip nMOS switches ensure high o VID-Selectable Output Voltages
efficiency at heavy loads while minimizing critical induc- 0.6, 0.7, 0.8, 1.0, 1.2, 1.5, 1.8, 2.0, and 2.5V
tances, making the layout a much simpler task with o Fully Protected Against Overcurrent
respect to discrete solutions. Following a simple layout and Overtemperature
and footprint ensures first-pass success in new designs. o Safe-Start into Prebiased Output
The MAX8643A comes with a high-bandwidth (> 14MHz) o Sink/Source Current in DDR Applications
voltage-error amplifier. The voltage-mode control archi-
tecture and the voltage-error amplifier permit a type III o Lead-Free, 24-Pin, 4mm x 4mm Thin QFN Package
compensation scheme to be utilized to achieve maxi-
mum loop bandwidth, up to 20% of the switching fre- Ordering Information
quency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance PART TEMP RANGE PIN-PACKAGE
and allowing for all-ceramic capacitor designs. MAX8643AETG+ -40°C to +85°C 24 Thin QFN-EP*
The MAX8643A provides two three-state logic inputs to MAX8643AETG/V+ -40°C to +85°C 24 Thin QFN-EP*
select one of nine preset output voltages. The preset +Denotes a lead(Pb)-free/RoHS-compliant package.
output voltages allow customers to achieve ±1% out- /V denotes an automotive qualified part.
put-voltage accuracy without using expensive 0.1% *EP = Exposed pad.
resistors. In addition, the output voltage can be set to
any customer value by either using two external resis-
tors at the feedback with 0.6V internal reference or Typical Operating Circuit
applying an external reference voltage to the REFIN INPUT
input. The MAX8643A offers programmable soft-start 2.4V TO 3.6V
IN BST
time using one capacitor to reduce input inrush current.
OUTPUT
The MAX8643A is available in a lead-free, 24-pin, 4mm EN
MAX8643A 1.8V, 3A
x 4mm thin QFN package. LX
VDD
Applications OUT

POLs PGND
CTL1
ASIC/CPU/DSP Core and I/O Voltages
CTL2 FB
DDR Power Supplies
FREQ
Base-Station Power Supplies
REFIN
Telecom and Networking Power Supplies SS COMP
VDD

RAID Control Power Supplies

PREBIAS PWRGD
GND
Pin Configuration appears at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
 3A, 2MHz Step-Down Regulator
with Integrated Switches
ABSOLUTE MAXIMUM RATINGS
MAX8643A

IN, VDD, PWRGD to GND ......................................-0.3V to +4.5V Continuous Power Dissipation (TA = +70°C)
COMP, FB, REFIN, OUT, 24-Pin TQFN-EP
CTL_, EN, SS, FREQ to GND...................-0.3V to (VDD + 0.3V) (derated 27.8mW/°C above +70°C)........................2222.2mW
LX Current (Note 1) .....................................................-4A to +4A Operating Temperature Range ...........................-40°C to +85°C
BST to LX..................................................................-0.3V to +4V Junction Temperature ......................................................+150°C
PGND to GND .......................................................-0.3V to +0.3V Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VIN = VDD = 3.3V, VFB = 0.5V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

IN/VDD
IN and VDD Voltage Range 2.35 3.60 V
fS = 1MHz, no load VIN = 2.5V 4 4.6
IN Supply Current mA
(includes gate-drive current) VIN = 3.3V 5.5
VIN = 2.5V 1.4 2.3
VDD Supply Current fS = 1MHz mA
VIN = 3.3V 2
Total Shutdown Current from IN
VIN = VDD = VBST - VLX = 3.6V, VEN = 0V 13 µA
and VDD
VDD rising 2 2.1
VDD Undervoltage Lockout V
LX starts/stops switching VDD falling 1.8 1.9
Threshold
Deglitching 2 µs
BST
VBST = VDD = VIN = 3.6V, TA = +25°C 5
BST Supply Current µA
VLX = 3.6V or 0V, VEN = 0V TA = +85°C 10
PWM COMPARATOR
PWM Comparator Propagation
10mV overdrive 20 ns
Delay
COMP
COMP Clamp Voltage, High VIN = 2.35V to 3.6V 2 V
COMP Slew Rate 1.4 V/µs
PWM Ramp Amplitude 1 V
COMP Shutdown Resistance From COMP to GND, VEN = VSS = 0V 8 Ω
ERROR AMPLIFIER
Select
Preset Output-Voltage Accuracy REFIN = SS -1 from +1 %
Table 1
FB Regulation Accuracy Using
CTL1 = CTL2 = GND 0.594 0.600 0.606 V
External Resistors
FB to OUT Resistor All VID settings except CTL1 = CTL2 = GND 5 8 11 kΩ

2 _______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)

MAX8643A
(VIN = VDD = 3.3V, VFB = 0.5V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Open-Loop Voltage Gain 1kΩ from COMP to GND 115 dB
Error-Amplifier Unity-Gain
Parallel 10kΩ, 40pF from COMP to GND (Note 3) 14 26 MHz
Bandwidth
Error-Amplifier Common-Mode VDD = 2.35V to 2.6V 0 VDD - 1.65
V
Input Range VDD = 2.6V to 3.6V 0 VDD - 1.7
Error-Amplifier Minimum Output Sourcing 1000
VCOMP = 1V µA
Current Sinking -500
VFB = 0.7V, CTL1 = CTL2 =
FB Input Bias Current TA = +25°C -200 -40 nA
GND
CTL_
VCTL_ = 0V -7
CTL_ Input Bias Current µA
VCTL_ = VDD +7
Rising 0.75
High-Impedance Threshold VDD V
Falling
- 1.2V
Hysteresis All VID transitions 50 mV
REFIN
REFIN Input Bias Current VREFIN = 0.6V TA = +25°C -500 -100 nA
VDD = 2.3V to 2.6V 0 VDD - 1.65
REFIN Common-Mode Range V
VDD = 2.6V to 3.6V 0 VDD - 1.7
REFIN Offset Voltage CTL1 = CTL2 = GND, TA = +25°C -3 +3 mV
LX (ALL PINS COMBINED)
VIN = VBST - VLX = 2.5V 39
LX On-Resistance, High Side ILX = -2A mΩ
VIN = VBST - VLX = 3.3V 37 58
VIN = 2.5V 36
LX On-Resistance, Low Side ILX = 2A mΩ
VIN = 3.3V 34 55
LX Current-Limit Threshold VIN = 2.5V, high-side sourcing 4 5.5 A
VLX = 0V -2
TA = +25°C
VLX = 3.6V +2
LX Leakage Current VIN = 3.6V, VEN = VSS = 0V µA
VLX = 0V 1
TA = +85°C
VLX = 3.6V 1
RFREQ = 50kΩ 0.9 1 1.1
LX Switching Frequency VIN = 2.5V to 3.3V MHz
RFREQ = 23.2kΩ 1.8 2.0 2.2
Frequency Range 500 2000 kHz
LX Minimum Off-Time VIN = 2.5V to 3.3V 40 75 ns
LX Maximum Duty Cycle RFREQ = 50kΩ, VIN = 2.5V to 3.3V 93 96 %
LX Minimum On-Time 80 ns
RMS LX Output Current 3 A

_______________________________________________________________________________________ 3
 3A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)
MAX8643A

(VIN = VDD = 3.3V, VFB = 0.5V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

ENABLE
EN Input Logic-Low, Falling 1.2 0.7 V
EN Input Logic-High, Rising 1.7 1.4 V
EN Hysteresis 200 mV
VEN = 0V or 3.6V, TA = +25°C 1
EN, Input Current µA
VDD = 3.6V TA = +85°C 0.01
SS
SS Charging Current VSS = 0.45V 7 8 9 µA
SS Discharge Resistance 500 Ω
THERMAL SHUTDOWN
Thermal-Shutdown Threshold +165 °C
Thermal-Shutdown Hysteresis 20 °C
POWER-GOOD (PWRGD)
Power-Good Threshold Voltage VFB falling, 3mV hysteresis 87 90 93 %
Clock
Power-Good Falling-Edge Deglitch 48
cycles
PWRGD Output-Voltage Low IPWRGD = 4mA 0.03 0.15 V
PWRGD Leakage Current VDD = VPWRGD = 3.6V, VFB = 0.9V 0.01 µA
OVERCURRENT LIMIT
Clock
Current-Limit Startup Blanking 128
cycles
Clock
Restart Time 1024
cycles
Note 2: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and characterization.
Note 3: Guaranteed by design.

Typical Operating Characteristics

(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 3A, and TA = +25°C, unless otherwise noted.)

EFFICIENCY vs. OUTPUT CURRENT EFFICIENCY vs. OUTPUT CURRENT

100 100
MAX8643A toc02
MAX8643A toc01

95
90
90
80
EFFICIENCY (%)

VOUT = 2.5V
EFFICIENCY (%)

85
VOUT = 1.88V
70 VOUT = 1.8V 80
VOUT = 1.5V
VOUT = 1.2V 75
60
70 VOUT = 1.2V
50
65
VIN = VDD = 3.3V VIN = VDD = 2.5V
40 60
0.1 1 10 0.1 1 10
OUTPUT CURRENT (A) OUTPUT CURRENT (A)

4 _______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)

MAX8643A
(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 3A, and TA = +25°C, unless otherwise noted.)

EFFICIENCY vs. OUTPUT CURRENT FREQUENCY vs. INPUT VOLTAGE LOAD REGULATION
100 0

MAX8643A toc03

MAX8643A toc04

MAX8643A toc05
1950 VIN = VDD = 3.3V
95 -0.02
+85°C

OUTPUT VOLTAGE CHARGE (%)

1800 -40°C +25°C
90 -0.04 VOUT = 2.5V
FREQUENCY (kHz)
1650
EFFICIENCY (%)

85 -0.06
VOUT = 1.8V
80 1500 -0.08 VOUT = 1.8V
VOUT = 1.5V
75 1350 -0.10

70 VOUT = 1.2V 1200 -0.12

-40°C +25°C +85°C
65 VIN = 2.5V 1050 -0.14 VOUT = 1.2V
VDD = 3.3V
60 900 -0.16
0.1 1 10 2.2 2.6 3.0 3.4 3.8 0 1 2 3 4 5
OUTPUT CURRENT (A) INPUT VOLTAGE (V) LOAD CURRENT (A)

LOAD TRANSIENT SWITCHING WAVEFORMS

MAX8643A toc06 MAX8643A toc07

VIN = VDD = 3.3V

VOUT AC-COUPLED
AC-COUPLED 20mV/div
VOUT 50mV/div

2A/div
ILX

0A

IOUT VLX
1A/div 2V/div
0V

0A
40µs/div 100ns/div

SOFT-START WAVEFORMS SHUTDOWN WAVEFORMS

MAX8643A toc08 MAX8643A toc09

VEN 2V/div
VEN 2V/div
0V 0V

VOUT 1V/div

VOUT 1V/div 0V

0V
RLOAD = 1Ω RLOAD = 1Ω

400µs/div 10µs/div

_______________________________________________________________________________________ 5
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
MAX8643A

(Typical values are at VIN = VDD = 3.3V, VOUT = 1.8V, RFREQ = 50kΩ, IOUT = 3A, and TA = +25°C, unless otherwise noted.)

INPUT CURRENT vs. INPUT VOLTAGE CURRENT LIMIT vs. OUTPUT VOLTAGE HICCUP CURRENT LIMIT
MAX8643A toc12
10 7

MAX8643A toc10

MAX8643A toc11
9 VEN = 0V
6 VOUT 1V/div
8
0V
7 5
INPUT CURRENT (µA)

CURRENT LIMIT (A)

6
4
5 IOUT 5A/div
4 3
0A
3 2
2
1 IIN
1 1A/div
0 0 0A
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0.5 1.0 1.5 2.0 2.5 400µs/div
INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

RMS INPUT CURRENT DURING SHORT CIRCUIT EXPOSED PAD TEMPERATURE

vs. INPUT VOLTAGE (C4 = 0.022µF) vs. AMBIENT TEMPERATURE FEEDBACK VOLTAGE vs. TEMPERATURE
0.50 110 0.64
MAX8643A toc14

MAX8643A toc15
MAX8643A toc13

VOUT = 0V VOUT = 1.8V

0.45 100 3A LOAD 0.63
EXPOSED PAD TEMPERATURE (°C)

0.40 90
0.62
RMS INPUT CURRENT (A)

FEEDBACK VOLTAGE (V)

0.35 80
70 0.61
0.30
0.25 60 0.60
0.20 50 0.59
0.15 40
0.58
0.10 30
20 0.57
0.05
MEASURED ON A MAX8643EVKIT
0 10 0.56
2.0 2.5 3.0 3.5 4.0 0 20 40 60 80 100 -40 -15 10 35 60 85
INPUT VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)

SOFT-START WITH REFIN STARTING INTO PREBIAS OUTPUT

MAX8643A toc16 MAX8643A toc17

2V/div
IIN 1A/div VEN
0V
0A

VREFIN 0.5V/div
VOUT 1V/div
0V
0V
VOUT 1V/div 2V/div
0V VPWRGD
0V
VPWRGD 2V/div
0V
200µs/div 100µs/div
CSS = 6800pF, CO = 122µF, L = 0.56µH, VOUT = 2.5V

6 _______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Pin Description

MAX8643A
PIN NAME FUNCTION
Leave pin unconnected to prevent discharging of output capacitor during soft-start. Connect to GND
1 PREBIAS
otherwise. (See the Soft-Starting into a Prebiased Output section.)
Supply Voltage and Bypass Input. Connect VDD to IN with a 10Ω resistor. Connect a 1µF ceramic
2 VDD
capacitor from VDD to GND.
CTL1, Preset Output Voltage Selection Input. CTL1 and CTL2 set the output voltage to one of nine preset
3, 4
CTL2 voltages. See Table 1 for preset voltages.

External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
5 REFIN external reference voltage forces FB to regulate the voltage applied to REFIN. REFIN is internally pulled to
GND when the IC is in shutdown mode.

Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN
6 SS
section for details on setting the soft-start time.
7 GND Analog Circuit Ground
Output of the Voltage-Error Amplifier. Connect the necessary compensation network from COMP to FB.
8 COMP
COMP is internally pulled to GND when the IC is in shutdown mode.

Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set
9 FB the output voltage from 0.6V to 90% of VIN. Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.

Output Voltage Sense. Connect to the output. Leave OUT unconnected when an external resistor-divider
10 OUT
is used.
11 FREQ Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching frequency.
Power-Good Output. Open-drain output that is high impedance when VFB ≥ 90% of VREFIN or 0.6V. PWRGD is
12 PWRGD internally pulled low when VFB falls below 90% of its regulation point. PWRGD is internally pulled low when the
IC is in shutdown mode, VDD or VIN is below the UVLO threshold, or the IC is in thermal shutdown.
13 BST High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor.
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the output
14, 15, 16 LX
inductor. LX is high impedance when the IC is in shutdown mode.
17–20 PGND Power Ground. Connect all PGND pins externally to the power ground plane.
Power-Supply Input. Input supply range is from 2.35V to 3.6V. Bypass with 22µF ceramic capacitance to
21, 22, 23 IN
PGND externally. See the Typical Application Circuit.
24 EN Enable Input. Logic input to enable/disable the MAX8643A.
— EP Exposed Pad. Connect to a large ground plane to optimize thermal performance.

_______________________________________________________________________________________ 7
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Block Diagram
MAX8643A

VDD

MAX8643A

SHUTDOWN UVLO
EN CONTROL CIRCUITRY

CURRENT-LIMIT
COMPARATOR

BIAS
LX
GENERATOR
ILIM THRESHOLD
BST

IN
VOLTAGE
REFERENCE BST CAPACITOR
CHARGING SWITCH

SS SOFT-START
CONTROL
LOGIC LX
IN

THERMAL
SHUTDOWN
REFIN
PGND
OUT
ERROR
8kΩ AMPLIFIER PWM
COMPARATOR
PREBIAS
FB

CTL1 VID
VOLTAGE-
CONTROL
CTL2 CIRCUITRY
1VP-P FREQ
OSCILLATOR

COMP

SHDN PWRGD

COMP LOW FB
DETECTOR
0.9 x VREFIN GND

8 _______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Application Circuit

MAX8643A
INPUT
2.4V TO 3.6V 23 13
IN BST C9 R10
C1 C3 22 0.1µF 2.2Ω
22µF 0.1µF IN U1
R1 21
IN 16 C15
10Ω VDD LX
MAX8643A L1 1000pF
15 OUTPUT
LX 0.56µH
2 14 1.8V/3A
VDD LX
C5 10
1µF R2 OUT
10kΩ 20 R6
PGND
100Ω C2 C4 C14
24 19
EN PGND 1% 100µF 0.01µF 22µF
C6 18, 17 C10
0.01µF PGND 1500pF
7
GND
3 9
CTL1 FB

4
CTL2 C11 R4
560pF 18kΩ
5 8
REFIN COMP
VDD
C12
6 10pF
SS 12
PWRGD
C8 11 R5
6800pF PREBIAS GND FREQ 20kΩ
R7
1 7 24kΩ
1%

Figure 1. 1MHz, All-Ceramic Capacitor Design with VOUT = 1.8V

Detailed Description pensation to fully utilize the bandwidth of the high-fre-

quency switching to obtain fast transient response.
The MAX8643A high-efficiency, voltage-mode switch-
Adjustable soft-start time provides flexibilities to mini-
ing regulator is capable of delivering up to 3A of output
mize input startup inrush current. An open-drain,
current. The MAX8643A provides output voltages from
power-good (PWRGD) output goes high when V FB
0.6V to (0.9 x VIN) from 2.35V to 3.6V input supplies,
reaches 90% of VREFIN or 0.54V.
making it ideal for on-board point-of-load applications.
The output voltage accuracy is better than ±1% over Controller Function
load, line, and temperature. The controller logic block is the central processor that
The MAX8643A features a wide switching frequency determines the duty cycle of the high-side MOSFET
range, allowing the user to achieve all-ceramic capaci- under different line, load, and temperature conditions.
tor designs and fast transient responses. The high oper- Under normal operation, where the current-limit and
ating frequency minimizes the size of external temperature protection are not triggered, the controller
components. The MAX8643A is available in a small logic block takes the output from the PWM comparator
(4mm x 4mm), lead-free, 24-pin thin QFN package. The and generates the driver signals for both high-side and
REFIN function makes the MAX8643A an ideal candi- low-side MOSFETs. The break-before-make logic and
date for DDR and tracking power supplies. Using inter- the timing for charging the bootstrap capacitors are
nal low-RDSON (37mΩ) n-channel MOSFETs for both calculated by the controller logic block. The error signal
high- and low-side switches maintains high efficiency at from the voltage-error amplifier is compared with the
both heavy-load and high-switching frequencies. ramp signal generated by the oscillator at the PWM
comparator and, thus, the required PWM signal is pro-
The MAX8643A employs voltage-mode control archi-
duced. The high-side switch is turned on at the begin-
tecture with a high-bandwidth (> 14MHz) error amplifi-
ning of the oscillator cycle and turns off when the ramp
er. The voltage-mode control architecture allows up to
voltage exceeds the VCOMP signal or the current-limit
2MHz switching frequency, reducing board area. The
threshold is exceeded. The low-side switch is then
op-amp voltage-error amplifier works with type III com-
turned on for the remainder of the oscillator cycle.

_______________________________________________________________________________________ 9
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Current Limit Undervoltage Lockout (UVLO)
MAX8643A

The internal, high-side MOSFET has a typical 5.5A The UVLO circuitry inhibits switching when V DD is
peak current-limit threshold. When current flowing out below 2V (typ). Once VDD rises above 2V (typ), UVLO
of LX exceeds this limit, the high-side MOSFET turns off clears and the soft-start function activates. A 100mV
and the synchronous rectifier turns on. The synchro- hysteresis is built in for glitch immunity.
nous rectifier remains on until the inductor current falls
below the low-side current limit. This lowers the duty BST
cycle and causes the output voltage to droop until the The gate-drive voltage for the high-side, n-channel
current limit is no longer exceeded. The MAX8643A switch is generated by a flying-capacitor boost circuit.
uses a hiccup mode to prevent overheating during The capacitor between BST and LX is charged from the
short-circuit output conditions. VIN supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
During current limit if V FB drops below 420mV and capacitor is stacked above LX to provide the necessary
stays below this level for 12µs or more, the part enters turn-on voltage for the high-side internal MOSFET.
hiccup mode. The high-side MOSFET and the synchro-
nous rectifier are turned off and both COMP and REFIN Frequency Select (FREQ)
are internally pulled low. If REFIN and SS are connect- The switching frequency is resistor programmable from
ed together, then both are pulled low. The part remains 500kHz to 2MHz. Set the switching frequency of the IC
in this state for 1024 clock cycles and then attempts to with a resistor (RFREQ) connected from FREQ to GND.
restart for 128 clock cycles. If the fault-causing current RFREQ is calculated as:
limit has cleared, the part resumes normal operation.
Otherwise, the part reenters hiccup mode again. 50kΩ 1
RFREQ = ×( − 0.05µs)
Soft-Start and REFIN 0.95µs fS
The MAX8643A utilizes an adjustable soft-start function where fS is the desired switching frequency in Hz.
to limit inrush current during startup. An 8µA (typ) cur-
rent source charges an external capacitor connected to Power-Good Output (PWRGD)
SS. The soft-start time is adjusted by the value of the PWRGD is an open-drain output that goes high imped-
external capacitor from SS to GND. The required ance when VFB is above 0.9 x VREFIN. PWRGD pulls
capacitance value is determined as: low when VFB is below 90% of its regulation for at least
48 clock cycles. PWRGD is low during shutdown.
8µA × t SS
C= Programming the Output Voltage
0.6V (CTL1, CTL2)
where tSS is the required soft-start time in seconds. The As shown in Table 1, the output voltage is pin program-
MAX8643A also features an external reference input mable by the logic states of CTL1 and CTL2. CTL1 and
(REFIN). The IC regulates FB to the voltage applied to CTL2 are tri-level inputs: VDD, unconnected, and GND.
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start Table 1. CTL1 and CTL2 Output Voltage
when using an external reference is shown in Figure 2. Selection
Connect REFIN to SS to use the internal 0.6V reference.
CTL1 CTL2 VOUT (V)
GND GND 0.6
R1 VDD VDD 0.7
REFIN GND Unconnected 0.8
GND VDD 1.0
R2 C MAX8643A Unconnected GND 1.2
Unconnected Unconnected 1.5
Unconnected VDD 1.8
VDD GND 2.0
Figure 2. Typical Soft-Start Implementation with External VDD Unconnected 2.5
Reference

10 ______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
The logic states of CTL1 and CTL2 should be pro- put ripple occurs due to variations in the charge stored

MAX8643A
grammed only before power-up. Once the part is in the output capacitor, the voltage drop due to the
enabled, CTL1 and CTL2 should not be changed. If the capacitor’s ESR, and the voltage drop due to the
output voltage needs to be reprogrammed, cycle capacitor’s ESL. Calculate the output voltage ripple
power or EN and reprogram before enabling. due to the output capacitance, ESR, and ESL:
Shutdown Mode VRIPPLE = VRIPPLE(C) +
Drive EN to GND to shut down the IC and reduce quies- VRIPPLE(ESR) + VRIPPLE(ESL)
cent current to less than 12µA. During shutdown, the LX
is high impedance. Drive EN high to enable the where the output ripple due to output capacitance,
MAX8643A. ESR, and ESL is:
Thermal Protection IP−P
VRIPPLE(C) =
Thermal-overload protection limits total power dissipation 8 x COUT x fS
in the device. When the junction temperature exceeds TJ
= +165°C, a thermal sensor forces the device into shut- VRIPPLE(ESR) = IP−P x ESR
down, allowing the die to cool. The thermal sensor turns
the device on again after the junction temperature cools
I
by 20°C, causing a pulsed output during continuous VRIPPLE(ESL) = P−P x ESL
overload conditions. The soft-start sequence begins after t ON
recovery from a thermal-shutdown condition.
I
Applications Information VRIPPLE(ESL) = P−P x ESL
t OFF
IN and VDD Decoupling or whichever is larger.
To decrease the noise effects due to the high switching The peak inductor current (IP-P) is:
frequency and maximize the output accuracy of
the MAX8643A, decouple VIN with a 22µF capacitor V − VOUT V
from VIN to PGND. Also decouple VDD with a 1µF from IP−P = IN x OUT
VDD to GND. Place these capacitors as close to the IC fS × L VIN
as possible. Use these equations for initial capacitor selection.
Inductor Selection Determine final values by testing a prototype or an
Choose an inductor with the following equation: evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
VOUT × (VIN − VOUT ) is a factor of the inductor value, the output voltage rip-
L= ple decreases with larger inductance. Use ceramic
fS × VIN × LIR × IOUT(MAX)
capacitors for low ESR and low ESL at the switching
where LIR is the ratio of the inductor ripple current to full frequency of the converter. The ripple voltage due to
load current at the minimum duty cycle. Choose LIR ESL is negligible when using ceramic capacitors.
between 20% to 40% for best performance and stability. Load-transient response depends on the selected out-
Use an inductor with the lowest possible DC resistance put capacitance. During a load transient, the output
that fits in the allotted dimensions. Powdered iron ferrite instantly changes by ESR x ∆ILOAD. Before the con-
core types are often the best choice for performance. troller can respond, the output deviates further,
With any core material, the core must be large enough depending on the inductor and output capacitor val-
not to saturate at the current limit of the MAX8643A. ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
Output-Capacitor Selection value. The controller response time depends on the
The key selection parameters for the output capacitor are closed-loop bandwidth. A higher bandwidth yields a
capacitance, ESR, ESL, and voltage-rating requirements. faster response time, preventing the output from deviat-
These affect the overall stability, output ripple voltage, ing further from its regulating value. See the Compen-
and transient response of the DC-DC converter. The out- sation Design section for more details.

______________________________________________________________________________________ 11
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Input-Capacitor Selection parallel, the value of the ESR in the above equation is
MAX8643A

The input capacitor reduces the current peaks drawn equal to that of the ESR of a single output capacitor
from the input power supply and reduces switching divided by the total number of output capacitors.
noise in the IC. The total input capacitance must be The high switching frequency range of the MAX8643A
equal to or greater than the value given by the following allows the use of ceramic output capacitors. Since the
equation to keep the input ripple voltage within specs ESR of ceramic capacitors is typically very low, the fre-
and minimize the high-frequency ripple current being quency of the associated transfer function zero is higher
fed back to the input source: than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole creat-
D x t S x IOUT ed by the output filtering inductor and capacitor. The dou-
CIN _ MIN =
VIN − RIPPLE ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°/decade. The error amplifier must com-
where VIN-RIPPLE is the maximum allowed input ripple pensate for this gain drop and phase shift to achieve a
voltage across the input capacitors and is recommend- stable high-bandwidth closed-loop system. Therefore,
ed to be less than 2% of the minimum input voltage. D use type III compensation as shown in Figure 3 and
is the duty cycle (VOUT/VIN), and tS is the switching Figure 4. Type III compensation possesses three poles
period (1/fS). and two zeros with the first pole, fP1_EA, located at zero
The impedance of the input capacitor at the switching frequency (DC). Locations of other poles and zeros of the
frequency should be less than that of the input source so type III compensation are given by:
high-frequency switching currents do not pass through 1
the input source but are instead shunted through the fZ1_ EA =
2π x R1 x C1
input capacitor. High source impedance requires high
input capacitance. The input capacitor must meet the
ripple current requirement imposed by the switching cur- L VOUT
LX
rents. The RMS input ripple current is given by:
COUT
R2
VOUT × (VIN − VOUT ) MAX8643A
R3
IRIPPLE = ILOAD × OUT
VIN C3
FB
CTL1
where IRIPPLE is the input RMS ripple current. R1 C1
CTL2 COMP R4
Compensation Design
The power transfer function consists of one double pole C2
and one zero. The double pole is introduced by the out-
put filtering inductor, L, and the output filtering capacitor, a) EXTERNAL RESISTOR-DIVIDER
CO. The ESR of the output filtering capacitor determines
the zero. The double pole and zero frequencies are L VOUT
given as follows: LX
1 COUT
fP1_ LC = fP2 _ LC = MAX8643A R2
⎛ R + ESR ⎞
2π x L x C O x ⎜ O ⎟ OUT
⎝ RO + RL ⎠
R3
1 8kΩ
fZ _ ESR = C3
2π x ESR x CO
FB
where RL is equal to the sum of the output inductor’s R1 C1
VOLTAGE CTL1
DCR and the internal switch resistance, RDSON. A typical COMP
SELECT
value for RDSON is 37mΩ. RO is the output load resis- CTL2
C2
tance, which is equal to the rated output voltage divided
by the rated output current. ESR is the total equivalent
series resistance of the output filtering capacitor. If there b) INTERNAL PRESET VOLTAGE
is more than one output capacitor of the same type in Figure 3. Type III Compensation Network

12 ______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Due to the underdamped nature of the output LC dou-

MAX8643A
COMPENSATION ble pole, set the two zero frequencies of the type III
OPEN-LOOP
TRANSFER GAIN compensation less than the LC double-pole frequency
FUNCTION to provide adequate phase boost. Set the two zero fre-
THIRD quencies to 80% of the LC double-pole frequency.
DOUBLE POLE POLE
Hence:
GAIN (dB)
1 L x CO x (RO + ESR)
SECOND
R1 = x
POWER-STAGE
POLE 0.8 x C1 RL + RO
TRANSFER
FUNCTION
1 L x CO x (RO + ESR)
FIRST AND SECOND ZEROS C3 = x
0.8 x R 3 RL + RO
Setting the second compensation pole, f P2_EA , at
Figure 4. Type III Compensation Illustration fZ_ESR yields:
1
fZ2 _ EA = CO x ESR
2π x R3 x C3 R2 =
C3
1
fP3 _ EA = Set the third compensation pole at 1/2 of the switching
2π x R1 x C2 frequency to gain some phase margin. Calculate C2 as
1 follows:
fP2 _ EA = 1
2π x R2 x C3 C2 =
π x R1 x fS × 2
The above equations are based on the assumptions that
C1>>C2 and R3>>R2 are true in most applications. The above equations provide accurate compensation
Placements of these poles and zeros are determined by when the zero-cross frequency is significantly higher
the frequencies of the double pole and ESR zero of the than the double-pole frequency. When the zero-cross
power transfer function. It is also a function of the frequency is near the double-pole frequency, the actual
desired closed-loop bandwidth. The following section zero-cross frequency is higher than the calculated fre-
outlines the step-by-step design procedure to calculate quency. In this case, lowering the value of R1 reduces
the required compensation components for the the zero-cross frequency. Also, set the third pole of the
MAX8643A. When the output voltage of the MAX8643A type III compensation close to the switching frequency
is programmed to a preset voltage, R3 is internal to the if the zero-cross frequency is above 200kHz to boost
IC and R4 does not exist (Figure 3b). the phase margin. The recommended range for R3 is
2kΩ to 10kΩ. Note that the loop compensation remains
When externally programming the MAX8643A (Figure
unchanged if only R4’s resistance is altered to set dif-
3a), the output voltage is determined by:
ferent outputs.
0.6 × R3 Soft-Starting into a Prebiased Output
R4 =
(VOUT − 0.6) When the PREBIAS pin is left unconnected, the
MAX8643A is capable of soft-starting up into a prebiased
The zero-cross frequency of the closed-loop, fC, should output without discharging the output capacitor. This
be between 10% and 20% of the switching frequency, type of operation is also termed monotonic startup.
fS. A higher zero-cross frequency results in faster tran- However, in order to avoid output voltage glitches during
sient response. Once fC is chosen, C1 is calculated soft-start, it should be ensured that the inductor current
from the following equation: is in continuous conduction mode during the end of the
soft-start period. This is done by satisfying the following
1.5625 VIN equation:
C1 =
R
2 x π x R3 x (1 + L ) × fC V I
RO CO × O ≥ P−P
t SS 2

______________________________________________________________________________________ 13
 3A, 2MHz Step-Down Regulator
with Integrated Switches
where CO is the output capacitor, VO is the output volt- 4) Connect IN, LX, and PGND separately to a large
MAX8643A

age, tSS is the soft-start time set by the soft-start capacitor copper area to help cool the IC to further improve
CSS, and IP-P is the peak-to-peak inductor ripple current efficiency and long-term reliability.
(as defined in the Output-Capacitor Selection section). 5) Ensure all feedback connections are short and
Depending on the application, one of these parameters direct. Place the feedback resistors and compensa-
may drive the selection of the others. See the Starting into tion components as close to the IC as possible.
Prebias Output waveform in the Typical Operating
Characteristics section for an example selection of the 6) Route high-speed switching nodes, such as LX,
above parameters. Connecting the PREBIAS pin to GND away from sensitive analog areas (FB, COMP).
disables the prebias soft-start feature and causes the
MAX8643A to discharge any voltage present on the out-
put capacitors and then commence its soft-start. Pin Configuration
PCB Layout Considerations and
Thermal Performance TOP VIEW

PGND

PGND
Careful PCB layout is critical to achieve clean and stable

BST
LX
LX

LX
operation. It is highly recommended to duplicate the
18 17 16 15 14 13
MAX8643 EV kit layout for optimum performance. If devia-
tion is necessary, follow these guidelines for good PCB PGND 19 12 PWRGD
layout: PGND 20 11 FREQ
1) Connect input and output capacitors to the power IN 21 10 OUT
ground plane; connect all other capacitors to the sig-
IN 22 MAX8643A 9 FB
nal ground plane.
IN 23 8 COMP
2) Place capacitors on VDD, VIN, and SS as close as
*EP
possible to the IC and its corresponding pin using EN 24 7 GND
direct traces. Keep power ground plane (connected +
1 2 3 4 5 6
to PGND) and signal ground plane (connected to
PREBIAS

VDD

CTL1
CTL2

REFIN

SS
GND) separate.
3) Keep the high-current paths as short and wide as
THIN QFN
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the out- *EP = EXPOSED PAD.
put capacitors, and the input capacitors.

14 ______________________________________________________________________________________
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Chip Information Package Information

MAX8643A
PROCESS: BiCMOS For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

24 TQFN-EP T2444+4 21-0139

______________________________________________________________________________________ 15
 3A, 2MHz Step-Down Regulator
with Integrated Switches
Revision History
MAX8643A

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 3/07 Initial release —
Updated Features, Electrical Characteristics, Figure 1, and Controller Function
1 9/07 section. 1, 2, 4, 8, 9, 13

2 10/09 Added MAX8643A automotive package to Ordering Information. 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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