General Purpose Timers
Chapter 15
Timer
• Free-run counter (independent of processor)
• Functions
– Input capture
– Output compare
– Pulse-width modulation (PWM) generation
2
Block
Diagram
Timer: Clock
Reload Value ARR
Reload
fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt
!"(_)*"
!"#_"%& =
+,- + 1
4
Timer: Output
Reload Value ARR
Reload
fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt
Timer Output
= (OCREF)
Compare &
Capture
Register (CCR)
5
Timer: Input Capture
Reload Value ARR
Reload
fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt
Compare &
Capture
Register (CCR)
6
Multi-Channel Outputs
Each timer has four channels. Each channel has its own Compare and Capture
Register. CCR1, CCR2, CCR3, CCR4. These four channels share the timer
counter
Compare
& Capture
Register
(CCR)
7
GP Timer Block Diagram
ARR (Autoloaded Register)
Output Compare
Output Compare Mode (OCM) Timer Output (OCREF)
000 Frozen
001 High if CNT == CCR
010 Low if CNT == CCR
011 Toggle if CNT == CCR
100 Forced low (always low)
101 Forced high (always high)
9
Counting up, down, center
0,1,2,3,4,0,1,2…..
4,3,2,1,0,4,3,2….
0,1,2,3,4,3,2,1,0,1,2…
10
PWM Mode
Mode Counter < Reference Counter ≥ Reference
PWM mode 1
Active Inactive
(Low True)
PWM mode 2
Inactive Active
(High True)
11
Edge-aligned Mode (Up-counting)
ARR = 6, RCR = 0
clock
6 6 6 6
5 Counter
5 Counter
5 Counter
5
4 overflow 4 overflow 4 overflow 4
3 3 3 3
counter 2 2 2 2
1 1 1 1
0 0 0 0
Counter overflow
Update event (UEV)
Period = (1 + ARR) * Clock Period
= 7 * Clock Period
RCR=Repetition Counter 12
Edge-aligned Mode (down-counting)
ARR = 6, RCR = 0
Clock
6 6 6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 Counter 2 Counter 2 Counter 2
1 underflow 1 underflow 1 underflow 1
0 0 0 0
Counter underflow
Update event (UEV)
Period = (1 + ARR) * Clock Period
= 7 * Clock Period
13
Center-aligned Mode
ARR = 6, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
Counter Counter Counter Counter
overflow underflow overflow underflow
Update event (UEV)
Period = 2 * ARR * Clock Period
= 12 * Clock Period
14
PWM Mode 1 Mode 1
Timer Output =
High if counter < CCR
Low if counter ≥ CCR
(Low-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
3
=
7
15
PWM Mode 2 Mode 2
Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
4
=
7
16
PWM Mode 2 Mode 2
Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
2
=
7
17
PWM Mode 2 Mode 2
Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
1
=
2
18
PWM Mode 2 Mode 2
Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
CCR = 1 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
5
=
6
19
Up-Counting: Left Edge-aligned
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
CCR = 6 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
CCR = 3
OC1REF
CCR = 6
OC2REF
Left-aligned
All rising edges occur at the same time! PWM Period
20
PWM Mode 2: Right Edge-aligned
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OC1REF CCR = 3
OC2REF CCR = 5
Right-aligned
All falling edges occur at the same time!
PWM Period
21
PWM Mode 2: Center Aligned Low if counter < CCR
Timer Output =
High if counter ≥ CCR
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
CCR = 1 0 0 0
CCR = 3
OC1REF
CCR = 1
OC2REF
Center-aligned
PWM signals are center aligned!
PWM Period
22
The devil is in the detail
• Timer output control
• Enable Timer Output
– MOE: Main output
enable
– OSSI: Off-state selection
for Idle mode
– OSSR: Off-state selection
for Run mode
– CCxE: Enable of
capture/compare output
for channel x
– CCxNE: Enable of
capture/compare
complementary output
for channel x
23
Input Capture
• Monitor both rising and falling edge
24
Input Capture
• Monitor only rising edges or only falling edge
25
Input Capture
26
Input Filtering
27
Input Capture Diagram
28
Ultrasonic Distance Sensor
*+,&- ./"0 ."1(×30((- +4 3+,&-
!"#$%&'( =
2
6789: ;<=> ;=?@ AB ×CDEF ×GHD?/B
=
J
*+,&- ./"0 ."1( µ#
=
58
29
Ultrasonic Distance Sensor
The echo pulse width corresponds to
round-trip time.
-./#( 0"1$ℎ (3#)
!"#$%&'( ('*) =
58
or
-./#( 0"1$ℎ (3#)
!"#$%&'( ("&'ℎ) =
148
If pulse width is 38ms,
no obstacle is detected.
30
Ultrasonic Distance Sensor
31
Later
Repetition Counter Register (PCR)
33
Repetition Counter Register (PCR)
34
Repetition Counter Register (RCR)
35
Repetition Counter Register (PCR)
36
Repetition Counter Register (PCR)
37
