## Creating the MW Library ##
#exec rm -rf db/dtmf_mw
#exec mkdir -p rpts/sanity_checks
set DESIGN or1200_top
## Creating Library
create_mw_lib -technology /tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf
\
-bus_naming_style {[%d]} \
-mw_reference_library { \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp \
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR/ \
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM} -open mwdb/$DESIGN.mw
## Attaching the TLU+ Files ##
set_tlu_plus_files -max_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmax.tluplus \
-min_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmin.tluplus \
-tech2itf_map /tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_tf_itf_tluplus.map
## Importing the Verilog Netlist ##
import_designs -format verilog -cel $DESIGN -top $DESIGN
/home/guepd2211ce18/srkrao/min_soc_24/inputs/minsoc.v
## Setting the Current Design ##
set current_design $DESIGN
## Linking the Physical Libraries ##
link_physical_library
## Linking the Timing Libraries ##
link
## Reading the SDC ##
read_sdc /home/guepd2211ce18/srkrao/min_soc_24/inputs/minsoc.sdc
#create path groups in your design
source scripts/create_path_groups.tcl
## PG - Global Net Connection ## need to read once floorplan is done
#source scripts/derive_pg_connection.tcl
## Saving the Design ##
save_mw_cel -as ${DESIGN}_import_design
save_mw_cel
======power_plan
# Making logical connection
derive_pg_connection -power_net {VDD} -ground_net {VSS} -power_pin {VDD} -ground_pin {VSS}
-reconnect
derive_pg_connection -power_net {VDD} -ground_net {VSS} -tie
# Creating power straps
create_power_straps -direction horizontal -start_at 5 -num_placement_strap 120 -increment_x_or_y 8
-nets {VDD VSS} -layer M7 -width 0.5
create_power_straps -direction vertical -start_at 5 -num_placement_strap 120 -increment_x_or_y 8
-nets {VDD VSS} -layer M8 -width 0.5
# Creating Standard cells PG pins
preroute_standard_cells -route_pins_on_layer M1 -fill_empty_rows -do_not_route_over_macros
-route_type {P/G Std. Cell Pin Conn}
# Verify PG Nets
verify_pg_nets -std_cell_pin_connection ignore -macro_pin_connection ignore -pad_pin_connection
ignore -nets {VDD VSS} -error_cell pg_net
# Save the mw cel
save_mw_cel -as ${design}_power_routed
save_mw_cel
=======place_IO_ports=====
set_fp_pin_constraints -no_stacking all -pin_spacing 1 -pin_preroute_spacing 3 -hard_constraints
{spacing location layer} -allowed_layers [get_layers { M3 M4}] -corner_keepout_percent_side 15.0
-keep_buses_together on -bus_ordering lsb_to_msb -use_physical_constraints on -block_level
place_fp_pins -block_level
====cut_row_near_macro
proc cut_rows_near_macro { value } {
set my_macros [all_macro_cells]
foreach_in_collection a $my_macros {
set macro_llx [lindex [get_attribute [get_cells $a] bbox_ll] 0]
set macro_lly [lindex [get_attribute [get_cells $a] bbox_ll] 1]
set macro_urx [lindex [get_attribute [get_cells $a] bbox_ur] 0]
set macro_ury [lindex [get_attribute [get_cells $a] bbox_ur] 1]
set macro_llx_new [expr $macro_llx - $value]
set macro_urx_new [expr $macro_urx + $value]
puts "cut_row -within \"$macro_llx_new $macro_lly $macro_urx_new $macro_ury\""
cut_row -within [list $macro_llx_new $macro_lly $macro_urx_new $macro_ury]
cut_rows_near_macro 0.5
====drive_pg_connection
derive_pg_connection -power_net VDD -power_pin VDD -ground_net VSS -ground_pin VSS
derive_pg_connection -power_net VDD -ground_net VSS -tie
