Digital Logic Families

&

Metrics for Logic Gate Comparison

 Digital Logic Families

• Gates.
– simply electronic circuits composed of resistors,
diodes and transistors.

– The style in which transistors are connected

characterises each logic family or library and gives
it its unique name.
 Digital Logic Families

· Diode-Resistor Logic (DRL) · Integrated Injection Logic (I2L)

· Diode-Transistor Logic (DTL) · standard I2L
· Schottky I2L
· Resistor-Transistor Logic (RTL)
· Schottky Transistor I2L

· Transistor-Transistor (TTL) · NMOS

· standard TTL
· Schottky-Clamped TTL · CMOS Logic
· Low-Power Schottky-Clamped · standard CMOS
TTL · 4000 Series CMOS Logic Family
· Advanced Schottky-Clamped TTL · 4000B and 74C Series
· 74HC/HCT Series
· Emitter-Coupled Logic (ECL) · 74AC/ACT Series
· ECL 10K Series · BiCMOS
· ECL 100K Series

• How do you compare these different logic families ?

Several metrics must be defined to allow comparison of different families.
 Metrics for Logic Gate Comparison

1. Logic Level

2. Noise Margin

3. Fan out

4. Propagation Delay

5. Power Dissipation
METRIC 1: Logic Level
 Logic Levels

• The inputs take two values (0 or 1) and for each value, a certain range of signal amplitude exists.
• The output takes specific values (0 or 1)

Vout
VOH
Vin Vout

Vin Vout
1 VIH 1
VOH
VOL
VIL
0 VOL
0 VIL VIH Vin
 Logic Levels
Vout
VOH
• The
Vin inputs take two values
Vout (0 or 1) and for
each
V in
value,
V a certain
Vout
range of signal
in

amplitude exists.
1 V
• The output takes specific values
1 1 V
(0 or 1)
OH
V IH V IH OL

VIL VIH Vin

0 VIL 0 VIL
0 VOL

• VOH : Minimum Output Voltage considered to be High.

• VOL: Maximum Input Voltage considered to be Low.

• VIH: Minimum Input Voltage considered to be High.

• VIL: Maximum Input Voltage considered to be low.

 Logic Level

• The voltage transfer curves for the inverting and non-inverting Digital Circuit.

Vin Vout Vin Vout

Vout Vout
VOH VOH

VOL VOL
VIL VIH Vin VIL VIH Vin

Inverting Circuit Non-Inverting Circuit

 Logic Swing and Transition Width

Vout
• Logic Swing – Magnitude of voltage
difference between the output high and low VOH
voltage levels.
– VLS = VOH – VOL
LS

• Transition Width – Amount of voltage change VOL

that is required to cause a change in the
output voltage. VIL VIH Vin
– VTW = VIH – VIL TW
 The Ideal Digital Circuit Element

• Operates from a single power source (Vcc)

• The two binary levels (0 and 1) are at 0 V and Vcc.
• Negligible current drawn from supply source
• Output impedance is low => large fan-out is possible.
• Transition between logic states occurs suddenly at Vin = Vcc/2

Vout
VCC VCC

Vin Vout

Vin
VCC
VCC
2
 The Ideal Digital Circuit Element
• There is negligible delay between input transition and
resulting output transition.

Vin

Vin

t
Vout

Vout
t
METRIC 2: Noise Margin
 Noise
• Noise :- Un-wanted variation of voltage or current.

• If the magnitude of the noise is large enough, it can cause logic errors.

• If the noise amplitude at the input of a logic gate is smaller than its “Noise Margin”,
the noise signal will be sharply reduced between the input and the output.

• In digital systems, noise does not accumulate from one logic gate to the next.

At this point, the output

is no longer 0 from the
view of the next input

VIL
VOL
 Noise Margins
Vout
VOH
• “Noise Margin” is the amplitude below
which the noise signal will not cause logic
errors.

– NML VOL
Vin
(Low Noise Margin)
VOL VIL VIH VOH
• NML = VIL - VOL
NML NMH

– NMH VOH 5.0 V

(High Noise Margin)

• NMH = VOH - VIH HIGH NMH

LS
1.5 V VIH

TW
0.7 V VIL
LOW NML VOL 0.1 V

Input Output
Typical Inverting Gate Characteristics

Vout

VOH In this area, the digital

circuit behaves like an
analog circuit

VOL
Vin
VOL VIL VIH VOH

NML NMH
Typical Inverting Gate Characteristics

• NOTE:
– In the area between VIL and VIH, the digital inverter
behaves like an analog device. In that range, the output
voltage is a linear amplification of the input voltage.
– The amount of time the circuit spends in this range must
be minimized as much as possible.
 How to determine noise margins?
• Compare input and output voltage ranges of gates in same family.

VCC (5.0) VCC (5.0)

H H
VOH (2.4)
High Noise
margin
VIH (2.0)

VIL (0.8)
Low Noise
margin
VOL (0.4)
• L L
GND (0) GND (0)

Output Voltage Input Voltage

range range

• output voltage range of a driving gate on LHS input voltage range of the driven
gate on RHS
– Any voltage between VOH and VCC is considered H.
– any voltage between 0 and VOL is considered L.
 How to determine noise margins?

• Similarly
– Any voltage between VIH and VCC is considered H
• Any voltage between 0 and VIL is considered L
• The voltage difference VOH - VIH called high-level noise margin

– Any noise voltage smaller than VOH - VIH will be tolerated and will not
change the output value of the driven gate.
• For the same reason, the voltage difference VIL - VOL is called the
low-level noise margin.
 How to determine noise margins?

• In the example of transistor-transistor

logic (TTL): VCC (5.0) VCC (5.0)
H H
– VOH = 2.4 V
VOH (2.4)
High Noise
– VIH = 2.0 V margin
VIH (2.0)
– VIL = 0.8 V
– VOL = 0.4 V Low Noise
VIL (0.8)

margin
VOL (0.4)
• Thus both high and low level noise margins L L
are 0.4 V. GND (0) GND (0)

Output Voltage Input Voltage

• Thus any noise smaller than 0.4 V will not range range
disturb gate operation.
METRIC 3: Fan-out
 Fan-out

• Fan-out – Maximum number of inputs that can be connected to a

particular output.

• The fan-out really depends on the amount of electric current a

gate can source or sink while driving other gates
 Fan-out

• When the gate output is H I IH

• Gate behaves as a current

source since IOH flows out I IH

of the driver gate and into I OH

the set of driven gates.

I IH

• The current IOH equals the

sum of all input currents
indicated by IIH, flowing to other gates

into the driven gates.

 Fan-out

• When the gate output is L

IIL

• Gate behaves as a current

sink since IOL flows into the IIL

gate and out of the driven IOL

gates.
IIL

• The current IOL is again

equal to the sum of all input to other gates

currents IIL, flowing out of

all the driven gates.
 Fan-out
• Since all gates in a logic family are constructed in such
a way that each gate requires the same IIH and the
same IIL,
– can compute fan-out in the following way:

I I 
Fan _ out  min  OH , OL 
 I IH I IL 
 min( Logic H output fanout, Logic L output fanout)
 Fan-out
Example

• Input and output current for the transistor-transistor logic

(TTL) family are the following:

IOH = 400 A
IOL = 16 A
IIH = 40 A
IIL = 1.6 A

Therefore the fan-out is ?

 Fan-out

• This means that each gate can drive 10 other gates in the same family
– without getting out of its guaranteed range of operation.

• In cases where more than 10 gates are connected to the output of a

single gate of this family, the output voltage levels will degrade and
the gate will slow down.

• Modern MOS logic families have a fan-out of about 50,

– since each gate must source or sink a current only during the
transition from H to L or L to H.
 Current Directions

• Both the input and output currents can flow either into or
out of the gate – both in the low and high states.

• For fan-out to be possible, the current directions must be

complementary.
– Fan-out can only be possible if the current flows out of
one terminal and into the other.
Metric 4 Propagation Delay
 Propagation Delay

Propagation delay defined as: Rise Fall

time time

Average time needed for an

90%

input change to propagate to Input

the output
50%

10%

Typically nanoseconds.

90%

The propagation delay can be

obtained from gate input and Output
50%

output waveforms.
10%

tPHL tPLH
 Propagation Delay
• Rise Time (tr):
– Amount of time it takes the signal to change from 10%
maximum signal value to 90% maximum signal value.

• Fall Time (tf):

– Amount of time it takes the signal to change from 90%
maximum signal value down to 10% maximum signal value.
Vout

90% VOH

VLS

10%
VOL
t
tr tf
 Propagation Delay
• Since H  L and L  H transitions are not
delayed equally, can define
– tPHL H  L propagation delay Vin
– tPLH L  H propagation delay
50%
t
• tPHL is defined as
Vout tPHL tPLH

– time necessary for output signal to reach

50% of its nominal value on H  L 50%
transition after input signal reached 50% t
of its nominal value.

• tPLH is defined similarly.

Propagation delay tP defined as average value of tPHL and tPHL.

t PHL  t PLH
tP 
2
 Propagation Delay
2-input NAND in the TTL family
tPHL = 7 nsec
tPLH = 11 nsec  tp = (7+11/2) = 9 nsec

2-input NAND in the CMOS family tp = 1 nsec

• As manufacturers cannot guarantee the same nominal value on every gate they
fabricate
– Usually give the maximum delay values (not that interested in the minimum
delay)
• no gate will exceed this maximal value.

• 2-input NAND in the TTL family, the maximal propagation delays

tPHL = 22 nsec
tPLH = 15 nsec  tp = (22+15/2) = 18.5 nsec
Metric 5: Power Dissipation
 Metric 5: Power Dissipation

• Each gate is connected to a power supply VCC

– Draws a certain amount of current during its operation.

• Since each gate can be in a High state, Transition or Low state.

– can distinguish 3 different currents drawn from power supply
during transitions (dynamic power dissipation) and during idle
states High or Lwo (static power dissipation).

ICCT
ICCH
ICCL
 TTL
• In some older logic families, such as TTL, the transition current ICCT is negligible
– in comparison to ICCH and ICCL.

• Assuming that gate spends an approximately equal amount of time in the high and the
low states and approximately no time in the transition state

I  I CCL 
 Average Current   CCH 
 2 

• Thus the average power dissipation (product of average current and power supply
voltage)

I  I CCL 
 Paverage  VCC   CCH 
 2 

• Power dissipation is measured in mW

– for the TTL family 10mW
 CMOS
• In more modern technologies such as the CMOS family
– the steady-state currents ICCH and ICCL are negligible in comparison with ICCT.

Paverage  VCC  I CCT

• Since ICCT is relatively small the typical power dissipation of CMOS gates is small.

 But the power dissipation increases with the frequency with which the gate
output is changing
 Power Dissipation
• Power Dissipation is an important metric for two reasons.

1. Amount of current and power available in a battery is nearly constant.

• power dissipation of a circuit or system defines battery life.
• The greater the power dissipation, the shorter the battery life.

2. Power dissipation is proportional to the heat generated by the chip or system.

• Excessive heat dissipation may increase operating temperature and cause
gate circuitry to drift out of its normal operating range
• will cause gates to generate improper output values.

• Thus power dissipation of any gate implementation must be kept as low as

possible
 Power-Delay Product

• A measure of the quality of the digital circuit is the product

of its power dissipation and the average delay.

• PD = PDISS(avg) * tP(avg)
 Important Factors

• Three important factors in the design of any digital circuit:

– Physical Size – Determines manufacturing cost.

– Power Consumption – Determines operating cost.

– Delay – Determines overall performance.

• All three need to be as small as possible. However, practically, it

is impossible to minimize all three. Therefore, digital circuit
design becomes a trade off between the different factors.
 Summary

• Need to have metrics to allow Digital Designers compare

different designs.

• So either the cost effective or fastest design can be

implemented for each application.