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ECE 251 - Lecture 02 PDF

The document discusses junction field effect transistors (JFETs). It describes the basic structure and operation of JFETs, including how applying a reverse voltage to the gate varies the width of the conduction channel. Key terms like shorted-gate drain current, pinch-off voltage, and gate-source cut-off voltage are defined. The characteristics, parameters, biasing, and example problems of JFETs are also covered.

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100% found this document useful (2 votes)
654 views7 pages

ECE 251 - Lecture 02 PDF

The document discusses junction field effect transistors (JFETs). It describes the basic structure and operation of JFETs, including how applying a reverse voltage to the gate varies the width of the conduction channel. Key terms like shorted-gate drain current, pinch-off voltage, and gate-source cut-off voltage are defined. The characteristics, parameters, biasing, and example problems of JFETs are also covered.

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Field Effect Transistor

Types of Field Effect Transistors

There are two basic types of field effect transistors:


(i) Junction field effect transistor (JFET)
(ii) Metal oxide semiconductor field effect transistor (MOSFET)

Junction Field Effect Transistor (JFET)

A junction field effect transistor is a three terminal semiconductor device in


which current conduction is by one type of carrier i.e., electrons or holes.

Symbol of JFET

Working Principle:

(i) When a voltage VDS is applied between drain and source terminals and voltage
on the gate is zero, the two pn junctions at the sides of the bar establish depletion
layers. The electrons will flow from source to drain through a channel between the
depletion layers. The size of these layers determines the width of the channel and
hence the current conduction through the bar.

(ii) When a reverse voltage VGS is applied between the gate and source, the width
of the depletion layers is increased. This reduces the width of conducting channel,
thereby increasing the resistance of n-type bar. Consequently, the current from
source to drain is decreased. On the other hand, if the reverse voltage on the gate is
decreased, the width of the depletion layers also decreases. This increases the
width of the conducting channel and hence source to drain current.

Characteristics of JFET

Drain Characteristics

Transfer Characteristics
Important Terms of JFET

1. Shorted-gate drain current (IDSS): It is the drain current with source short-
circuited to gate (i.e. VGS = 0) and drain voltage (VDS) equal to pinch off voltage. It
is sometimes called zero-bias current.
2. Pinch off Voltage (VP): It is the minimum drain-source voltage at which the
drain current essentially becomes constant.
3. Gate-source cut off voltage VGS (off): It is the gate-source voltage where the
channel is completely cut off and the drain current becomes zero.

Expression for Drain Current (ID)

Where, ID = drain current at given VGS


IDSS = shorted – gate drain current
VGS = gate–source voltage
VGS (off) = gate–source cut off voltage

Parameters of JFET

(i) a.c. drain resistance (rd): It is the ratio of change in drain-source voltage
(∆VDS) to the change in drain current (∆ID) at constant gate-source voltage i.e.
∆VDS
a.c. drain resistance, rd = at constant VGS
∆ID

(ii) Transconductance ( gfs ): It is the ratio of change in drain current (∆ID) to the
change in gate-source voltage (∆VGS) at constant drain-source voltage i.e.
∆ID
Transconductance, gfs = at constant VDS
∆VGS

(iii) Amplification factor ( μ ). It is the ratio of change in drain-source voltage


(∆VDS) to the change in gate-source voltage (∆VGS) at constant drain current i.e.
∆VDS
Amplification factor, μ = at constant ID
∆VGS
JFET Biasing

Self-Bias for JFET

Problem 01

Find VDS and VGS in the following network, given that ID = 5 mA.
Solution:

Problem 02

In a self-bias n-channel JFET, the operating point is to be set at ID = 1.5 mA and


VDS =10 V. The JFET parameters are IDSS= 5 mA and VGS (off) = − 2 V. Find the
values of RS and RD. Given that VDD = 20 V.
Solution:

JFET with Voltage-Divider Bias


Problem 02

Determine ID and VGS for the JFET with voltage-divider bias in the following
network, given that VD = 7V.

Solution:

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