EXPERIMENT NUMBER 1

TITLE: TO STUDY TRANSFER CHARACTERISTICS OF CMOS INVERTER

SOFTWARE TOOLS: Tanner Spice Software version 13

THEORY

The configuration which consists of an enhancement–type nMOS and an enhancement type

pMOS transistor, operating in complementary mode is called complementary MOS(CMOS).
The circuit topology is complementary push-pull in the sense that for high input, the nMOS
transistor drives (pulls down) the output node while the pMOS transistor acts as the load, and
for low input the pMOS transistor drives (pulls up) the output node while the nMOS
transistor acts as the load. Consequently, both devices contribute equally to the circuit
operation characteristics.

CIRCUIT OPERATION

Input voltage is connected to the gate terminals of both the nMOS and the pMOS transistors.
Thus, both transistors are driven directly by the input signal, vin. The substrate of the nMOS
transistor is connected to the ground, while the substrate of the pMOS transistor is connected
to the power supply voltage, VDD, in order to reverse-bias the source and drain junctions.
Since VSB = 0 for both devices, there will be no substrate-bias effect for either device. It can
be seen from circuit diagram that
VGS,n = Vin
VDS,n = Vout
and also,
VGS,p = -(VDD-Vin)
VDS,p = -(VDD-Vout)
When input voltage is smaller than the nMOS threshold voltage, i.e., when Vin<VTO,n, the
nMOS transistor is cut-off. At the same time, the pMOS transistor is on, operating in the
linear region. Since the drain currents of both transistors are approximately equal to
zero(except for small leakage current), i.e.,
ID,n = ID,p = 0
The drain-to-source voltage of the pMOS transistor is equal to zero, and the output voltage
VOH is equal to the power supply voltage.
Vout = VOH = VDD
On the other hand, when the input voltage exceeds (VDD + VTO,p), the pMOS transistor is
turned off. In this case, the nMOS transistor is operating in the linear region, but its drain-to-
source voltage is equal to zero. Consequently, the output voltage of the circuit is
Vout = VOL = 0
Next, we examine the operating modes of the nMOS and the pMOS transistors as functions
of the input and output voltages. The nMOS transistor operates in saturation if Vin > VTO,n and
if the following condition is satisfied
VDS,n >= VGS,n – VTO,n  Vout >= Vin – VTO,n
The pMOS transistor operates in saturation if Vin < (VDD + VTO,p), and if :
VDS,p <= VGS,p – VTO,p  Vout <= Vin – VTO,p
The table below lists these regions and the corresponding critical input and output voltage
levels:
 vin vout nMOS pMOS
<VTO,n VOH Cut-off Linear
VIL High(VOH) saturation linear
Vth Vth saturation saturation
VIH Low(VOL) linear saturation
>(VDD + VOL linear Cut-off
VTO,p)

Note that the critical voltages Vin and Vout corresponds to (dVout/dVin) = -1 and at inverter
threshold voltage, Vth, Vin = Vout.
In a simplistic analogy, the nMOS and the pMOS transistors can be seen as nearly ideal
switches-controlled by the input voltage-that connect the output node to the power supply
voltage or to the ground potential, depending on the input voltage level.
The most significant feature of this circuit is that the current drawn from the power supply in
steady-state operating points is nearly equal to zero. The only current that flows is the very
small leakage current of the reversed-biased source and drain junctions.
We already know that the drain current ID,n of the nMOS transistor ID,p of the pMOS transistor
is a function of the voltages VGS and VDS. Hence, the nMOS and pMOS drain current is also a
function of the inverter input and output voltages Vin and Vout,
ID,n = f(Vin,Vout)
ID,p = f(Vin,Vout)
In a CMOS inverter operating in steady-state, the drain current of the nMOS transistor is
always equal to the drain current of the pMOS transistor, according to KCL
ID,n=ID,p
PROCEDURE:
Procedure same as experiment number 1.

SCHEMATIC DIAGRAM

NETLIST

* SPICE export by: SEDIT 13.00

* Design: trchofcmosinv
* Cell: trchofcmosinv
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude. model: no
* Exclude. end: no
* Expand paths: yes
* Wrap lines: no
* Root path: D:\10&11ece3\trchofcmosinv
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
m1 vout N_1 Gnd Gnd NH W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
m2 vout N_1 Vdd Vdd PH W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
vin N_1 Gnd DC 5
vdd vdd gnd 5
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.dc vin 0 5 .1
.print vout i(m1)
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OBSERVATION

TRANSFER ANALYSIS
vin<V> v(vout)<V> i1(m1)<A>
0.0000e+000 4.9999e+000 4.6890e-008
1.0000e-001 4.9988e+000 9.4548e-007
2.0000e-001 4.9886e+000 9.1123e-006
3.0000e-001 4.9529e+000 3.7360e-005
4.0000e-001 4.8964e+000 8.1306e-005
5.0000e-001 4.8357e+000 1.2752e-004
6.0000e-001 4.7753e+000 1.7228e-004
7.0000e-001 4.7149e+000 2.1572e-004
8.0000e-001 4.6540e+000 2.5829e-004
9.0000e-001 4.5917e+000 3.0027e-004
1.0000e+000 4.5276e+000 3.4185e-004
1.1000e+000 4.4612e+000 3.8310e-004
1.2000e+000 4.3919e+000 4.2409e-004
1.3000e+000 4.3190e+000 4.6484e-004
1.4000e+000 4.2417e+000 5.0535e-004
1.5000e+000 4.1586e+000 5.4561e-004
1.6000e+000 4.0683e+000 5.8559e-004
1.7000e+000 3.9683e+000 6.2524e-004
1.8000e+000 3.8546e+000 6.6445e-004
1.9000e+000 3.7200e+000 7.0302e-004
2.0000e+000 3.5468e+000 7.4047e-004
2.1000e+000 3.2759e+000 7.7513e-004
2.2000e+000 2.7792e+000 8.0306e-004
2.3000e+000 2.0091e+000 8.2031e-004
2.4000e+000 1.2446e+000 8.2237e-004
2.5000e+000 8.8365e-001 8.0440e-004
2.6000e+000 7.4149e-001 7.7763e-004
2.7000e+000 6.5572e-001 7.4858e-004
2.8000e+000 5.9106e-001 7.1855e-004
2.9000e+000 5.3779e-001 6.8793e-004
3.0000e+000 4.9188e-001 6.5684e-004
3.1000e+000 4.5120e-001 6.2536e-004
3.2000e+000 4.1442e-001 5.9350e-004
3.3000e+000 3.8065e-001 5.6127e-004
3.4000e+000 3.4925e-001 5.2866e-004
3.5000e+000 3.1972e-001 4.9563e-004
3.6000e+000 2.9169e-001 4.6214e-004
3.7000e+000 2.6484e-001 4.2810e-004
3.8000e+000 2.3890e-001 3.9341e-004
3.9000e+000 2.1360e-001 3.5792e-004
4.0000e+000 1.8869e-001 3.2138e-004
4.1000e+000 1.6388e-001 2.8348e-004
4.2000e+000 1.3877e-001 2.4365e-004
4.3000e+000 1.1285e-001 2.0105e-004
4.4000e+000 8.5381e-002 1.5434e-004
4.5000e+000 5.5834e-002 1.0243e-004
4.6000e+000 2.6586e-002 4.9464e-005
4.7000e+000 7.0250e-003 1.3197e-005
4.8000e+000 9.6714e-004 1.8244e-006
4.9000e+000 8.8569e-005 1.6741e-007
5.0000e+000 6.8441e-006 1.2958e-008

OUTPUT WAVEFORM

Now we increase the ratio kn/k p

NETLIST
m1 vout N_1 Gnd Gnd NH W=.9u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
m2 vout N_1 Vdd Vdd PH W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
vin N_1 Gnd DC 5
vdd vdd gnd 5
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.dc vin 0 5 .1
.print vout i(m1)
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OBSERVATION

TRANSFER ANALYSIS
vin<V> v(vout)<V> i1(m1)<A>
0.0000e+000 4.9999e+000 7.6353e-008
1.0000e-001 4.9980e+000 1.5872e-006
2.0000e-001 4.9799e+000 1.6051e-005
3.0000e-001 4.9133e+000 6.8335e-005
4.0000e-001 4.8031e+000 1.5232e-004
5.0000e-001 4.6806e+000 2.4175e-004
6.0000e-001 4.5556e+000 3.2840e-004
7.0000e-001 4.4276e+000 4.1222e-004
8.0000e-001 4.2941e+000 4.9399e-004
9.0000e-001 4.1527e+000 5.7420e-004
1.0000e+000 4.0001e+000 6.5307e-004
1.1000e+000 3.8323e+000 7.3058e-004
1.2000e+000 3.6424e+000 8.0651e-004
1.3000e+000 3.4176e+000 8.8025e-004
1.4000e+000 3.1193e+000 9.4978e-004
1.5000e+000 2.6047e+000 1.0072e-003
1.6000e+000 1.7589e+000 1.0428e-003
1.7000e+000 9.3008e-001 1.0527e-003
1.8000e+000 6.1285e-001 1.0347e-003
1.9000e+000 5.0633e-001 1.0076e-003
2.0000e+000 4.4613e-001 9.7845e-004
2.1000e+000 4.0307e-001 9.4853e-004
2.2000e+000 3.6905e-001 9.1814e-004
2.3000e+000 3.4073e-001 8.8741e-004
2.4000e+000 3.1632e-001 8.5640e-004
2.5000e+000 2.9476e-001 8.2517e-004
2.6000e+000 2.7536e-001 7.9372e-004
2.7000e+000 2.5763e-001 7.6207e-004
2.8000e+000 2.4124e-001 7.3023e-004
2.9000e+000 2.2592e-001 6.9818e-004
3.0000e+000 2.1149e-001 6.6594e-004
3.1000e+000 1.9777e-001 6.3347e-004
3.2000e+000 1.8465e-001 6.0076e-004
3.3000e+000 1.7202e-001 5.6778e-004
3.4000e+000 1.5980e-001 5.3449e-004
3.5000e+000 1.4791e-001 5.0086e-004
3.6000e+000 1.3628e-001 4.6681e-004
3.7000e+000 1.2485e-001 4.3225e-004
3.8000e+000 1.1353e-001 3.9708e-004
3.9000e+000 1.0227e-001 3.6112e-004
4.0000e+000 9.0975e-002 3.2415e-004
4.1000e+000 7.9524e-002 2.8581e-004
4.2000e+000 6.7757e-002 2.4557e-004
4.3000e+000 5.5429e-002 2.0255e-004
4.4000e+000 4.2181e-002 1.5541e-004
4.5000e+000 2.7738e-002 1.0305e-004
4.6000e+000 1.3265e-002 4.9674e-005
4.7000e+000 3.5096e-003 1.3219e-005
4.8000e+000 4.8307e-004 1.8249e-006
4.9000e+000 4.4234e-005 1.6742e-007
5.0000e+000 3.4180e-006 1.2958e-008

OUTPUT WAVEFORM

COMMENT

As the ratio kn/k p increase the steepness of the slope of VTC of CMOS inverter decrease and
thus the noise margin decreases which is not desirable.

CONCLUSION

We see that the VTC of the CMOS inverter that is obtained practically is same as that we
draw manually by analyzing circuit behavior and considering several mathematical
expressions. Thus, the experiment has been successful.

EXPERIMENT NUMBER 2A
TITLE: TO STUDY THE TRANSIENT ANALYSIS OF CMOS INVERTER

SOFTWARE TOOLS: Tanner Spice Software version 13

THEORY

The configuration which consists of an enhancement–type nMOS and an enhancement type

pMOS transistor, operating in complementary mode is called complementary MOS(CMOS).
The circuit topology is complementary push-pull in the sense that for high input, the nMOS
transistor drives (pulls down) the output node while the pMOS transistor acts as the load, and
for low input the pMOS transistor drives (pulls up) the output node while the nMOS
transistor acts as the load. Consequently, both devices contribute equally to the circuit
operation characteristics.

CIRCUIT OPERATION

Input voltage is connected to the gate terminals of both the nMOS and the pMOS transistors.
Thus, both transistors are driven directly by the input signal, vin. The substrate of the nMOS
transistor is connected to the ground, while the substrate of the pMOS transistor is connected
to the power supply voltage, VDD, in order to reverse-bias the source and drain junctions.
Since VSB = 0 for both devices, there will be no substrate-bias effect for either device. It can
be seen from circuit diagram that
VGS,n = Vin
VDS,n = Vout
and also,
VGS,p = -(VDD-Vin)
VDS,p = -(VDD-Vout)
When input voltage is smaller than the nMOS threshold voltage, i.e., when Vin<VTO,n, the
nMOS transistor is cut-off. At the same time, the pMOS transistor is on, operating in the
linear region. Since the drain currents of both transistors are approximately equal to zero
(except for small leakage current), i.e.,
ID,n = ID,p = 0
The drain-to-source voltage of the pMOS transistor is equal to zero, and the output voltage
VOH is equal to the power supply voltage.
Vout = VOH = VDD
On the other hand, when the input voltage exceeds (VDD + VTO,p), the pMOS transistor is
turned off. In this case, the nMOS transistor is operating in the linear region, but its drain-to-
source voltage is equal to zero. Consequently, the output voltage of the circuit is
Vout = VOL = 0

PROCEDURE:
Procedure same as experiment number 1.

SCHEMATIC DIAGRAM
NETLIST
MNMOS_1 Vout N_1 Gnd Gnd NH W=0.45u L=0.15u AS=0.3375p PS=2.4u AD=0.3375p
PD=2.4u
MPMOS_1 Vout N_1 Vdd Vdd PH W=0.90u L=0.15u AS=0.675p PS=3.3u AD=0.675p
PD=3.3u
VVoltageSource_1 N_1 Gnd BIT ({0101}PW=50n on=1 off=0 rt=0.1n ft=0.1n delay=0
lt=50n ht=50n)
Vdd Vdd GND 1
.tran .1n 200n
.print V(N_1) V(vout)
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM

CONCLUSION
The output waveform as obtained practically coincides with the waveform drawn manually
based on analysis of the circuit and mathematical expressions i.e. for a low input output is
high and for a high input output is low. Thus, the experiment has been successful.

EXPERIMENT NUMBER 2B
Spice Simulation of NAND, NOR Gates.
 .
Objectives:
1) To design a NAND gate circuit using S-edit window
2)To design an NOR gate circuit using S-edit window.
3)To simulate the circuit & obtain the output response of the circuit using
TSPICE simulator.
PART (1)
TITLE TO DESIGN NAND CIRCUIT USING STATIC CMOS

OBJECTIVE
1. Simulation of basic gates (NAND, NOR) and their complements.

SOFTWARE TOOLS: Tanner Spice Software version 13

THEORY

STATIC CMOS DESIGN

The most widely used logic style is static complementary CMOS. The static CMOS style is
really an extension of the static CMOS inverter to multiple inputs. To review, the primary
advantage of the CMOS structure is robustness (i.e., low sensitivity to noise), good
performance, and low power consumption with no static power dissipation. Most of those
properties are carried over to large fan-in logic gates implemented using a similar circuit
topology.
The complementary CMOS circuit style falls under a broad class of logic circuits called
static circuits in which at every point in time, each gate output is connected to either V DD
or VSS via a low-resistance path. Also, the outputs of the gates assume at all times the value
of the Boolean function implemented by the circuit (ignoring, the transient effects during
switching periods).
COMPLEMENTARY CMOS
A static CMOS gate is a combination of two networks-the Pull-up network (PUN) and the
Pull-down network (PDN), as shown in the figure below:

The figure shows a generic N-input logic gate where all inputs are distributed to both the
pull-up and pull-down networks. The function of the PUN is to provide a connection between
the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs).
Similarly, the function of the PDN is to connect the output to VSS when the output of the logic
gate is meant to be 0. The PUN and PDN networks are constructed in a mutually exclusive
fashion such that one and only one of the networks is conducting in steady state. In this way,
once the transients have settled, a path always exists between VDD and the output F for a high
output (“one”), or between VSS and F for a low output (“zero”). This is equivalent to stating
that the output node is always a low-impedance node in steady state.
In constructing the PDN and PUN networks, THE designer should keep the
following observations in mind:
 A transistor can be thought of as a switch controlled by its gate signal. An NMOS
switch is on when the controlling signal is high and is off when the controlling signal
is low. A PMOS transistor is on when the controlling signal is low and is off when the
controlling signal is high.
 The PDN is constructed using NMOS devices, while PMOS transistors are used in the
PUN The primary reason for this choice is that NMOS transistors produce “strong
zeros”, and PMOS devices generate “strong ones”.

 A set of rules can be derived to construct logic functions. NMOS devices connected in
series correspond to an AND function. With all the inputs high, the series
combination conducts and the value at one end of the chain is transferred to the other
end. Similarly, NMOS transistors connected in parallel represent an OR function. A
conducting path exists between the output and input terminal if at least one of the
inputs is high. Using similar arguments, construction rules for PMOS networks can be
formulated. A series connection of PMOS conducts if both inputs are low,
representing a NOR function ( A.B  A  B ), while PMOS transistors in parallel
implement a NAND ( A  B  A.B ).
 Using De Morgan’s theorems ( A.B  A  B and A  B  A.B ), it can be shown that
the pull-up and pull-down networks of a complementary CMOS structure are dual
networks. This means that a parallel connection of transistors in the pull-up network
corresponds to a series connection of the corresponding devices in the pull-down
network, and vice-versa. Therefore, to construct a CMOS gate, one of the networks
(e.g., PDN) is implemented using combinations of series and parallel devices. The
other network (i.e., PUN) is obtained using the duality principle by walking the
hierarchy, replacing series subnets with parallel subnets, and parallel subnets with
series subnets. The complete CMOS gate is constructed by combining the PDN with
the PUN.
 The complementary gate is naturally inverting, implementing only functions such as
NAND, NOR, and XNOR. The realization of a non-inverting Boolean function (such
as AND, OR, or XOR) in a single stage is not possible, and requires addition of an
extra inverter stage.
 The number of transistors required to implement an N-input logic gate is 2N.

TWO-INPUT NAND GATE

The schematic diagram below shows a two-input NAND gate (F= A.B ). The PDN network
consists of two NMOS devices in series that conduct when both A and B are high. The PUN
is the dual network, and it consists of two parallel PMOS transistors. This means that F is 1if
A=0 or B=0, which is equivalent to F= A.B . The truth table for the simple two input NAND
gate is given below. It can be verified that the output is always connected to either VDD or
GND, but never to both at the same time.
A B F
0 0 1
0 1 1
1 0 1
1 1 0
TWO-INPUT AND GATE

The complementary gate is naturally inverting, implementing only function NAND. The
realization of a non-inverting Boolean function AND in a single stage is not possible, and
requires addition of an extra inverter stage. The truth table for the simple two input AND gate
is given below:
A B F
0 0 1
0 1 1
1 0 1
1 1 0

PROCEDURE: Procedure same as experiment number 1.

SCHEMATIC DIAGRAM FOR A TWO-INPUT NAND GATE

NETLIST TO SIMULATE NAND GATE

MNMOS_1 y b N_1 Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u

MNMOS_2 N_1 a Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MPMOS_2 y a Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_3 y b Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
v1 a gnd BIT ({0101} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n lt=50n)
v2 b gnd BIT ({0011} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n lt=50n)
vdd vdd gnd 1
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.tran .1n 200n
.power vdd .1n 200n
.print y b a p(vdd)
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM-SIMULATION OF NAND GATE

COMMENT

From the output waveform it can be seen that when either of the input (A or B) goes low
output is high and only when both the input go high output goes low which is in close
agreement with the truth table of NAND gate. Thus, the experiment has been successful.
POWER dissipation is high during any transition of output or input (from high to low or vice-
versa).

SCHEMATIC DIAGRAM FOR A TWO-INPUT AND GATE

NETLIST TO SIMULATE AND GATE

MNMOS_1 N_1 N_2 N_3 Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p
PD=2.4u
MNMOS_2 N_3 b Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_3 y N_1 Gnd N_4 nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MPMOS_1 N_1 a Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_2 N_1 b Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_3 y N_1 N_6 N_5 ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
VVoltageSource_1 a gnd BIT ({0101} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n
lt=50n)
VVoltageSource_2 b gnd BIT ({0011} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n
lt=50n)
vdd vdd gnd 1
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.tran .1n 200n
.power vdd .1n 200n
.print N_1 N_2 b y p(vdd)
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM-SIMULATION OF AND GATE

COMMENT

From the output waveform it can be seen that when either of the input (A or B) goes low
output is low and only when both the input go high output goes high which is in close
agreement with the truth table of AND gate. Thus, the experiment has been successful.
POWER dissipation is high during any transition of output or input (from high to low or vice-
versa).

Part (2)
TITLE TO DESIGN NOR GATE CIRCUIT USING STATIC CMOS DESIGN STYLE
OBJECTIVE
1. Simulation of NOR gate.
REQUIREMENT Tanner Spice Software version 13

THEORY

TWO-INPUT NOR GATE

The schematic diagram below shows a two-input NOR gate (F= A  B ). The PDN network
consists of two NMOS devices in parallel that conduct when both A and B are low. The PUN
is the dual network, and it consists of two series PMOS transistors. This means that F is 1 if
A=0 and B=0, which is equivalent to F= A  B . The truth table for the simple two input NOR
gate is given below. It can be verified that the output is always connected to either VDD or
GND, but never to both at the same time.
A B F
0 0 1
0 1 0
1 0 0
1 1 0
TWO-INPUT OR GATE

The complementary gate is naturally inverting, implementing only function NOR. The
realization of a non-inverting Boolean function OR in a single stage is not possible, and
requires addition of an extra inverter stage. The truth table for the simple two input OR gate
is given below:

PROCEDURE:
Procedure same as experiment number 1.
A B F
0 0 0
0 1 1
1 0 1
1 1 1

SCHEMATIC DIAGRAM FOR A TWO-INPUT NOR GATE

NETLIST TO SIMULATE NOR GATE
MNMOS_1 y a Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_2 y b Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MPMOS_1 N_1 a Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_2 y b N_1 Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
VVoltageSource_1 a gnd BIT ({0101} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n
lt=50n)
VVoltageSource_2 b gnd BIT ({0011} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht=50n
lt=50n)
vdd vdd gnd 1
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.tran .1n 200n
.print y b a
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM-SIMULATION OF NOR GATE

COMMENT
From the output waveform it can be seen that when either of the input (A or B) goes high
output is low and only when both the input go low output goes high which is in close
agreement with the truth table of NOR gate. Thus, the experiment has been successful.

SCHEMATIC DIAGRAM FOR A TWO-INPUT OR GATE

NETLIST TO SIMULATE OR GATE

MNMOS_1 ybar a Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_2 ybar b Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_3 y ybar Gnd Gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MPMOS_1 N_1 a Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_2 ybar b N_1 Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_3 y ybar Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
VVoltageSource_1 a gnd BIT ({0101} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht= 50n
lt=50n)
VVoltageSource_2 b gnd BIT ({0011} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s ht= 50n
lt=50n)
vdd vdd gnd 1
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.tran .1n 200n
.print a b y
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM-SIMULATION OF OR GATE

COMMENT
From the output waveform it can be seen that when either of the input (A or B) goes high
output is high and only when both the input go low output goes low which is in close
agreement with the truth table of OR gate. Thus, the experiment has been successful.

EXPERIMENT NUMBER 2C
TITLE: Design of CMOS XOR Gates
SOFTWARE TOOLS: Tanner Spice Software version 13

THEORY:
Static logic is a design methodology in integrated circuit design where there is at all times
some mechanism to drive the output either high or low. For example, in many of the popular
logic families, such as TTL and traditional CMOS, there is always a low-impedance path
between the output and either the supply voltage or the ground. The most widely used logic
style is static CMOS. A static CMOS gate is a combination of two networks, called the pull-
up network (PUN) and the pull-down network (PDN). The function of the PUN is to provide
a connection between the output and VDD anytime the output of the logic gate is meant to
be 1 (based on the inputs). Similarly, the function of the PDN is to connect the output to VSS
when the output of the logic gate is meant to be 0 (based on the inputs). The PUN and PDN
networks are constructed in a mutually exclusive fashion such that, one and only one of these
networks is conducting in the steady state:

Static Logic Design of NAND, NOR, XOR and XNOR Gates:

In order to design 2-input NAND, NOR, XOR and XNOR gates for equal rise and fall time, it
is necessary to first design an inverter with equal rise and fall time. This involves
compensating for the difference in electron and hole mobilities. For silicon material, the
electron mobility is about 2.5 to 3 times greater than the hole mobility. Therefore, to have
equal rise and fall time in an inverter, we must choose the W/L ration of pMOS as 2.5 times
greater than that of the nMOS transistor. After performing this task, we need to size the
transistors of each gate under worst case conditions (of input combination) for charging and
discharging resistances Rc and Rd. (In every gate circuit, the PUN provides maximum ON
resistance for rise time and the PDN provides maximum ON resistance for fall time.) For a
NAND gate, the worst-case charging corresponds to an input combination where only one of
the pMOS is ON and discharging takes place only when both nMOS’ are turned ON. i.e. in
the worst case, Rc/Rd=1/2. Thus, in order to equalize both currents (considering also the
mobility differences), we must have (W/L)p=(2.5*2)(W/L)n. This can be achieved in a
180nm technology by choosing Wn=0.18 µm and Wp=0.90 µm. Similarly, in case of a NOR
gate, (W/L)p must be equal to (2.5*0.5)(W/L)n which can be achieved by taking Wn=0.36µm
and Wp=0.45µm. For XOR and XNOR gates, worst case Rc/Rd  ratio is equal to one.
Therefore, (W/L)p must be equal to (2.5*1)(W/L)n for both gates.

Procedure: Same as Experiment 1

SCHEMATIC DIAGRAM

NETLIST:

SPICE export by: SEDIT 13.02

* Design: EXOR2
* Cell: EXOR2
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude.model: no
* Exclude.end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Users\Gourav\Desktop\EXOR2
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 64
*-------- Devices: SPICE.ORDER > 0 --------
MN1 Out A Gnd 0 NH W=.45u L=150n AS=.3375p PS=2.25p AD=.3375p PD=2.4u
MP1 Out A Vdd Vdd PH W=.9u L=150n AS=.675p PS=3.3u AD=.675p PD=3.3u
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 --------
XINV_1 A ABAR Gnd Vdd INV
XINV_2 B BBAR Gnd Vdd INV
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_1 BBAR Gnd Gnd NH W=.45u L=150n AS=.3375p PS=2.25p AD=.3375p
PD=2.4u
MNMOS_2 N_3 B Gnd Gnd NH W=.45u L=150n AS=.3375p PS=2.25p AD=.3375p
PD=2.4u
MNMOS_3 Out N_2 N_1 Gnd NH W=.45u L=150n AS=.3375p PS=2.25p AD=.3375p
PD=2.4u
MNMOS_4 Out A N_3 Gnd NH W=.45u L=150n AS=.3375p PS=2.25p AD=.3375p
PD=2.4u
MPMOS_1 N_7 A Vdd Vdd PH W=.9u L=150n AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_2 N_7 B Vdd Vdd PH W=.9u L=150n AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_3 Out ABAR N_7 Vdd PH W=.9u L=150n AS=.675p PS=3.3u AD=.675p
PD=3.3u
MPMOS_4 Out BBAR N_7 Vdd PH W=.9u L=150n AS=.675p PS=3.3u AD=.675p
PD=3.3u
VVoltageSource_1 A Gnd BIT({0101}pw=50n on=1 off=0.0 delay=0 rt=0.1n ft=0.1n lt=50n
ht=50n )
VVoltageSource_2 B Gnd BIT({0001}pw=50n on=1 off=0.0 delay=0 rt=0.1n ft=0.1n lt=50n
ht=50n )
Vdd Vdd gnd 1
.tran 0.1n 200n
.print V(A) V(B) V(Out)
.include "C:\Users\Gourav\Desktop\dual.md"
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end
OUTPUT WAVEFORM
 EXPERIMENT NUMBER 3

TITLE TO DESIGN A SINGLE BIT FULL ADDER CIRCUIT USING STATIC CMOS
DESIGN STYLE.

OBJECTIVE
1. Simulation of basic gates (AND, OR) and their complements
2. Simulation of 1-bit full adder circuit to check its functionality

SOFTWARE TOOLS: Tanner Spice Software version 13

THEORY

THE ADDER

Addition is the most commonly used arithmetic operation. It often is the speed-limiting
element as well. Therefore, careful optimization of the adder is of the utmost importance.
This optimization can proceed either at the logic or circuit level. Typical logic-level
optimizations try to rearrange the Boolean equations so that a faster or smaller circuit is
obtained. Circuit optimizations, on the other hand, manipulate transistor sizes and circuit
topology to optimize the speed.

THE BINARY ADDER: DEFINITION

The following table shows the truth table of a binary full adder:

A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

A and B are the adder inputs, ci is the carry input, S is the sum output, and C o is the carry
output. The Boolean expression for S and Co is given by the following equations:
s  A  B  C i  ABC i  ABC i  A BC i  ABC i
C 0  AB  BC i  AC i

THE FULL ADDER: CIRCUIT DESIGN CONSIDERATIONS

One way to implement the full-adder circuit is to take the logic equations above and to
translate them directly into complementary CMOS circuitry. Some logic manipulations can
help to reduce the transistor count. For instance, it is advantageous to share some logic
between the sum- and carry-generation sub circuits, as long as this does not slow down the
carry generation, which is the most critical part, as stated previously. The following is an
example of such a reorganized equation set:
 C 0  AB  BC i  AC i
S  ABC i  C 0 ( A  B  C i )
The equivalence with the original equations is easily verified. The corresponding static
CMOS, is shown in the schematic diagram and requires 28 transistors. In addition to
consuming a large area, this circuit is slow:
 Tall PMOS transistor stacks are present in both carry- and sum-generation circuits.
 The intrinsic load capacitance of the Co signal is large and consists of two diffusion
and six gate capacitances, plus the wiring capacitance.
 The signal propagates through two inverting stages in the carry-generation circuit. As
mentioned earlier, minimizing the carry-path delay is the prime goal of the designer of
high-speed adder circuits. Given the small load (fan-out) at the output of the carry
chain, having two logic stages is too high a number, and leads to extra delay.
 The sum generation requires one extra logic stage, but that is not that important, since
a factor appears only once in the propagation delay of the ripple-carry adder of the
first equation.

Although slow, the circuit includes some smart design tricks. Notice that the first gate of the
carry-generation circuit is designed with the Ci signal on the smaller PMOS stack, lowering
its logical effort to 2. Also, the NMOS and PMOS transistors connected to Ci are placed as
close as possible to the output of the gate. This a direct application of the circuit-optimization
technique-transistors on the critical path should be placed as close as possible to the output of
the gate. For instance, in stage k of the adder, signals Ak and Bk are available and stable long
before Ci,k (=Co,k-1 ) arrives after rippling through the previous stages. In this way, the
capacitances of the internal nodes in the transistor chain are precharged or discharged in
advance. On arrival of Ci,k , only the capacitance of the node where inverter is connected to
get Co output has to be (dis)charged. Putting the Ci,k transistors closer to VDD and GND would
require not only the (dis)charging of the capacitance of that node, but also of the internal
capacitances.
The speed of this circuit can now be improved gradually by using some of the adder
properties. First, the number of inverting stages in the carry path can be reduced by exploiting
the inverting property-inverting all the inputs of a full-adder cell also inverts all the outputs.
This rule allows us to eliminate an inverter in a carry chain.

Procedure: Same as Experiment no-1

SCHEMATIC DIAGRAM-ONE BIT FULL ADDER CIRCUIT

NETLIST-TO DESIGN OF ONE BIT FULL ADDER CIRCUIT TO CHECK ITS

FUNCTIONALITY

MN1 Out A Gnd 0 nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u

MP1 Out A Vdd Vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 --------
XINV_1 cobar co Gnd Vdd INV
XINV_2 sbar s Gnd Vdd INV
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 cobar a N_1 gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_2 N_1 b Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_3 cobar ci N_6 gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_4 N_6 a Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_5 N_6 b Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_10 N_3 b N_5 gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_11 N_5 ci Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_12 sbar cobar N_4 gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p
PD=2.4u
MNMOS_6 N_4 a Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_7 N_4 b Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_8 N_4 ci Gnd gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MNMOS_9 sbar a N_3 gnd nh W=.45u L=.15u AS=.3375p PS=2.4u AD=.3375p PD=2.4u
MPMOS_1 N_9 a Vdd vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_2 N_9 b Vdd vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_3 cobar ci N_9 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_4 N_2 a N_9 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_5 cobar b N_2 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_6 N_26 a Vdd vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_7 N_26 b Vdd vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_8 N_26 ci Vdd vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_9 sbar cobar N_26 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_10 N_7 a N_26 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_11 N_8 b N_7 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
MPMOS_12 sbar ci N_8 vdd ph W=.9u L=.15u AS=.675p PS=3.3u AD=.675p PD=3.3u
VVoltageSource_3 ci gnd BIT ({01010101} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s
ht=50n lt=50n)
VVoltageSource_1 a gnd BIT ({00001111} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s
ht=50n lt=50n)
VVoltageSource_2 b gnd BIT ({00110011} pw=50n on=1 off=0 rt=.1n ft=.1n delay=0s
ht=50n lt=50n)
vdd vdd gnd 1
.include" C:\Documents and Settings\Gourav\Desktop\dual.md "
.tran .1n 400n
.print ci b a co s
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

OUTPUT WAVEFORM-ONE BIT FULL ADDER CIRCUIT

CONCLUSION

We see that in the output waveform of one-bit full adder circuit, the bit pattern for sum and
carry with respect to addend, augend and input carry coincides with the data obtained from
truth table of the one-bit full adder circuit. Thus, the functionality of one-bit full adder circuit
is verified and the experiment has been successful.
 EXPERIMENT NUMBER 4A

 Name of The Experiment: Familiarity with EDA tools for VLSI design/FPGA
based system design.

DESIGNING A FULL ADDER.

 Objectives:
i) To write a full adder program using VHDL.
ii) To check functionalities of the adder.
iii) Obtaining the desired output waveform.

 Procedure:
1. Double click on Xilinx ISE 10.1
2. Click on Fine->New Project

2. Give Project Name

3. Specify Project Location.
4.Select Top –level source HDL
5.Select Preferred Language –VHDL.
6.Check on Enable Enhanced Design Summary.

7.Click on New Source

8.Click on Next
9.Select VHDL Module.
10.Give File Name.

10.Give Port Name

Schematic Diagram:

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladd;

architecture Behavioral of fulladd is

begin
sum<=a xor b xor cin;
cout<=(a and b)or(b and cin)or(cin and a);
end Behavioral;

Simulation Result & Waveform:

Conclusion:
 Here we use Xilinx module to do our experiment.
 Schematic diagram shows the different I/Os & Signal used by program.
 Here VHDL source has been selected as program editor & Test Bench
Waveform source to observe the waveform.
 It’s an important note that the change in output is occurring after 50ns of
input given.
Truth Table:
a b cin sum cout
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
 Result is verified Successfully.
 EXPERIMENT NUMBER 4B

 Name of The Experiment:

DESIGNING A FULL ADDER USING TWO HALF ADDER AND AN OR

GATE.
 Objectives:
i) To write a full adder program using two half adder & an OR gate, using
Hardware Description Language.
ii) To check functionalities, simulate the program.
iii) Obtaining the desired output waveform.
 Procedure: Same as previous.

 Schematic Diagram of Full adder using two half adder & an OR gate:

Schematic diagram of Full adder.

 Net List or VHDL program of Full Adder:

 Program of Half adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha is
Port ( a : in STD_LOGIC
b : in STD_LOGIC;
s : out STD_LOGIC;
Cout : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin
s<=a xor b;
Cout<=a and b;
end Behavioral;

 Program of OR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or_1 is
Port ( x : in STD_LOGIC;
 y : in STD_LOGIC;
z : out STD_LOGIC);
end or_1;
architecture Behavioral of or_1 is
begin
z<=x or y;
end Behavioral;

 Program of Full adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout1 : out STD_LOGIC;
S : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
component ha
port( a: in std_logic;
b: in std_logic;
s: out STD_LOGIC;
Cout: out STD_LOGIC);
end component;
component or_1
port(x: in std_logic;
y: in std_logic;
z: out STD_LOGIC);
end component;
signal sig1,c1,c2: std_logic;
begin
X1: ha port map(a1,b1,sig1,C1);
X2: ha port map(Cin,sig1,S,c2);
X3: or_1 port map(c1,c2,Cout1);
end Behavioral;

 Simulation result:
 Remarks:

 Here we use Xilinx module to do our experiment.

 Schematic diagram shows the different I/Os & Signal used by program.
 Here VHDL source has been selected as program editor & Test Bench
Waveform source to observe the waveform.
 It’s an important note that the change in output is occurring after 50ns of
input given.
 During call operation using PORT MAP command it should be remember to
write the actual parameter’s name of component’s module at component
declaration section & to use the program parameter’s name at PORT MAP
command.
 Here we use Structural mode which is quite long in programming.
 In full adder design it will be easier if we direct implement the program
using commands in behavioral mode.
 EXPERIMENT NUMBER 4C

 Name of The Experiment:

DESIGNING AN 3:8 DECODER.

 Objectives:
i) To write a 3:8 decoder program using Hardware Description Language.
ii) To check functionalities, simulate the program.
iii) Obtaining the desired output waveform.
 Procedure: Same as previous.

 Schematic Diagram of 3:8 Decoder:

Schematic diagram of 3:8 Decoder.

 Truth Table of 3:8 Decoder:

Input Output
d(0) d(1) d(2) O(0) O(1) O(2) O(3) O(4) O(5) O(6) O(7)
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

 Net List or VHDL program of 3:8 Decoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dec_3_8 is
Port ( d1 : in STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (7 downto 0));
end Dec_3_8;
architecture Behavioral of Dec_3_8 is
begin
process(d1)
begin
if en='1' then
if(d1="000") then o<="00000001";
elsif (d1="001") then o<="00000010";
elsif (d1="010") then o<="00000100";
elsif (d1="011") then o<="00001000";
elsif (d1="100") then o<="00010000";
elsif (d1="101") then o<="00100000";
elsif (d1="011") then o<="01000000";
else o<="10000000";
end if;
end if;
end process;
end Behavioral;

Technology Schematic Diagram:

  Simulation result:

 Another Approach:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
D(0)<=(not A)and(not B)and(not C);
D(1)<=(not A)and(not B)and C;
D(2)<=(not A)and B and(not C);
D(3)<=(not A)and B and C;
D(4)<=A and(not B)and(not C);
D(5)<=A and(not B)and C;
D(6)<=A and B and(not C);
D(7)<=A and B and C;
end Behavioral;
 Simulation Result & Waveform:

 Technology Schematic Diagram:

 Remarks:

 Here we use Xilinx module to do our experiment.

 Schematic diagram shows the different I/Os & Signal used by program.
 Here VHDL source has been selected as program editor & Test Bench
Waveform source to observe the waveform.
 It’s an important note that the change in output is occurring after 50ns of
input given.
 EXPERIMENT NUMBER 4D

 Name of The Experiment:

DESINING AN 8:1 MULTIPLEXER USING TWO 4:1 MULTIPLEXER.

 Objectives:
i) To write an 8:1 Multiplexer program using two 4:1 multiplexers & an OR
gate, using Hardware Description Language.
ii) To check functionalities, simulate the program.
iii) Obtaining the desired output waveform.
 Procedure: Same as previous.

 Schematic Diagram of 8:1 Multiplexer using two 4:1 Multiplexer & an OR

gate:

Schematic diagram of 8:1 multiplexer.

 Net List or VHDL program of 8:1 multiplexer:

 Program of 4:1 Multiplexer:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4 is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
o : out STD_LOGIC);
end mux_4;
 architecture Behavioral of mux_4 is
begin
process(s)
begin
if en='1' then
case s is
when "00" =>o<=d(0);
when "01" =>o<=d(1);
when "10" =>o<=d(2);
when others =>o<=d(3);
end case;
end if;
end process;
end Behavioral;

 Program of OR gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or_1 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end or_1;
architecture Behavioral of or_1 is
begin
z<=x or y;
end Behavioral;
 Program of 8:1 Multiplexer:
entity mux_8 is
Port ( d1 : in STD_LOGIC_VECTOR (7 downto 0);
s1 : in STD_LOGIC_VECTOR (2 downto 0);
y1 : out STD_LOGIC);
end mux_8;
architecture Behavioral of mux_8 is
component or_1
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component mux_4
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
o : out STD_LOGIC);
end component;
signal sig1,sig2 : std_logic;
begin
 A1: mux_4 port map(d1(3 downto 0),s1(1 downto 0),s1(2),sig1);
A2: mux_4 port map(d1(7 downto 4),s1(1 downto 0),(not s1(2)),sig2);
A3: or_1 port map(sig1,sig2,y1);
end Behavioral;

 Technology Schematic Diagram:

 Simulation result:

 Another Approach:
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
s1 : in STD_LOGIC;
 s2 : in STD_LOGIC;
s3 : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
y<=((not s1)and(not s2)and(not s3)and d(0))or
((not s1)and(not s2)and s3 and d(1))or
((not s1)and s2 and(not s3)and d(2))or
((not s1)and s2 and s3 and d(3))or
(s1 and(not s2)and(not s3)and d(4))or
(s1 and(not s2)and s3 and d(5))or
(s1 and s2 and(not s3)and d(6))or
(s1 and s2 and s3 and d(7));
end Behavioral;

 Simulation Result & Waveform:

 Block Diagram:

 Remarks:
 Here we use Xilinx module to do our experiment.
 Schematic diagram shows the different I/Os & Signal used by program.
 Here VHDL source has been selected as program editor & Test Bench
Waveform source to observe the waveform.
 It’s an important note that the change in output is occurring after 50ns of
input given.
 During call operation using PORT MAP command it should be remember to
write the actual parameter’s name of component’s module at component
declaration section & to use the program parameter’s name at PORT MAP
command.
 Here we use Structural mode which is quite long in programming.
 In 8:1 multiplexer design it will be easier if we direct implement the
program using commands in behavioral mode/dataflow mode.