MODULE -4

Sub system design and PLA

ACSCE

ACSCE DR.HBB notes on VLSI 1

 SYSTEM and SUB SYSTEM
• System is a set of interdependent entities/modules /leaf cell which interact
among themselves to form a complete unit.
• Large systems are composed of subsystems known as leaf cells.
• Most basic leaf cells are inverter, NAND,CMOS ….

ACSCE DR.HBB notes on VLSI 2

 A system

ACSCE DR.HBB notes on VLSI 3

 ARCHITECTURAL ISSUES OF SUBSYSTEM DESIGN
• In any VLSI system, logical and systematic approach is essential.
For ex:
In designing an MSI logic circuit comprising of
a) 500 transistors - 2 engineer-months are required, similarly in designing
b) 500,000 transistor - 2,000 engineer-months or 170-engineers - years are
required.
• Thus as complexity increases, design time exponentially increases.
Therefore,
we must adopt design methods which handle complexity
with a less time and
with less labor.

ACSCE DR.HBB notes on VLSI 4

GUIDELINES TO BE FOLLOWED AT THE SUBSYSTEM OR LEAF-CELL

ACSCE DR.HBB notes on VLSI 5

ACSCE DR.HBB notes on VLSI 6
SWITCH LOGIC and GATE(RESTORING LOGIC) are the 2 basic ways of build
logic circuits in digital systems in MOS technology.
SWITCH LOGIC: It is based on “Pass Transistor” or “Transmission Gate”.

Pass transistor
➢ Buffer used in MSI = PT used in VLSI.
➢ One form of logic that is popular in nMOs rich ckt is PTLogic.
➢ It occupies minimum space.
➢ One of the alternative for conventional logic
➢ PT Logic will not allow us to have a direct path between Vcc and GND . Here
,current only flows on switching. Therefore, power dissipation is small.
➢ Minimum size of PT is 2λ x 2λ.
➢ PT can be used as either Pull Up Transistor or Pull down Transistor.

ACSCE DR.HBB notes on VLSI 7

 Pass Transistor
• Transistors can be thought as a switch controlled by its gate signal.
• PT are single FET’s that pass signal b/w drain to source, instead of fixed
power supply value.
• It cannot pass entire Voltage range.
• PT are used in designing regular arrays such as ROM, PLA’s and
Multiplexers.

➢ VO=VDD-VT (nMOS Transistor).

➢ VO=VDD+VT (pMOS Transistor).

➢ It is similar to model shown below:

ACSCE DR.HBB notes on VLSI 8

 MOSFET AS PASS TRANSISTOR

Depending on Control Signal at gate, Vin is passed to output. A

transistor connected in this manner is called Pass transistor.

Advantages of PT:
occupies less area than logic gateS
3 Terminal device
require no DC power
DO not have direct short b/w Vcc and gnd.
ACSCE DR.HBB notes on VLSI 9
MOSFET as SWITCH

ACSCE DR.HBB notes on VLSI 10

MOSFET as Pull up and Pull down transistor

ACSCE DR.HBB notes on VLSI 11

SERIES AND PARALLEL CONNECTION OF SWITCHES.

ACSCE DR.HBB notes on VLSI 12

 Series and Parallel a a a a a

Switches g1
g2
0 0 1 1

0 1 0 1
b b b b b

• nMOS: 1 = ON (a) OFF OFF OFF ON

• pMOS: 0 = ON a
0
a
0
a
1
a
1
a

g1

• Series: both must be ON g2

0 1 0 1
b b b b b
• Parallel: either can be ON (b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

ACSCE DR.HBB
Slide 13notes on VLSI
MODEL FOR Pass Transistor logic

More examples from Book –I of VLSI -

HBB NOTES.
PAGE NO 25 TO 27

PT as AND gate, XNOR,CMOS XNOR,CMOS

4 way selector
A general 2 variable functional block, 4:1
Mux, 2 way selector, 2:1 MUX,

ACSCE DR.HBB notes on VLSI 14

 Signal degradation in nMOS tr
• Tr here behaves like a ‘R’ and ‘C’.
• When G=1, Vin = Vd = Vs = Vo. The ‘C’ charges and Vo
increases.
• This reduces Vgs.
• When Vgs becomes < Vtn,Vgs < Vtn,tr= off=C.O
• Tr enters Cutoff and C cannot charge.
• Maximum output voltage ,
• Vo= VGG –Vtn = 5-1.5 = 3.5Volts approximately.
• Disadvantage:
• o/p of nMos tr is always < 5V.
• i.e logic 1 level in nMOs < 5V.
• This implies that transmission of Logic 1 is degraded as it
passes through the gate.
• This is called signal degradation.
• If source tries to increase the voltage , device will cutoff.

ACSCE DR.HBB notes on VLSI 15

 nMOS:
Page 17 , book -1
• An nMOS transistor is an almost pMOS
perfect switch when passing a 0 • Transmission of Logic 0 is degraded
and thus we say it passes a strong as it passes through the p device.
0. VO=VDD+ VT
• However, the nMOS transistor is • Vin = 0 , Vo=0+0.7 = 0.7
imperfect at passing a 1. The high • Vin= 5,Vout = 5.7 >5 V
• voltage level is somewhat less • pMOS tr is good at transmitting ‘1’
than V DD . We say it and bad in transmitting ‘0 ‘.
• passes a degraded or weak signal. • A pMOS transistor again has the
Transmission of Logic 1 is opposite behavior, passing
degraded as it passes through the • strong 1s but degraded 0s.
nmos.
VO=VDD-VT (nMOS tr.)
• Vin = 0 , Vo= 0 - 0.7 = - 0.7
• Vin= 5, Vout = 4.3 < 5 V
Nmos is bad in transmitting ‘1’ or
5V and good at transmitting zero.

ACSCE DR.HBB notes on VLSI 16

PASS TRANSISTOR AS SWITCHES.

ACSCE DR.HBB notes on VLSI 17

Case: I and II

ACSCE DR.HBB notes on VLSI 18

 Case III

ACSCE DR.HBB notes on VLSI 19

4:1 mux using pass transistor

ACSCE DR.HBB notes on VLSI 20

 Transmission gate/ Complementary switches
• When an nMOS or pMOS is used alone as an imperfect
switch, we sometimes call it a pass transistor.
• TG is used to eliminate the undesirable threshold voltage
effects which give rise to the loss of logic levels in PT.
• A transmission gate, or analog switch, is defined as an
electronic element that will selectively block or pass a signal
level from the input to the output.
• This solid-state switch is obtained by combining an nMOS and
a pMOS transistor in parallel.
• They transmit entire voltage from
input to output.

ACSCE DR.HBB notes on VLSI 21

 Transmission Gates- WORKING
• Pass transistors produce degraded outputs
• Transmission gates pass both ‘0’ and ‘1’ well when
g=1 and gb=0.
• When g=0,gb=1,it enters high impedance state.
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

Advantages : No degradations of
g g g signals.
a b a b a b D.A:
gb gb gb More area is occupied .
It requires 2 FET’s and one inverter.
ACSCE DR.HBB
Slide 22notes on VLSI
 GATE (restoring LOGIC)
• It is based on general arrangements circuits.
• Ex: Inverter ,NAND,NOR and OR.

ACSCE DR.HBB notes on VLSI 23

 nMOS INVERTER

4:1 or 8:1

CIRCUIT SYMBOL

ACSCE DR.HBB notes on VLSI 24

CMOS INVERTER

ACSCE DR.HBB notes on VLSI 25

Bi- CMOS INVERTER colour plate 3.1d
We combine,
low static power consumption of CMOS and
high current driving capability of BJT,
BiCMOS configuration combines best of two
worlds.

ACSCE DR.HBB notes on VLSI 26

 Page number 20,21, book- 1 vlsi

• Nand gate
• Nor gate

ACSCE DR.HBB notes on VLSI 27

Examples for structured design
( Combinational logic)

ACSCE DR.HBB notes on VLSI 28

 PARITY GENERATOR ( PG)- Basics
• It is a concept to detect errors.
• A parity bit is commonly used for error detection during the
transmission of digital signals.
• Parity systems: Odd parity and Even parity
• Parity bit is added to original message signal to make it either
even or odd parity.
• Exclusive-OR and exclusive-NOR gates are used in applications
such as parity checking, binary comparison and controlled
complementing circuits.
• Electrical noise in the transmission of binary information can
cause errors. Parity can detect these types of errors.

ACSCE DR.HBB notes on VLSI 29

 The Exclusive-OR Gate-Basics
• The output is HIGH if either one or the
other inputs are HIGH., but not both.
• o/p is high for odd number of ones.

ACSCE DR.HBB notes on VLSI 30 4

 The Exclusive-OR Gate- Basics
Logic circuits for the exclusive-OR function.

The Exclusive-OR Gate

The Exclusive- NOR Gate

ACSCE DR.HBB notes on VLSI 31 5

 Basic block diagram for PG
• (n+1)bit input
• n = no of n inputs
• 1 bit is = parity
bit

ACSCE DR.HBB notes on VLSI 32 10

Page 152,fig 6.16

ACSCE DR.HBB notes on VLSI 33

ONE BIT PARITY CELL PAGE 152 , FIG 6.17
• Here ,parity information is passed
from one cell to next cell and is
modified or not , depending on
input Ai and Ai.
• Pi = (P’i-1) ( Ai) + (Pi-1) (A’i)
• X-OR gate is used between inputs
and Parity of previous stage.
• When writing stick diagram, cell
boundary must be chosen in each
case so that cells may be
cascaded at will.

ACSCE DR.HBB notes on VLSI 34

Stick diagram for one bit nMOS PG.
• Fig 6.18 a

35

ACSCE DR.HBB notes on VLSI

Stick diagram for one bit CMOS PG
• Fig 6.18b

ACSCE DR.HBB notes on VLSI 36

 MULTIPLEXER / DATA SELECTOR
• The multiplexer OR “MUX” is a combinational logic circuit
designed to switch one of several input lines through to a
single common output line by the application of a control
signal.
• It can be either digital circuits or analogue types using
transistors, MOSFET’s or relays to switch one of the voltage or
current inputs through to a single output.
• They are available in a number of standard configuration in
TTL or other logic families.

ACSCE DR.HBB notes on VLSI 37

 4 WAY MULTIPLEXER.
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Select lines

ACSCE DR.HBB notes on VLSI 38

Implementation using pass transistor

ACSCE DR.HBB notes on VLSI 39

 transmission gate based CMOS stick diagram - 6.24 b- place
colour plate
Note :
All n transistor are below the
demarcation line and close to Vss rail to
configure p-well and Vss contacts.
All p transistor are above the
demarcation line and close to Vdd rail .
Logic level 1 will not be degraded.

ACSCE DR.HBB notes on VLSI 40

FOUR WAY N-SWITCH BASED MULTIPLEXER LAYOUT

Standard cell = 7λ x 11λ

ACSCE DR.HBB notes on VLSI 41

PLA – Programmable logic array

ACSCE DR.HBB notes on VLSI 42

 Contents covered - I
The Programmable Logic Array (PLA)- VLSI Design”- Douglas
A. Pucknell& Kamran Eshraghian, PHI 3rd,Edition (original
Edition – 1994). Slide 2- 11

Contents covered – II
FIELD PROGRAMMABLE GATE ARRAYS
FPGA ARCHITECTURE
PHYSICAL DESIGN OF FPGA
“FPGA Based System Design”- Wayne Wolf, Pearson Education,
Technology and Engineering, 2004 . Slide 22 - 49

ACSCE DR.HBB notes on VLSI 43

 The Programmable Logic Array (PLA)

Text book :
“Basic VLSI Design”- Douglas A. Pucknell&
Kamran Eshraghian, PHI 3rd,Edition (original
Edition – 1994).

ACSCE DR.HBB notes on VLSI 44

 The Programmable Logic Array (PLA) –introduction
A simple solution to mapping of irregular combinational logic functions
into regular Structures is provided by PLA.

It provides the designers a regular way of implementing / providing

multiple ‘m’ outputs with n inputs variables using sum-of-products (SOP)
logic functions.

'AND' plane is responsible for the generation of all product terms needed
to form logic functions. 'OR' plane OR's (sums) the selected product terms
together to form the desiredACSCE
logic functions.
DR.HBB notes on VLSI 45
 The Programmable Logic Array (PLA)

▪Personalized" by making or breaking connections among the gates.

▪It performs the same basic function as a ROM.
▪Pre-fabricated building block of many AND/OR gates (or NOR, NAND).
▪It consists of two level of combinational logic functions .
▪PLA describes class of standalone devices that allows users to program the
functionalities.
▪Presently, we have PLA with 14 i/p variables, 96 product terms , 8 o/p
functions. Such elements are programmed by manufacturer or field
programmed by user to meet requirements.
▪The capability of these programmable devices are limited and have been
. replaced by significantly powerful field programmable gate array (FPGA).

ACSCE DR.HBB notes on VLSI 46

 ▪

1) In Vlsi design, however, Custom PLA’s can be readily designed and must be programmed during
the design process . Thus, for the VLSI designer , PLA’s are tailored
to specific task with little wastage of function or space .
.
2)PLA structure is normally expanded, or modified during design.

3) In vlsi design, our objectives is to map circuits onto silicon to meet specifications
Floor plan indicates PLA mapping onto chips. It also gives notional areas and relative disposition of
particular circuits and subsystems.
.
De-morgan’s theorem is used to manipulate AND-OR combinational logic requirements into NOR
form. .

ACSCE DR.HBB notes on VLSI 47

 Depending on which of the AND/OR logic arrays is
programmable, we have three basic organizations

AND ARRAY OR ARRAY

ORGANIZATION
PROG. FIXED
PAL
FIXED PROG.
PROM
PROG. PROG.
PLA

Programmable Array Logic – PAL

ACSCE DR.HBB notes on VLSI 48

General architecture of PLA

ACSCE DR.HBB notes on VLSI 49

 General architecture of PLA
• Fig. shows 3 input and 3 output PLA. Along
with 3 inputs, its compliment is also
available.
• With this, it is possible to generate many
functions of product terms in AND array.
• Inputs are A, B & C and outputs are O1, O2
& O3 .
• X indicates no connection and desired
product term can be obtained by making
relevant connection in the AND array
(shown with dot)
• Similarly connection can be made in OR
array.
• For obtaining O1 = B’C + A’B, the
connections are shown in the Fig.

ACSCE DR.HBB notes on VLSI 50

• In VLSI design, objective is to map circuits onto Si to meet the
specifications.
• In circuit implementation for AND and OR array needs NAND and NOT
logic and NOR and NOT logic respectively. But this includes more
fabrication steps.
• However, this can be simplified by implementing the logic in NOR logic.
Thus AND and OR array can be implemented using NOR logic.
• If the output of NOR is complimented, then we get the OR logic. Similarly
if both the inputs of AND is complimented and given to NOR it gives AND
logic

ACSCE DR.HBB notes on VLSI 51

PLA floor plan for AND/OR based

ACSCE DR.HBB notes on VLSI 52

PLA floor plan for NOR based

ACSCE DR.HBB notes on VLSI 53

 FPGA –
FIELD PROGRAMMABLE GATE ARRAYS

“FPGA Based System Design”- Wayne Wolf,

Pearson Education, Technology and
Engineering, 2004

DR.HBB . PLA - VLSI DESIGN 1

FPGA -FIELD PROGRAMMABLE GATE ARRAYS

An introduction

.
DR.HBB . PLA - VLSI DESIGN 2
 FPGA
• FPGA plays the complementary role of microprocessor.
• Standard parts: They are not designed for any particular
functions but are programmed by customer for a particular
purpose.
• Implement multilevel logic:
They use both programmable logic blocks and Programmable
interconnect to build the multi level logic functions.
• FABRIC: Combination of logic and interconnect.
• They are used in all sorts of digital systems. Because of its
a) high speed Telecommunications equipment
b) as video accelerators in home personal video recorders
(PVR)’s.
• FPGA is far better than smaller programmable device like
PLD’s.
DR.HBB . PLA - VLSI DESIGN 3
 FPGA

Permanently Re-programmed / Reconfigurable

programmed Devices

❑ Device need not be thrown away

every time a change is made.

❑It can be reprogrammed on the fly

during system operation.

Thus ,one hardware to perform several

diff functions.
Thus systems can be operated in diff
modes.

DR.HBB . PLA - VLSI DESIGN 4

Schematics and Logic Functions

DR.HBB . PLA - VLSI DESIGN 6

 Schematics Symbols For
Schematics Symbols For
Register Transfer
Logic Gates
Components

DR.HBB . PLA - VLSI DESIGN 7

 Digital Design and FPGAs
Microprocessor or FPGA /ASIC-
General Purpose operating Application specific integrated
system circuit

• Rely on S/w to implement • Not custom parts

functions. • Slower
• Slower • Burn more power than
• More power consumption custom logic.
than custom chips • Expensive

DR.HBB . PLA - VLSI DESIGN 8

Difference between

DR.HBB . PLA - VLSI DESIGN 9

DR.HBB . PLA - VLSI DESIGN 10
when FPGA is used in final design, the jump from prototype to product is
much smaller and easier to negotiate.

The same FPGA can be used in several diff designs reducing cost.

The design can be programmed into FPGA and tested immediately.

DR.HBB . PLA - VLSI DESIGN 11

DR.HBB . PLA - VLSI DESIGN 12
 Alternative to FPGA-
ASIC – Application Specific IC
• ASIC is designed to implement a particular logical function/
designed for particular purpose.
• ASIC uses predesigned layouts for logic gates.
• Design of ASIC ----Mask ---- used to fabricate IC.
• ASIC – after months – fabricated----tested.
• Consumes low power.
• Faster than FPGA
• Cheaper.
• FPGAs use more transistors for a given function than ASICs,
but an FPGA can be designed in days compared to the year
long design cycle required for garden variety FPGAs.
DR.HBB . PLA - VLSI DESIGN 13
 FPGA -Based system design
Goals and techniques
The logical function to be performed is only one of the goals that must be
met by an FPGA or any digital system design. Many other attributes must
be satisfied for the project to be successful.
1) Performance : Logic must run at desired rate.It is measured in
many ways, such as throughput and latency. Clock rate often
measures performance.
2) Power / Energy : Chip must run within an energy or power
budget. Energy consumption is very imp in battery powered
system.
• 3) Design time : FPGAs have standard parts, have several
advantages in design time. As prototypes ,programming
should be very quick. It effects design cost also.

DR.HBB . PLA - VLSI DESIGN 14

4) Design cost : Design time is one important
component in design cost, but other factors such as
required support tools may be considered. FPGA
tools are less expensive than custom VLSI
tools.
5) Manufacturing cost : Its cost of replicating
the system many times. FPGAs are generally more
expensive than ASICs due to overhead of
programming. But the fact that they are standard
parts helps to reduce their cost .

DR.HBB . PLA - VLSI DESIGN 15

 Design Challenges
Design is particularly hard because we must solve several
problems.
• Multiple levels of abstractions
• Multiple and conflicting costs
• Short design time

DR.HBB . PLA - VLSI DESIGN 16

DR.HBB . PLA - VLSI DESIGN 17
DR.HBB . PLA - VLSI DESIGN 18
Assignments:
Section 1.4.2 ( page 31,32 )
1.4.4 (37,38,39)

DR.HBB . PLA - VLSI DESIGN 19

DR.HBB . PLA - VLSI DESIGN 20
 FPGA FABRICS - Basic structure
3.2 - FPGA Architecture
• FPGA consists of three major elements.
Combinational Logic
Interconnect
I/O pins

DR.HBB . PLA - VLSI DESIGN 21

DR.HBB . PLA - VLSI DESIGN 22
 FPGA Architecture
➢The combinational logic is divided into small units which is known as logic
elements(LE) or combinational logic blocks(CLB).

➢ LE or CLB usually forms the functions of several logic gates.

➢Interconnections between these logic elements are made using programmable

interconnects.

➢This interconnects are logically organized into channels or other units.

➢FPGA offers several interconnects depending on the distance between CLB’s that
are to be connected: clock signals are provided with their own interconnection
networks.

➢I/O pins are referred as I/O blocks (IOB’s).

➢These are generally programmable for inputs or outputs and often provides other
features such as low power or high speed connection.
DR.HBB . PLA - VLSI DESIGN 23
 FPGA Interconnect s

The FPGA designer should rely on pre-designed wiring, unlike custom

VLSI designer cannot design wires as needed.
The interconnection system of FPGA is one of the most complex
aspects because wiring is global property of logic design.

DR.HBB . PLA - VLSI DESIGN 24

 Connection Paths
• Connection between logic elements requires complex paths since LE’s are
arranged in two dimensional structure as shown in below in previous slide.
• We therefore need to make connections not just between LEs and wires but
also between the wire themselves.
• Wires are typically organized in wiring channels or routing channels
which runs horizontally and vertically throughout the chip.
• Each channel contains several wires ; human designer or program chooses
which wire will carry signal in each channel.
• Connection must be made between wires to carry signal from one point to
another.

• Ex: Net in figure starts from output of LE in upper-right-hand corner

travels down vertical channel 5 until it reaches horizontal channel 2, then
moves down vertical channel 3 to horizontal channel 3, then it uses
vertical channel 1 to reach the input of LE at Lower-left-corner.

DR.HBB . PLA - VLSI DESIGN 25

 Segmented wiring
top signal of length 1 goes to next
LE,
the second signal goes to second
LE and so on.
This organization is Known as
segment wiring structure.

FPGA channel must provide wires of variety of lengths for designer to make all
the required connection between logic elements.
Since LE’s are organized in regular array, we can arrange wires going from one
LE to another.
Figure above shows connections of varying length as measured in unit LE’s:

DR.HBB . PLA - VLSI DESIGN 26

 FPGA Configuration.
• All FPGA’s need to be programmed or configured.
• Three major circuit technologies for configuring an
FPGA:
a) SRAM
b) Antifuse
c) flash.
• No matter which circuits we use, all the major
elements of FPGA - Logic elements, interconnect
and i/O pins needs to be confugured.

DR.HBB . PLA - VLSI DESIGN 27

 4.8 Physical Design of FPGA
Configuring an FPGA means placing the logic into LE in fabric and choose
paths .Delay and Energy consumption of LE plays a major role.
Physical design is divided into two major phases.
• Placement: it determines the position of logic elements and I/O pads.
• Routing: selects the paths for connection between logic elements and I/O
pads.
• These two phases interact – one placement of the logic may not be
routable whereas a different placement of the same logic can be routed.
But this division allows us to make physical design problem for tractable.
• We use several different metrics to judge the quality of a Placement or
Routing.

DR.HBB . PLA - VLSI DESIGN 28

• Size matters as we are concerned about whether we can fit complete
design on to the chip.
• In FPGA, size is closely tied with routing.The number of logic elements
required is determined by logic synthesis. If we cannot find legal routing
for given placement, we may need to change placement.
• Delay is also critical measure in most design. A long delay is not critical,
whereas a relatively short delay path that is critical must be carefully
considered.
• Detailed delay characteristics are somewhat expensive to calculate, so
tools are used for the same.

DR.HBB . PLA - VLSI DESIGN 29

 Placement
• The separation of placement and routing raises an important
problem: how to judge the quality of placement?
• We cannot judge the placement quality by 2 measures ( area
and delay).
• We cannot afford to execute a complete routing for every
placement to judge its quality:
• There fore, we need some metric which estimates the quality
of routing.
• Different algorithms use different metrics, but few simple
metrics suggests important properties of placement
algorithms.

DR.HBB . PLA - VLSI DESIGN 30

 Two types of placements
•One way to judge the area of layout before
routing is to measure total distance between
interconnection.
•Of course, we can’t measure total wire length
without routing the wires, but we can estimate
length of a wire by measuring distance between
pins it connects.
When straight lines between connected pins are
Longer rat’s nest Shorter rats nest plotted ,results is known as rat’s nest plot.
interconnections interconnections Larger connections means larger layouts.

SEVERAL WAYS TO MEASURE DISTANCE

Euclidean Manhattan distance,

distance is the also known as half
direct line perimeter
between the two.
DR.HBB . PLA - VLSI DESIGN 31
 Clustering Vs Partitioning
Many algorithms for there for partitioning
Bottom up
These methods are generally referred as Top Down
clustering methods. These cluster Top Down methods divide nodes into
groups that are than further divided.
together nodes to create partitions.
These methods are known as
Fig 4-44 pp-289 partitioning methods.
• Fig 4-45 pp290

DR.HBB . PLA - VLSI DESIGN 32

 Placement by clustering .
• Page 292 second pyara

DR.HBB . PLA - VLSI DESIGN 33

 Placement by partitioning
Partitioning process for mini cut bisecting
criterion is as shown. • 4-46 pp291
Here nodes are components & edges are
connections b/w components.
Goal : to separate the graph nodes into 2
partition with nearly equal nodes with
minimum edges.
In fig ,we can see 5 wires crossing partition
boundary.
When we swapping ,2 nodes reduces the net
cut count to one. Thus a significant
reduction.

DR.HBB . PLA - VLSI DESIGN 34

 Routing
• Routing selects paths for connections that must be made
between logic elements and I/O pads.
• In an FPGA, the interconnection resources are predetermined
by the architecture of the FPGA fabric.
• A connection must be made by finding sequence of routing
resources, all of which unused and which share connections
such that continuous path can be made from source to sink.
Routing is generally divided into two phases:
• Global Routing selects general path through the chip but does
not determine exact wire segments to be used.
• Detailed Routing selects the exact set of wires to be used for
each connections.

DR.HBB . PLA - VLSI DESIGN 35

 Costs in routing
Routing has two major cost metrics:
wire length
Delay.
Wire length approximates utilization of routing resources. We
may not use more routing resorces for wires and
Delay may be measured by looking at the delay on paths with
largest number of levels of logic
or
by looking to nets whose delay is close to maximum allowed
value .

DR.HBB . PLA - VLSI DESIGN 36

 Global routing
• The principal job during global routing of FPGAs is to balance the
requirements of various nets.
• Nets are routed one at a time, so the order in which nets are routed affects
final result.
• Net may have one of the two problems:
1) it may not be routable because there is no room available to
make connection or
2) it may take a path that incurs too much delay.
• These problems are harder to solve in FPGAs than in custom chip designs
because routing resources are pre determined .
• Connections must be composed of re-designed paths that may include
larger wire segments.
• Most FPGA have diff categories of wiring ,each with very diff CH .

DR.HBB . PLA - VLSI DESIGN 37

 Wire ordering
• Many ways have developed to determine the order
in which wires are routed.
• A good heuristic for initial ordering is to route most
delay critical nets first:
• one may also want to start with large fanout nets
since they consume many routing resources.
• In general , a wire may be routed more than once
before it finds its final route. Ripup and reroute is
one simple strategy for choosing the order in which
to route nets.

DR.HBB . PLA - VLSI DESIGN 38