Introduction to
CMOS VLSI
Design
Lecture 1:
Circuits & Layout
Manoel E. de Lima – CIn – UFPE
David Harris
Harvey Mudd College
Spring 2004
Outline
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
1: Circuits & Layout CMOS VLSI Design Slide 2
CMOS Gate Design
Activity:
– Sketch a 4-input CMOS NAND gate
1: Circuits & Layout CMOS VLSI Design Slide 3
CMOS Gate Design
Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
1: Circuits & Layout CMOS VLSI Design Slide 4
Complementary CMOS
Complementary CMOS logic gates
– nMOS pull-down network pMOS
– pMOS pull-up network pull-up
network
inputs
output
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
1: Circuits & Layout CMOS VLSI Design Slide 5
Series and Parallel
nMOS: 1 = ON g1
a
0
a
0
a
1
a
1
a
pMOS: 0 = ON
g2
b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON
Series: both must be ON a a a a a
Parallel: either can be ON g1
g2
0 0 1 1
0 1 0 1
b b b b b
(b) ON OFF OFF OFF
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
1: Circuits & Layout CMOS VLSI Design Slide 6
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Circuits & Layout CMOS VLSI Design Slide 7
Compound Gates
Compound gates can do any inverting function
Ex: A.B+C.D nMOS
CD
AB 00 01 11 10
00 1 1 0 1
01 1 1 0 1
pMOS
11 0 0 0 0
10 1 1 0 1
nMOS+pMOS
1: Circuits & Layout CMOS VLSI Design Slide 8
Example: O3AI
Y = (A+B+C).D
Vcc
1: Circuits & Layout CMOS VLSI Design Slide 9
Signal Strength
Strength of signal
– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
– But degraded or weak 1
pMOS pass strong 1
– But degraded or weak 0
Thus nMOS are best for pull-down network
1: Circuits & Layout CMOS VLSI Design Slide 10
Pass Transistors
Transistors can be used as switches
s d
s d
1: Circuits & Layout CMOS VLSI Design Slide 11
Pass Transistors
Transistors can be used as switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1
g g=0 Input Output
g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
1: Circuits & Layout CMOS VLSI Design Slide 12
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
1: Circuits & Layout CMOS VLSI Design Slide 13
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
1: Circuits & Layout CMOS VLSI Design Slide 14
Tristates
Tristate buffer produces Z when not enabled
EN
EN A Y
0 0 A Y
0 1
1 0
EN
1 1
A Y
EN
1: Circuits & Layout CMOS VLSI Design Slide 15
Tristates
Tristate buffer produces Z when not enabled
EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y
EN
1: Circuits & Layout CMOS VLSI Design Slide 16
Nonrestoring Tristate
Transmission gate acts as tristate buffer
– Only two transistors\
• Noise on A is passed on to Y
EN
A Y
EN
1: Circuits & Layout CMOS VLSI Design Slide 17
Tristate Inverter
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
EN
Y
EN
1: Circuits & Layout CMOS VLSI Design Slide 18
Tristate Inverter
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
1: Circuits & Layout CMOS VLSI Design Slide 19
Multiplexers
2:1 multiplexer chooses between two inputs
S
S D1 D0 Y
0 X 0 D0 0
0 X 1
Y
D1 1
1 0 X
1 1 X
1: Circuits & Layout CMOS VLSI Design Slide 20
Multiplexers
2:1 multiplexer chooses between two inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
1: Circuits & Layout CMOS VLSI Design Slide 21
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)
How many transistors are needed?
1: Circuits & Layout CMOS VLSI Design Slide 22
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)
How many transistors are needed?
20
1: Circuits & Layout CMOS VLSI Design Slide 23
Inverting Mux
Inverting multiplexer
– Pair of tristate inverters
– Essentially the same thing
Noninverting multiplexer adds an inverter
1: Circuits & Layout CMOS VLSI Design Slide 24
Transmission Gate Mux
Two transmission gates
– Only 4 transistors
S
D0
S Y
D1
1: Circuits & Layout CMOS VLSI Design Slide 25
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
1: Circuits & Layout CMOS VLSI Design Slide 26
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
1: Circuits & Layout CMOS VLSI Design Slide 27
D Latch
When CLK = 1, latch is transparent
– D flows through to Q like a buffer
When CLK = 0, the latch is opaque
– Q holds its old value independent of D
Transparent latch or level-sensitive latch
CLK CLK
D
Latch
D Q
Q
1: Circuits & Layout CMOS VLSI Design Slide 28
D Latch Design
Multiplexer chooses D or old Q
1: Circuits & Layout CMOS VLSI Design Slide 29
D Latch Operation
1: Circuits & Layout CMOS VLSI Design Slide 30
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
Positive edge-triggered flip-flop, master-slave flip-
flop
CLK
CLK
D
Flop
D Q
Q
1: Circuits & Layout CMOS VLSI Design Slide 31
D Flip-flop Design
Built from master and slave D latches
Master Slave
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
1: Circuits & Layout CMOS VLSI Design Slide 32
D Flip-flop Operation
Master on
Slave off
Master of
Slave on
1: Circuits & Layout CMOS VLSI Design Slide 33
Race Condition
Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
CLK1 CLK2 CLK2
Q1 Q1
Flop
Flop
D Q2
Q2
1: Circuits & Layout CMOS VLSI Design Slide 34
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
– Industry manages skew more carefully instead
2 1
QM
D Q
2 2 1 1
2 1
1
2
1: Circuits & Layout CMOS VLSI Design Slide 35
