Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network
❑ And, pMOS are best for pull-up network
1: Circuits & Layout CMOS VLSI Design 4th Ed. 1
Pass Transistors
❑ Transistors can be used as switches
1: Circuits & Layout CMOS VLSI Design 4th Ed. 2
CMOS VLSI Design 4th Ed.
CMOS VLSI Design 4th Ed.
CMOS VLSI Design 4th Ed. 5
Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well
1: Circuits & Layout CMOS VLSI Design 4th Ed. 6
CMOS VLSI Design 4th Ed. 7
Tristates
❑ Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 8
Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
1: Circuits & Layout CMOS VLSI Design 4th Ed. 9
Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
1: Circuits & Layout CMOS VLSI Design 4th Ed. 10
Multiplexers
❑ 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 11
Gate-Level Mux Design
❑
❑ How many transistors are needed? = 20 (2 for S_bar, 6*2
for AND,finally 6 for OR)
D1
S Y
D0
these are transistor
count
D1 4 2
S 4 2 Y
D0 4 2
2
CMOS VLSI Design 4th Ed.
Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors << 20 in prev slide
1: Circuits & Layout CMOS VLSI Design 4th Ed. 13
Logic Gate using TG
=A
GND
=A
1: Circuits & Layout CMOS VLSI Design 4th Ed. 14
Logic Gate using TG
=A
5V
=A
1: Circuits & Layout CMOS VLSI Design 4th Ed. 15
Logic Gate using TG
=A
B’
=A
1: Circuits & Layout CMOS VLSI Design 4th Ed. 16
2:1 MUX using TG
A0
A1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 17
Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter
1: Circuits & Layout CMOS VLSI Design 4th Ed. 18
4:1 Multiplexer
1: Circuits & Layout CMOS VLSI Design 4th Ed. 19
4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates
1: Circuits & Layout CMOS VLSI Design 4th Ed. 20
20
D Latch
❑ When CLK = 1, latch is transparent
– D flows through to Q like a buffer
❑ When CLK = 0, the latch is opaque
– Q holds its old value independent of D
❑ a.k.a. transparent latch or level-sensitive latch
1: Circuits & Layout CMOS VLSI Design 4th Ed. 21
D Latch Design using MUX
❑ Multiplexer chooses D or old Q
1: Circuits & Layout CMOS VLSI Design 4th Ed. 22
D Latch Design using
Transmission gate
1: Circuits & Layout CMOS VLSI Design 4th Ed. 23
D Latch Operation
1: Circuits & Layout CMOS VLSI Design 4th Ed. 24
D Flip-flop
❑ When CLK rises, D is copied to Q
❑ At all other times, Q holds its value
❑ a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
1: Circuits & Layout CMOS VLSI Design 4th Ed. 25
D Flip-flop Design
❑ Built from master and slave D latches
1: Circuits & Layout CMOS VLSI Design 4th Ed. 26
D Flip-flop Operation
When CLK=0: Q retains
it’s old value and
QM_bar = D_bar is
being continuously set
unless CLK=1
When CLK=1: D gets
disconnected from QM_bar
line hence QM_bar=D_bar is
sent directly to Inveter to Q
point.
Also,after CLK=1 is set,Q can’t
follow D anymore as D is
isolated from QM_bar
1: Circuits & Layout CMOS VLSI Design 4th Ed. 27
