2/1/2025

CpE 474:

ASIC Design
Introduction
Instructor: Dr. Mahmoud Bennaser

Computer Engineering
College of Engineering & Petroleum
Kuwait University
CMOS VLSI Design 4th Ed. 1

Welcome to CpE 474

 Instructor: Dr. Mahmoud A. Bennaser
 Office: Building ENG-S, 3rd floor Room C2-068
 Office Phone: 2498-5039
 Office Hours:
– Sunday, Tuesday & Thursday 10:00 – 11:00 AM

 Course Web Page: http://www.moodle.ku.edu.kw

 Email: [email protected]

CMOS VLSI Design 4th Ed. 2

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Grading Policy
 Homework’s 5%
 Participation 5%
 Quizzes 10%
 Project 20%
 Midterm Exam I 15%
 Midterm Exam II 15%
 Final Exam 30%

CMOS VLSI Design 4th Ed. 3

Late Policy, Attendance, & Makeup

 Homework is due at the beginning of class time

 Student with more than 6 absents will receive an FA grade

 No makeup exam will be given for missing exam or quiz

 Exams:
– Final Exam: Monday May 26, 11:00–1:00 PM

CMOS VLSI Design 4th Ed. 4

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Which Books will be Used?

 Digital Integrated Circuits, Jan M. Rabaey,
Anantha P. Chandrakasan, Borivoje Nikolic,
Pearson Education,Prentice Hall, 2nd Edition, 2003,
ISBN 0130909963.

 CMOS VLSI Design: A Circuits and Systems

Perspective, 4th Edition, Neil Weste, David Harris,
Addison Wesley, 2010, ISBN: 0321547748.

CMOS VLSI Design 4th Ed. 5

Application-Specific Integrated Circuit (ASIC)

 Developed for a specific application

 Not “general purpose”

CMOS VLSI Design 4th Ed. 6

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Progress of State of the Art

CMOS VLSI Design 4th Ed. 7

Moore’s Law (Gordon Moore –1965)

 Moore's law is the observation that the number of

transistors in a dense integrated circuits doubles
approximately every two years.

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System-on-Chip (SoC)
 An ASIC that packages basic computing components into
a single chip.
 A SoC has most of the components to power a computer.

CMOS VLSI Design 4th Ed. 9

Advantages of SoC
 Higher performance benefiting from:
– Less propagation delay since internal wires are shorter;
– Less gate delay as internal transistors have lower electrical impedance;

 Power efficiency benefiting from:

– Lower voltage required compared with external chip voltage;
– Less capacitance;
 Lighter footprint:
– Device size and weight is reduced;

 Higher reliability:
– All encapsulated in a single chip package, less interference from the
external world;
 Low cost:
– Cost per unit is reduced since a single chip design can be fabricated in
a large volumes.

CMOS VLSI Design 4th Ed. 10

10

Gate Oops pica's

5
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Limitations of SoC
 Less flexibility
– Unlike a PC or a laptop, which allows you to upgrade a
single component, such as RAM or graphic card, a SoC
cannot be easily upgraded after manufacture;
 Application Specific
– Most SoCs are specified to particular applications thus they
are not easily adapted to other applications.
 Complexity
– A SoC design usually requires advanced skills compared
with board-level development.

CMOS VLSI Design 4th Ed. 11

11

µg
of
Introduction
 Integrated Circuits (IC’s): many transistors on one chip.

 Very Large Scale Integration (VLSI)

 Complementary Metal Oxide Semiconductor (CMOS)

5
– Fast, cheap, low power transistors
ri  Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors 8512105
I
– Transistor layout and fabrication
mmI
iii
 Rest of the course: How to build a good CMOS chip

CMOS VLSI Design 4th Ed. 12

12

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Silicon Lattice
 Transistors are built on a silicon substrate
at  Forms crystal lattice with bonds to four neighbors
a
a
Si Si
ii
Si
48
Si Si Si
a
Si Si Si

CMOS VLSI Design 4th Ed. 13

13

Dopants
y  Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
e
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

i
Si

Si
Si

O
+
As
-
Si

Si
Si

Si
8B
III
Si
+

-
Si

Si

Si Si Si Si Si Si

CMOS VLSI Design 4th Ed.

jmjj.IE 14

14 IS
charging
48 7
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p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode. It
Feeds
o.gov
 Current flows only in one direction
gfold
p-type n-type
É diode
anode cathode

CMOS VLSI Design 4th Ed. 15

15

Asa o nMOS Transistor

 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors

II
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)

g
capacitor

want

CMOS VLSI Design 4th Ed. 16

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nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source o Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

CMOS VLSI Design 4th Ed. 17

17

nMOS Operation Cont.

 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor

E
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

process
ofI
CMOS VLSI Design 4th Ed. 18

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pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior

CMOS VLSI Design 4th Ed. 19

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Power Supply Voltage

 GND = 0V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
his
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
15Eur
voltag

saltines
at
CMOS VLSI Design 4th Ed. 20

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Transistors as Switches
 We can view MOS transistors as electrically controlled
switches
 Voltage at gate controls path from source to drain
g=0 g=1

950 shift
d d d
OFF

0
nMOS g ON
s
OPEN s s

d d d

pMOS g OFF
ON
puppie
s s shof.ee s

0: Introduction CMOS VLSI Design 4th Ed. 21

21

CMOS Inverter

A Y
ITS
0 1
1 0 OFF
ON
0
1

gatelevel off ON
OFF inventory

A Y transester
o I never
0
0: Introduction CMOS VLSI Design 4th Ed. 22

22
pull Down
grounds

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ATB
ATB said
of w
f µ
ps
CMOS NAND Gate
Katel case 5
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON foment
0 1 1
1 Y
1
0 22 4
1 0 1
A ON
OFF
1 1 0 0
1
1
0 series
Nand
B OFF
ON
ON
OFF

s nor
L 0: Introduction CMOS VLSI Design 4th Ed. 23

23

is
CMOS NOR Gate
A B Y
Ifr
0
0 0 1 A ONseries
0 1 0
0
1 0 i
0 B ON
1 1 0
0 Y
OFF OFF
parrotted

0: Introduction CMOS VLSI Design 4th Ed. 24

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SIX
compoundgate and
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universal
150 in
5
3-input NAND Gate The
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction CMOS VLSI Design 4th Ed. 25

25 T

MT
CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

0: Introduction CMOS VLSI Design 4th Ed. 26

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for 1,51318b
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of  Typically use p-type substrate for nMOS transistors

f
 Requires n-well for body of pMOS transistors

p
int

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a

0: Introduction CMOS VLSI Design 4th Ed. 27

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I nm

Inverter Mask Set

 Transistors and wires are defined by masks
 Cross-section taken along dashed line

case.ae
Is'tt A

fourput
GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

0: Introduction CMOS VLSI Design 4th Ed. 28

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Detailed Mask Views

 Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal

0: Introduction CMOS VLSI Design 4th Ed. 29

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Fabrication
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

0: Introduction CMOS VLSI Design 4th Ed. 30

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553 Fabrication Steps

 Start with blank wafer
 Build inverter from the bottom up t
 First step will be to form the n-well
I wt

– Cover wafer with protective layer of SiO2 (oxide)

– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 31

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Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist
a p  Spin on photoresist
as
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
M
sm
www.T.im
Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 33

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Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 34

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Etch
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 35

35

Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 36

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n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
O Egon
 Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

0: Introduction CMOS VLSI Design 4th Ed. 37

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Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well O
 Subsequent steps involve similar series of steps
Hf

n well
p substrate

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Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

0: Introduction CMOS VLSI Design 4th Ed. 39

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Polysilicon Patterning
 Use same lithography process to pattern polysilicon

0: Introduction CMOS VLSI Design 4th Ed. 40

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Self-Aligned Process
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact

0: Introduction CMOS VLSI Design 4th Ed. 41

41

N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

0: Introduction CMOS VLSI Design 4th Ed. 42

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N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

Em

0: Introduction CMOS VLSI Design 4th Ed.

JAP
43

43

N-diffusion cont.
 Strip off oxide to complete patterning step

0: Introduction CMOS VLSI Design 4th Ed. 44

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P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

0: Introduction CMOS VLSI Design 4th Ed. 45

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Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

0: Introduction CMOS VLSI Design 4th Ed. 46

E
46

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Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

M e ta l

MI
v
0: Introduction CMOS VLSI Design 4th Ed. 47

47

Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain DUE
– Set by minimum width of polysilicon

o
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of  = f/2
– E.g.  = 0.3 m in 0.6 m process

0: Introduction CMOS VLSI Design 4th Ed. 48

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Nmos
PMOS
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Simplified Design Rules

 Conservative rules to get you started inverted

p
devil
so

profit
affect
µ
so
0: Introduction CMOS VLSI Design 4th Ed. 49
inputy

49

Inverter Layout
 Transistor dimensions specified as Width / Length
– Minimum size is 4 / 2sometimes called 1 unit
– In f = 0.6 m process, this is 1.2 m wide, 0.6 m
long

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Summary
 MOS transistors are stacks of gate, oxide, silicon
 Act as electrically controlled switches
 Build logic gates out of switches
 Draw masks to specify layout of transistors

 Now you know everything necessary to start

designing schematics and layout for a simple chip!

0: Introduction CMOS VLSI Design 4th Ed. 51

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