Explana'on of Exercise 5: Cache
Uploaded by
opwekkiExplana'on of Exercise 5: Cache
Uploaded by
opwekkiExplana'on
of Exercise 5
Cache
2
Exercise
5
• A
processor
has
an
8-‐bit
physical
address
space
and
a
physically
addressed
k-‐way
set-‐
associa've
cache.
Memory
is
byte-‐addressable.
The
cache
uses
LRU
replacement.
– The
processor
supplies
the
following
sequence
of
addresses
to
the
cache.
The
cache
is
ini'ally
empty.
The
hit/miss
outcome
of
each
access
is
shown.
Address
Outcome
0
Miss
2
Hit
4
Miss
128
Miss
0
Hit
128
Hit
64
Miss
4
Hit
0
Miss
32
Miss
64
Hit
– Determine
the
block
size,
associa'vity,
and
size
of
the
cache
(a)
Determine
the
block
size
(b)
Determine
the
associa'vity
or
value
k
• Value
k
is
also
number
of
lines
per
set
• k
is
at
least
2
since
the
cache
is
k-‐way
associa've
cache.
k=1
implies
that
the
cache
is
a
direct
mapped
cache.
• The
following
few
slides
show
analysis
of
each
cache
outcome
to
get
to
the
value.
Cache
Memory
Line
content
Address
content
0
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
3(0000_0011)
byte3
:
4(0000_0100)
byte4
5(0000_0101)
byte5
6(0000_0110)
byte6
7(0000_0111)
byte7
Ini'ally,
the
:
:
cache
is
:
:
empty.
64(0100_0000)
byte64
:
:
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
3(0000_0011)
byte3
:
4(0000_0100)
byte4
5(0000_0101)
byte5
6(0000_0110)
byte6
7(0000_0111)
byte7
0
Miss
,
then
block
0
:
:
will
go
to
:
:
line
0
64(0100_0000)
byte64
:
:
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
3(0000_0011)
byte3
:
4(0000_0100)
byte4
5(0000_0101)
byte5
6(0000_0110)
byte6
7(0000_0111)
byte7
Then,
2
hit
because
:
:
byte2
is
:
:
there
64(0100_0000)
byte64
:
:
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
5(0000_0101)
byte5
6(0000_0110)
byte6
7(0000_0111)
byte7
4
Miss
,
then
block
1
:
:
will
go
to
:
:
some
line
64(0100_0000)
byte64
:
:
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
5(0000_0101)
byte5
6(0000_0110)
byte6
128
Miss
,
7(0000_0111)
byte7
then
the
:
:
correspondi
:
:
ng
block
will
go
to
some
64(0100_0000)
byte64
line
:
:
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
0
hit,
which
means
:
:
128
did
not
overwrite
line0.
:
:
128
goes
to
other
64(0100_0000)
byte64
line
but
likely
same
:
:
set
with
line
0
because
bit2,
bit3…
:
:
represent
set
128(1000_0000)
byte128
number
but
we
:
:
don’t
know
total
bits
yet.
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
Maybe
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
0
hit,
which
:
:
means
128
did
64(0100_0000)
byte64
not
overwrite
:
:
line0.
128
goes
to
other
line
but
:
:
likely
same
set
128(1000_0000)
byte128
with
line
0
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
:
:
64(0100_0000)
byte64
:
:
128
hit
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
:
:
64(0100_0000)
byte64
:
:
0
hit
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
:
:
64(0100_0000)
byte64
:
:
0
hit
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
64
miss
then
the
:
:
corresponding
64(0100_0000)
byte64
block
will
move
:
:
to
some
line.
Its
set
maybe
Set0,
:
:
maybe
Set8
128(1000_0000)
byte128
(1000)
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte0
byte1
byte2
byte3
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
but
we
don’t
5(0000_0101)
byte5
know
how
many
6(0000_0110)
byte6
lines
per
set
7(0000_0111)
byte7
:
:
:
:
64(0100_0000)
byte64
:
:
4
hit
:
:
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte64
byte65
byte66
byte67
0
(0000_0000)
byte0
1
byte128
byte129
byte130
byte131
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
now
we
know
Set0
has
2lines
only
5(0000_0101)
byte5
because
data
of
block0
need
to
be
evicted
6(0000_0110)
byte6
to
give
way
to
data
of
address64
and
the
7(0000_0111)
byte7
following
three
bytes;
Set0
does
not
have
3rd
empty
line
to
hold
them.
:
:
K=2
as
each
set
has
2
lines.
:
:
0
miss!
64(0100_0000)
byte64
That
means
just
:
:
now
data
of
64
has
overwriaen
:
:
line0!!
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
Cache
Memory
Line
content
Address
content
0
byte64
byte65
byte66
byte67
0
(0000_0000)
byte0
1
byte0
byte1
byte2
byte3
1
(0000_0001)
byte1
:
2(0000_0010)
byte2
:
Byte4
byte5
byte6
byte7
3(0000_0011)
byte3
:
4(0000_0100)
byte4
Set
0,
now
we
know
Set0
has
2lines
only
5(0000_0101)
byte5
because
data
of
block0
need
to
be
evicted
6(0000_0110)
byte6
to
give
way
to
data
of
address64
and
the
7(0000_0111)
byte7
following
three
bytes;
Set0
does
not
have
3rd
empty
line
to
hold
them.
:
:
K=2
as
each
set
has
2
lines.
:
:
0
miss!
64(0100_0000)
byte64
Then,
block0
:
:
goes
to
Line1,
instead
of
line0,
:
:
due
to
LRU
algo.
128(1000_0000)
byte128
:
:
255(1111_1111)
byte255
(c)
Determine
the
cache
size
Cache
Memory
Address
content
Line
content
byte64
byte65
byte66
byte67
0
(0000_0000)
byte0
0
1
(0000_0001)
byte1
1
byte0
byte1
byte2
byte3
2(0000_0010)
byte2
:
3(0000_0011)
byte3
:
Byte4
byte5
byte6
byte7
4(0000_0100)
byte4
:
5(0000_0101)
byte5
Set0:
2
lines
per
set
6(0000_0110)
byte6
7(0000_0111)
byte7
:
:
32 (0010_0000) miss: 32(0010_0000) :
IT may belong to : :
Set0 or Set8. 64(0100_0000) byte64
Assuming it is : :
Set0, data32 : :
will go to line0 128(1000_0000) byte128
due to LRU algo.
: :
Cache Memory
Address content
Line content
byte64 byte65 byte66 byte67 0 (0000_0000) byte0
0
1 (0000_0001) byte1
1 byte0 byte1 byte2 byte3
2(0000_0010) byte2
:
3(0000_0011) byte3
: Byte4 byte5 byte6 byte7
4(0000_0100) byte4
:
5(0000_0101) byte5
Set0: 2 lines per set Set8 6(0000_0110) byte6
7(0000_0111) byte7
: :
32(0010_0000) :
But 64 hit!! : :
That means data 64(0100_0000) byte64
32 will go to
Set8, which : :
means set bits : :
consist of 4-‐bit
128(1000_0000) byte128
: :
con'nued
• So, if set bits consists of 4-‐bit, the cache
consist of 24 or 16 sets.
• Cache size = 16 sets x 2 lines per set x 4 bytes per line
= 128 Bytes
You might also like
- Computer Organization Homework05: RISC-V EditionNo ratings yetComputer Organization Homework05: RISC-V Edition10 pages
- Edgar David Hernández Medina T00054326: 54-Bit 5-Bit 5-BitNo ratings yetEdgar David Hernández Medina T00054326: 54-Bit 5-Bit 5-Bit2 pages
- Chapter 6 Sample Problems: Problem No.08No ratings yetChapter 6 Sample Problems: Problem No.082 pages
- Review Problems For Exam 1: MIPS (Instruction Count) / (Execution Time X 10No ratings yetReview Problems For Exam 1: MIPS (Instruction Count) / (Execution Time X 106 pages
- Lab 11 - Activity - Understanding Cache & Exploring Direct Mapped Caches - CS 261 Spring 2025No ratings yetLab 11 - Activity - Understanding Cache & Exploring Direct Mapped Caches - CS 261 Spring 20252 pages
- NAND Dump Analysis, Bit Errors Fixing With ECC, UBI Image Analysis, and Firmware Extraction DemystifiedNo ratings yetNAND Dump Analysis, Bit Errors Fixing With ECC, UBI Image Analysis, and Firmware Extraction Demystified43 pages
- More Pipelining Topics!: Notes Originally by Matt JohnsonNo ratings yetMore Pipelining Topics!: Notes Originally by Matt Johnson3 pages
- Core Security Introduction To Software Vulnerability ExploitationNo ratings yetCore Security Introduction To Software Vulnerability Exploitation74 pages
- Princes Nourah University Cs323-Computer Architecture 1 Semester/ 1435No ratings yetPrinces Nourah University Cs323-Computer Architecture 1 Semester/ 14356 pages
- Memory Hierarchy Assignment: 1. Exercises A.8, A.9 From Hennessy and Patterson 5th EdNo ratings yetMemory Hierarchy Assignment: 1. Exercises A.8, A.9 From Hennessy and Patterson 5th Ed8 pages
- CS 211: Computer Architecture, Summer 2021 Programming Assignment 3: Cache Simulator (100 Points)No ratings yetCS 211: Computer Architecture, Summer 2021 Programming Assignment 3: Cache Simulator (100 Points)4 pages
- Universidad de Guadalajara Centro Universitario de Ciencias Exactas e IngenieríasNo ratings yetUniversidad de Guadalajara Centro Universitario de Ciencias Exactas e Ingenierías11 pages
- CS 356 Cache Exercises: Redekopp Name: - ScoreNo ratings yetCS 356 Cache Exercises: Redekopp Name: - Score4 pages
- Numerical Methods SMJM 3053: Nurhazimah Nazmi, PHD 5.33.01 Nurhazimah@Utm - MyNo ratings yetNumerical Methods SMJM 3053: Nurhazimah Nazmi, PHD 5.33.01 Nurhazimah@Utm - My30 pages
- Pre-Requisite For SAP Solution Manager: Java RequirementsNo ratings yetPre-Requisite For SAP Solution Manager: Java Requirements3 pages
- 5 in 1 V.35 Assembly and Pinouts: Document ID: 46803No ratings yet5 in 1 V.35 Assembly and Pinouts: Document ID: 468035 pages
- In Ps5 0033e 02 0 Ps5 Power Source Information 1No ratings yetIn Ps5 0033e 02 0 Ps5 Power Source Information 115 pages
- Dokumen - Tips Infobip HTTP API and SMPP Specification 5684789a636cbNo ratings yetDokumen - Tips Infobip HTTP API and SMPP Specification 5684789a636cb35 pages
- Storage Virtualization in Cloud Computing Types and BenefitsNo ratings yetStorage Virtualization in Cloud Computing Types and Benefits30 pages
- The Avantext Techpubs CD User Guide: Avantext Inc 340 Morgantown RD Reading, Pa 19611No ratings yetThe Avantext Techpubs CD User Guide: Avantext Inc 340 Morgantown RD Reading, Pa 1961111 pages