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UNIVERSITY OF TECHNOLOGY, JAMAICA
ENGINEERING DEPARTMENT
BEng 2M/2C Electrical Technology
Lab #6: Basic Logic Gates and Combinational Circuits
Name: __________________________________
I.D. #:___________________________________
Group: __________________________________
Date of Submission: _______________________
Lab Instructor: ___________________________
Objective(s)
To investigate the behavior of the AND, OR and NOT gate.
To investigate combinational logic circuits and Boolean expression.
Apparatus
Digital Design Experimenter
7408 IC
7432 IC
7404 IC
Pre-Lab Assignment
1. What is the difference between the CMOS and TTL logic families?
[6 Marks]
Introduction
In general, logic circuits have one or more inputs and only one output. The circuits respond to
various input combinations, and a truth table shows the relationship between a circuits’ input
combination and its output.
The digital design experimenter is an instrument primarily used to construct and test digital
circuits. The basic digital design experiment consists of a breadboard, power supply, several
logic level switches and logic level indicators.
Procedure
Activity #1: The AND Logic Gate
Figure 6.1
1. Figure 6.1 shows the pin layout for the 7408 IC which contains four AND logic gates.
2. Connect Vcc to 5 volts and GND to ground of the power supply respectively.
3. Choose one of the AND gates. Connect the inputs A and B to separate logic switches and
the output Y, to a logic indicator.
4. Set inputs A and B to each set of logic levels listed in table 6.1 and record the output
level observed.
1
Logic Switches Output Logic
Level (0/1)
A B Y
0 0
0 1
1 0
1 1
Table 6.1
[1 Mark]
5. Disconnect input A from the toggle switch, and set input B to 1. Note the logic level
indicated by the LED monitor. Based on your observation, what logic level does the
unconnected input act like? ________.
[1 Mark]
Activity #2: The OR Logic Gate
Figure 6.2
1. Figure 6.2 shows the pin layout for the 7432 IC which contains four OR logic gates.
2. Connect Vcc to 5 volts and GND to ground of the power supply respectively.
3. Choose one of the OR gates. Connect the inputs A and B to separate logic switches and
the output Y, to a logic indicator.
4. Set inputs A and B to each set of logic levels listed in table 6.2 and record the output
level observed.
Logic Switches Output Logic
Level (0/1)
A B Y
0 0
0 1
1 0
1 1
Table 6.2
[1 Mark]
2
5. Disconnect one of the inputs, and set the remaining one to 0. Based on your
observation and knowledge of the OR operation, what level does the
unconnected input act like? ________.
[1 Mark]
Activity #3: The NOT Logic Gate
Figure 6.3
1. Figure 6.3 shows the pin layout for the 7404 IC which contains six NOT logic gates.
2. Connect Vcc to 5 volts and GND to ground of the power supply respectively.
3. Connect a logic level switch to input A and a logic level indicator to output Y.
4. Set inputs A and B to each set of logic levels listed in table 6.3 and record the output
level observed.
Logic Output Logic
Switches Level (0/1)
A Y
0
1
Table 6.3
[1 Mark]
Activity #4: Combinational Logic Circuit
A
B
Y
C
Figure 6.4
1. Construct the circuit of figure 6.4 using the 7408 IC and 7432 IC (make sure to connect
Vcc and GND to both ICs).
2. Connect toggle switches to inputs A, B and C and connect the output Q to a logic level
indicator.
3. For each combination in table 4. Observe the output state and record the state in table 6.4.
3
Logic Level Inputs Output Level
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 6.4
[2 Marks]
Questions
1. The output of an AND gate is __________ whenever any input is LOW.
[1 Mark]
2. The output of an OR gate is LOW only when __________________.
[1 Mark]
3. The output of an inverter is always ___________ the input.
[1 Mark]
4. To use a three-input AND gate as a two-input gate, one input should be connected to
[VCC, GND].
[1 Mark]
5. If an OR gate input were accidentally shorted to VCC, the output of the gate would always
be _________, no matter what level the other input might be.
[1 Mark]
6. Write the Boolean expression for the circuit of figure 6.4
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[2 Marks]
