International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 05 Issue: 05 | May-2018 www.irjet.net p-ISSN: 2395-0072

FPGA Implementation of Image Enhancement Using Verilog HDL

Mandeep Singh Narula1, Nishant Singla2
1Professor, Dept. of E.C.E., JIIT, Noida, India
2Student, Dept. of E.C.E., JIIT, Noida, India.
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Abstract - The demand of Image Processing methods 1. Improve the human interpretation and enhance the
traditionally implemented on a digital processing software pictorial visual information;
such as MATLAB is increasing widely to get high performance.
2. Modify information of image illustration so as to optimize
In this project we implemented four basic operations of it for data storage, transmission or different illustration for
Image Enhancement i.e. threshold, contrast, brightness, invert autonomous machine perception.
to manipulate the RGB values of every pixel of the image to
improve the human interpretation of image[1]. The main goal of any improvement methodology is simply
too acquire a a lot of appropriate result compared with the
To perform the above mentioned operations we have first as is from the purpose of read of a selected application.
implemented Image Enhancement on FPGA (Field
Programmable Gate Array) using Verilog HDL. Any image improvement procedures are often categorised
Implementation in HDL (Hardware Description Language) is into 2 approaches: spatial domain methods and frequency
quite different from implementation in MATLAB mainly domain methods. The spatial domain refers to the pixels
because of the parallel nature of the HDLs. The system is structure of the image plane itself and this sort of
implemented on FPGA[5], which is modern programmable improvement is predicated on direct manipulation of these
logic device, i.e. we can program almost any digital function in pixels of a picture. Frequency domain process techniques
it. area unit mistreatment mathematical transforms to induce
totally different enhancements. The Fourier remodel of a
Keywords - Verilog; FPGA,DE0 Nano; Image Enhancement picture is accepted for these functions[9].

I. INTRODUCTION Some of the best, yet useful, image process operations within
the spatial domain involves the adjustment of brightness,
There are many Hardware Description Languages (HDLs) distinction or colour a picture. A reason for manipulating
available to help the engineers describe the circuit both these attributes is to reduce the difficulties in image
logically and functionally so that they can simulate and acquisition and with image process we will increase the
properly calculate the performances with the help of general brightness of the item of interest and amplify the
personalized test environment and clock cycle. small residual variations in distinction across it. This image
process operations will reveal enough detail to permit
Since the HDL syntax is always related to a hardware correct interpretation. Some mainly used point operations
structure, the timing information of the potential hardware are: [2]
implementation is also available allowing specific speed
optimizations. Above all, with the use of HDLs it means that • modifying image brightness or contrast,
we can enjoy hardware portability and on-the-fly re- • applying arbitrary intensity transformations
programmability. But here the bigger challenge is to (“curves”),
implement the validated algorithms into a non-programming
language as hardware description languages are. Also, the • quantizing (or “posterizing”) images,
input and output RGB files need to be constructed accordingly • global thresholding,
to match the binary content permitted into the hardware
simulators[4]. • gamma correction,
• color transformations.

II. IMPLEMENTATION OF IMAGE ENHANCEMENT

METHODS USING VERILOG HDL
Fig - 1 : Block Diagram of the System
Point process operation is performed to reinforce a picture
Among all, the most interesting image processing approaches and details not clearly visible within the original image could
is the image enhancement. The importance for this domain is come into view upon application of the point operation. The
mainly for two application directions: aim of the paper is to explain some basic image enhancement
strategies employing a hardware description language,
Verilog.
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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 05 | May-2018 www.irjet.net p-ISSN: 2395-0072

The Verilog language has the power to browse or write files the hardware built along with the development board is
from a storage setting. This feature create it potential to explained in this section.
significantly style the test benches to browse the test
information from device, generate the stimulant signals to b. Terasic DE0-Nano FPGA Development Board:
the Verilog check module and write back the results to the
device. sadly, Verilog solely browse (and write) ASCII This Project uses a Terasic DE0-Nano FPGA Development
character files being unable to browse pictures in Board, it introduces a compact-sized FPGA development
commonplace formats like image or jpeg directly from disk platform suited for to a wide range of portable design
[6]. projects.

The project is implemented on FPGA using Verilog, which is The DE0-Nano features a powerful Altera Cyclone IV FPGA
Hardware Description Language. The code written in Verilog (with 22,320 logic elements), 32 MB of SDRAM, 2 Kb
describes the behaviour of the desired hardware. The code is EEPROM, and a 64 Mb serial configuration memory device.
taken by Altera’s synthesis tool (we use Altera’s toolchain For connecting to real-world sensors the DE0-Nano includes
because we have an Altera Cyclone IV FPGA) which ‘try’ to a National Semiconductor 8-channel 12-bit A/D converter,
find an implementation of the description of the code. and it also features an Analog Devices 13-bit, 3-axis
accelerometer device.
The word try is empathised as the tools, advance as they may
be, might not be able to find a correct implementation for The DE0-Nano board includes a built-in USB Blaster for FPGA
given description or might produce poor or overly complex programming, and the board can be powered either from this
implementation, thus it is our job as designer to write USB port or by an external power source. The board includes
synthesizable code. expansion headers that can be used to attach various Terasic
daughter cards or other devices, such as motors and
The main idea is to have a general view of the kind of circuit actuators. Inputs and outputs include 2 pushbuttons, 8 user
implementation will be derived by the tools and to logically LEDs and a set of 4 dip-switches.
partition the module in the code, it is easy to correctly
implement small module interconnected then a very big and The key feature of the board are listed below –
complex block.
• Featured device
RGB-files contain only information about RGB vector for each o Altera Cyclone IV EP4CE22F17C6N FPGA
pixel of the input image and does not contain information
about image dimensions or similar. The data from files was o 153 maximum FPGA I/O pins
applied as stimulus to the point operations blocks described • Configuration status and set-up elements
in Verilog language.
o On-board USB-Blaster circuit for programming
The result was obtained in another external file and we o Spansion EPCS64
create an application described in MATLAB to show the
modified output image and to compare with the original • Expansion header
input image. o Two 40-pin Headers (GPIOs) provide 72 I/O pins, 5V
Next, we describe the theory and implementation, using power pins, two 3.3V power pins and four ground pins
Verilog language, of most commonly used point operations • Memory devices
used for image enhancement[3]:
o 32MB SDRAM
A. Contrast manipulation o 2Kb I2C EEPROM
B. Brightness manipulation • General user input/output
C. Inverting images o 8 green LEDs
D. Threshold operation o 2 debounced pushbuttons
In view of above ideas, we have tried to best partition our o 4-position DIP switch
implementation, using many modules.
• G-Sensor
a. Hardware o ADI ADXL345, 3-axis accelerometer with high
resolution (13-bit)
The system is supposed to be implemented on a Terasic DE0-
Nano[8] FPGA development board. As the board does not • Clock system
have many peripherals we need to make our own expansion o On-board 50MHz clock oscillator
board to connect the FPGA to controller, VGA monitor . All
• Power Supply

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 05 | May-2018 www.irjet.net p-ISSN: 2395-0072

o USB Type mini-AB port (5V)

o DC 5V pin for each GPIO header (2 DC 5V pins)
o 2-pin external power header (3.6-5.7V)

c. Verilog HDL Hardware

The complete system is implemented in Verilog. As a

successful implementation in Verilog calls for good logical
partitioning of the circuit, various modules are created that
are interconnected to make the whole system.

Module Name: Contrast Operation: - This module changes

the contrast of the picture by setting the darkest pixel value
to black, the brightest value to white, and others to different
shades of gray which makes good use of the display and
enhances the visibility of features in the image[10].

Module Name: Invert Image: - This module inverts an

image by inverting the bits of the grayscale pixel value of an
image.

And, to change a coloured image into a grayscale one, the

RGB pixel values must be equalized and it is done by taking e
the average of the three color components[7].

Module Name: Threshold operation: - This module is used

Module Name: Brightness Operation: - This module to perform the threshold operation i.e. set the pixel above a
changes the brightness of the picture by adding or threshold value to 255 and below it to 0.
subtracting a fixed value to the pixel value. The purpose of
the below mentioned code is add and subtract a constant The threshold operation can be performed using below
value to the image pixel values mentioned Verilog testing code[9].

© 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1796
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 05 | May-2018 www.irjet.net p-ISSN: 2395-0072

Fig - 5 : Black & White result using threshold = 120

III. Advantages of FPGA V. REFERENCES
 Better performance than DSP’s [1] John C. Russ - “Image Processing Handbook (sixth
 Less Time to Market edition)”, CRC Press, pp. 270-331, 2011

 Low long-term Cost [2] Raman Maini, H. Aggarwal - “A Comprehensive

Review of Image enhancement Techniques”, Journal of
 More Reliability Computing, vol. 2, issue 3, ISSN 2151-9617, pp. 269-300,
 Long-term Maintenance 2010.

IV. RESULTS [3] Wilhelm Burger, Mark J. Burge - “Principles of Digital

Image Processing – Fundamental Techniques”,
The simulation results obtained after applying the operations Undergraduate Topics in Computer Science, DOI
described using Verilog HDL to an input image are shown 10.1007/978-1-84800-191-6_4, Springer- Verlag
here. London Limited, 2009.

[4] A. Zuloaga, J.L. Martin, U. Bidarte, J.A. Ezquerra -

“VHDL test bench for digital image processing systems
using a new image format”, ECSI, 2007
(http://mx.reocities.com/CapeCanaveral/8482/).

[5] Daggu Venkateshwar Rao, Shruti Patil, Naveen Anne

Babu and V. Muthukumar - “Implementation and
Evaluation of Image Processing Algorithms on
Reconfigurable Architecture using C-based Hardware
Fig - 2 : Verilog result for Invert Operation Descriptive Languages”, International Journal of
Theoretical and Applied Computer Sciences, Volume 1,
Number 1, pp. 9–34, 2006
(http://www.gbspublisher.com/ijtacs/1002.pdf).

[6] “Verilog HDL” by Samir Palnitkar, 2003, ISBN 0-13-

044911-3 [Publisher: Prentice Hall PTR]

[7] R. C. Gonzalez, R. E. Woods – “Digital Image

Processing”, Prentice Hall, ISBN 0-13-094659-8, pp. 1-
Fig - 3 : Verilog result for Contrast Operation using 142, 2002.
threshold = 90, valueToAdd = 10 and valueToSubtract = 15
[8] Bovik, A. (Ed.). (2000). Handbook of image and video
processing. Texas: Academic Press.

[9] Nick Efford - “Digital Image Processing – A Practical

Introduction Using Java”, pp. 103-132, 2000.

[10] Fisher, R., Perkins, S., Walker, A., & Wolfart, E.

(1996). Hypermedia image processing reference.
Chichester: John Wiley & Sons, Inc.

Fig - 4 : Verilog result for Brightness Operation using sign

= 0 and value = 60

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