78 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

1, JANUARY 2012

Addressing DC Component in PLL and Notch

Filter Algorithms
Masoud Karimi-Ghartemani, Senior Member, IEEE, S. Ali Khajehoddin, Member, IEEE,
Praveen K. Jain, Fellow, IEEE, Alireza Bakhshai, Senior Member, IEEE, and Mohsen Mojiri

Abstract—This paper presents a method for addressing the dc the system bandwidth and degrades the dynamic response [4].
component in the input signal of the phase-locked loop (PLL) and Complete removal of dc component in the phase-locked loop
notch filter algorithms applied to filtering and synchronization (PLL) systems has not been addressed in the literature so far.
applications. The dc component may be intrinsically present in the
input signal or may be generated due to temporary system faults or The dc component can be an intrinsic component of a signal
due to the structure and limitations of the measurement/conversion (e.g., the dc-link voltage in a single-phase rectifier that has
processes. Such a component creates low-frequency oscillations in a dc and a second-order harmonic), and can be generated by
the loop that cannot be removed using filters because such filters measurement devices (e.g., due to the saturation phenomenon
will significantly degrade the dynamic response of the system. The in a current transformer [5]), conversion processes (e.g., the A/D
proposed method is based on adding a new loop inside the PLL
structure. It is structurally simple and, unlike an existing method conversion for fixed-point DSP applications [6]), or when a fault
discussed in this paper, does not compromise the high-frequency occurs [7]. Therefore, it is necessary to remove any error that
filtering level of the concerned algorithm. The method is formulated such a component may cause.
for three-phase and single-phase systems, its design aspects are The enhanced phase-locked loop (EPLL)—in conjunction
discussed, and simulations/experimental results are presented. with its three-phase extensions—has been introduced and ex-
Index Terms—Adaptive notch filter (ANF), dc component, dc tensively studied for filtering [8], frequency estimation [9], har-
offset, enhanced phase-locked loop (EPLL), notch filter (NF), or- monic estimation [10], and synchronization [2], [11]. The EPLL
thogonal signal generator (OSG), phase-locked loop (PLL), second- resolves the problem of double-frequency oscillation in conven-
order generalized integrator frequency-locked loop (SOGI-FLL),
synchronous reference-frame phase-locked loop (SRF-PLL). tional PLLs. However, the presence of a dc component in the
input signal of the EPLL causes an error in the loop at the
fundamental frequency that is hard to filter.
The second-order generalized integrator (SOGI) has been
I. INTRODUCTION used as a building block for orthogonal signal generator (OSG)
[12], [13]. The orthogonal signal can be used either in a dq
HE three-phase synchronous reference-frame phase-
T locked loop (SRF-PLL), also called dqo-PLL, is widely
used for synchronization applications in power systems. The
setup [13] or in a direct integration form called the frequency-
locked loop (FLL) [12] to estimate the frequency. The lat-
ter approach coincides with the concept of adaptive notch
SRF-PLL suffers from double-frequency error when the input filter (ANF) [14]–[16]. These tools find applications in con-
signal is unbalanced. Such an error can be mitigated using an trol, filtering, frequency estimation [15], harmonics estima-
in-loop or preloop low-pass filter (LPF) [1] and can also be tion [17], and also grid synchronization [18], [19]; their ex-
completely removed by incorporating dual structures for neg- tensions to three-phase applications are also available [20]. In
ative and zero components [2], [3]. When the input signal has these methods, the quadrature signal (or estimated frequency
some dc component, the loop suffers from an error at the fun- depending on the case) is erroneous when the input signal has
damental frequency. Mitigation of such a low-frequency error some dc.
using in-loop LPF is undesirable because it extremely reduces A method to overcome this drawback of both PLL- and notch
filter (NF)-type algorithms is proposed and studied in this pa-
per. The method is structurally simple and is based on adding
one (or three in a three-phase case) integrator to the system.
Manuscript received August 15, 2010; revised January 25, 2011; accepted
May 15, 2011. Date of current version December 16, 2011. Recommended for This completely rejects the error that is caused by the dc com-
publication by Associate Editor D. Xu. ponent. Moreover, an estimation of the dc component is made
M. Karimi-Ghartemani, P. K. Jain, and A. Bakhshai are with the Department available.
of Electrical and Computer Engineering, Queens University, Kingston, ON
K7M 1L2, Canada (e-mail: [email protected]; [email protected]; This paper is organized as follows. Section II introduces the
[email protected]). problem in the SRF-PLL and formulates the proposed solution.
S. A. Khajehoddin is with SPARQ Systems Inc., Kingston, ON K7L 3N6, Section III presents a brief review of the EPLL and discusses the
Canada (e-mail: [email protected]).
M. Mojiri is with the Department of Electrical and Computer Engineer- proposed modification. Section IV provides a brief review of the
ing, Isfahan University of Technology, Isfahan 84156-83111, Iran (e-mail: NF, presents the proposed modification, and compares it with
[email protected]). an existing method. Section V discusses the design aspects of
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. the proposed method. Simulation and experimental results are
Digital Object Identifier 10.1109/TPEL.2011.2158238 presented in Section VI, and Section VII concludes this paper.

0885-8993/$26.00 © 2011 IEEE

KARIMI-GHARTEMANI et al.: ADDRESSING DC COMPONENT IN PLL AND NOTCH FILTER ALGORITHMS 79

Fig. 1. Three-phase SRF-PLL or dqo-PLL.

Fig. 3. Three-phase PLL of [21].

Fig. 2. Alternative representation of the three-phase SRF-PLL.

II. THREE-PHASE PLL

A. Review of Conventional PLL
The well-known SRF-PLL, also called dqo-PLL, is shown
in Fig. 1. The abc/dqo block realizes the Park’s transformation
vdqo = P vab c where
⎛    ⎞ Fig. 4. Alternative realization of the three-phase PLL of [21].
2π 2π
cos(φ) cos φ − cos φ +
⎜ 3 3 ⎟
 
2⎜
⎜ 2π 2π
⎟
⎟
P = ⎜ sin(φ) sin φ − sin φ + ⎟ . (1)
3⎜ 3 3 ⎟
⎝ ⎠
1 1 1
2 2 2
For a three-phase balanced set of input signals vab c =
(V sin(θ), V sin(θ − 2π/3), V sin(θ + 2π/3))T , the d compo-
nent is vd = V sin(θ − φ). The loop regulates this quantity
to zero and, thus, regulates φ to θ. Assume that the in-
put signal has a dc component of (da , db , dc )T ; then, a term
2/3[da cos φ + db cos(φ − 2π/3) + dc cos(φ + 2π/3)] will su-
perimpose on vd . If the dc offset is unbalanced (i.e., has unequal Fig. 5. Modified three-phase PLL to avoid dc error.
values on three phases), this causes an error whose frequency is
the same as the fundamental frequency.
An alternative representation of the SRF-PLL is shown
B. Proposed Structure
in Fig. 2. In this diagram, the block denoted by “dot”
makes the dot product of its inputs: < x, y >= xT y. The proposed structure is based on the prior work in Fig. 3
Notice that the output of this block in Fig. 2 is equal and it is shown in Fig. 5. The dc component on the input signal
to V sin(θ) cos(φ) + V sin(θ − 2π/3) cos(φ − 2π/3) + is detected by adding a new branch to the structure. The branch
V sin(θ + 2π/3) cos(φ + 2π/3) = 3/2V sin(θ − φ) = 3/2vd . comprises three integrators with equal gains ko to estimate the
Thus, the factor 2/3 is placed to make it equal to vd . The dc components on three phases. Since the dc components are
realization of Fig. 2 discovers the resemblance of this PLL estimated by this branch and directed to the output, the signal e
with the conventional single-phase PLL used in other areas will have no dc, and thus, the PLL operation no longer suffers
of electrical engineering [22], [23]. An improved version from the presence of such components.
of SRF-PLL is presented in [21] and is shown in Fig. 3. A sample simulation is shown in Fig. 6. In this simulation,
In the PLL of Fig. 3, the voltage magnitude V is also the input signal is a balanced signal at frequency 50 Hz that
estimated and helps generate the fundamental component undergoes a jump of frequency to 50.25 Hz at t = 0.1 s, and
f
vab c . A simplified, alternative implementation of the PLL then, a dc component with values of −2%, 1%, and 2% is
of Fig. 3 is shown in Fig. 4. This is derived based on the superimposed on it starting from t = 0.2 s. Performances of
fact that V sin(φ) sin(φ) + V sin(φ − 2π/3) sin(φ − 2π/3) + the conventional SRF-PLL and the proposed PLL in estimating
V sin(φ + 2π/3) sin(φ + 2π/3) = 3/2V . This implementa- the frequency are shown in the Fig. 6 (Top). A large oscillatory
tion clearly shows that this PLL preserves the same structure error with peak-to-peak value of about 0.2 Hz is observed on the
of the SRF-PLL and only adds an amplitude estimation branch conventional SRF-PLL response. The proposed PLL generates
without introducing any change to the basic operation of the no error. The estimated dc components by the proposed PLL are
SRF-PLL. Notice that the location of feed-forward term ωo is shown in Fig. 6 (Bottom) and accurate and fast performance is
selected in such a way that the proportional gain is excluded observed. For this simulation, the values of parameters are set
from the estimated frequency. This improves the steady-state to ki = 5000, kp = 100, k = 200, and ko = 150. A method for
smoothness of an estimated frequency variable. designing the gains is proposed in the next section.
80 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 8. Modified EPLL.

Fig. 6. (a) Performances of the conventional SRF-PLL and the proposed

PLL when frequency jump and dc components are present (b) Estimated dc
components by the proposed PLL.
Fig. 9. SOGI-based OSG.

B. Proposed Modified EPLL

The proposed method is shown in Fig. 8 where an additional
integrator estimates the dc component. The dc component is
estimated through this branch and is added to the output. This
removes the dc from the input signal of the PI unit and, therefore,
the error from the whole loop. The modified EPLL equations
are given by
Fig. 7. Enchanced phase-locked loop (EPLL.) V̇ = μ1 e sinφ, ω̇ = μ2 e cosφ,
φ̇ = μ3 e cosφ + ω, d˙ = μo e (3)
III. SINGLE-PHASE PLL
where e = v − d − V sinφ.
A. Review of EPLL
The EPLL is depicted in Fig. 7, where μ1 , μ2 , and μ3 are IV. NOTCH FILTER
positive real numbers [24], [25]. This EPLL is described by A. Review of the Second-Order Notch Filter
V̇ = μ1 e sinφ, ω̇ = μ2 e cosφ, φ̇ = μ3 e cosφ + ω (2) The second-order BPF has the transfer function of
kωo s
where e = v − y and y = V sinφ. The variables V , ω, and φ BPF(s) = 2 (4)
s + kωo s + ωo2
estimate magnitude, frequency, and angle of the input signal
with nominal fundamental frequency of ωo . The EPLL perfor- and the NF is NF(s) = 1 − BPF(s) where ωo is the center
mance is controlled by three parameters μ1 , μ2 , and μ3 . The frequency and k is a real positive constant that determines
“synchronizing signal” shown in Fig. 7, whose angle is locked the sharpness (or bandwidth) of the filter. The band-pass fil-
with that of the input signal, has a unity magnitude regardless ter (BPF)/NF can be represented by the closed-loop feedback
of the input signal amplitude and is used as a stable signal for diagram of Fig. 9 where x1 is the BPF output and e is the NF
synchronization purposes. output. The transfer function from input to x2 is
Assume that the input signal to the EPLL is v = Vin sin θ +
X2 (s) ωo kωo2
d where d is a dc component. The input signal to the = BPF(s) = 2 . (5)
V (s) s s + kωo s + ωo2
PI unit is e cos φ = (v − V sin φ) cos φ = Vin /2 sin(θ − φ) +
[Vin /2 sin(φ + θ) − V /2 sin(2φ)] + d cos φ. In normal opera- Thus, for an input signal v exhibiting a fundamental component
tion, and when d = 0, the loop regulates the first term to zero at ωo , the output x1 is its bandpass-filtered version with no
and φ approaches θ. The estimated amplitude V approaches Vin phase shift and the output x2 is its low-pass-filtered version with
and the second term (in brackets) that is a double frequency also 90◦ phase shift. That is why this structure is also called OSG
goes to zero. When the dc term d is present, the loop suffers from or quadrature signal generator (QSG). The output x2 exhibits
a low-frequency ripple. Such a term also impacts the amplitude better filtering features for high frequencies as compared with
estimation loop. x1 , but it obviously suffers from nonzero dc offset when the
KARIMI-GHARTEMANI et al.: ADDRESSING DC COMPONENT IN PLL AND NOTCH FILTER ALGORITHMS 81

Fig. 10. Single-phase dq-based PLL using the OSG.

Fig. 13. Modified ANF (SOGI-FLL).

Fig. 11. SOGI-based FLL or ANF.

Fig. 12. Modified SOGI-based OSG.

input signal has some dc component. The magnitude of this

offset is k times that of the input dc component.
A major application of the OSG unit is in the dq-based single-
phase PLL [13], [26]. A structure of this PLL is shown in
Fig. 10. The estimated frequency is fed back to the OSG and
the whole system is adaptive with respect to frequency changes.
An alternative structure, called ANF [15] and also SOGI-based Fig. 14. Comparison of the conventional OSG and the modified OSG when
the input signal undergoes a dc jump of 0.2 p.u. at t = 0.1 s: (a) Quadrature
FLL [19], is shown in Fig. 11. In the PLL of Fig. 10, the dc signals estimated by both methods. (b) dc signal estimated by the proposed
component in the input signal transfers to the quadrature signal method.
and is then transferred to the loop in the form of a low-frequency
error. In the ANF (or FLL) of Fig. 11, the frequency estimation
The proposed modified OSG of Fig. 12 can be used to over-
loop automatically removes the dc offset from the quadrature
come erroneous operation of the dq-based single-phase PLL of
signal. The input dc component, present on e, is multiplied by
Fig. 10. As for the ANF (SOGI-FLL), the frequency estimation
x2 and transferred to the frequency estimation loop again in the
law remains unchanged and, the modified ANF is depicted in
form of a low-frequency error. Therefore, both structures are
Fig. 13. This modified ANF can be represented by
prone to error if the input signal has some dc component.
ẋ0 = ko ωe, ẋ1 = −ωx2 +kωe, ẋ2 = ωx1 , ω̇ = −γex2
B. Proposed Modified OSG (7)
The proposed method for rejecting the dc offset from the where e = v − x1 − x0 .
quadrature signal is shown in Fig. 12. A third integrator gener- A sample simulation result comparing the conventional OSG
ates a third state variable x0 and adds with x1 before subtracting with the modified version is shown in Fig. 14. In this simula-
from the input signal. The following transfer functions describe tion, the input signal is a pure sinusoid until t = 0.1 s when
this system: a dc component of 0.2 p.u. superimposes on it at this time.
The quadrature signal generated by the conventional method
X1 (s) kωo s2 X2 (s) kωo2 s X0 (s) ko ωo (s2 + ωo2 ) becomes biased due to this dc while the proposed method con-
= , = , =
V (s) Δ(s) V (s) Δ(s) V (s) Δ(s) tinues to estimate an accurate quadrature signal [see Fig. 14(a)].
(6) The estimated dc component (x0 ) is shown in Fig. 14(b). The
where Δ(s) = s3 + (k + ko )ωo s2 + ωo2 s + ko ωo3 . Since parameters are k = 1 and ko = 0.25.
Δ(jωo ) = −kωo3 , it is concluded that x1 is a bandpass-filtered
version of input with no phase shift, x2 is a bandpass-filtered
version of the input with 90◦ of phase shift, and x0 will be C. Comparison With an Alternative Method
a low-pass/notch-filtered version of the input signal. Thus, A method for compensating the dc offset of conventional
neither x1 nor x2 will carry any dc offset and x0 will be equal OSG is presented in [6] based on using an LPF as shown in
to the dc component of the input signal. Fig. 15. The LPF can be as simple as LPF(s) = 1/(τ s + 1).
82 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 15. Alternative method of [6].

Fig. 17. Frequency response at point x2 for the proposed method, the alter-
native method of [6], and the conventional method.

grades the high-frequency filtering characteristics of the

system. The level of degradation is already about 10 dB
for the fifth harmonic.
3) The alternative method deteriorates the phase-angle char-
acteristics around the center frequency of 50 Hz (see the
Fig. 16. Frequency response at point x1 for the proposed method and the
conventional method.
zoomed graph in Fig. 17(b)). This shows that the accu-
racy of x2 is sensitive to the uncertainties in the frequency
setting of the filter.
The filter time constant τ must be properly selected to filter out For Figs. 16 and 17, the parameters are selected as k = 1,
higher order harmonics without causing much delay. ko = 0.2, and τ = 1/2π25 = 0.0064 s. With this selection, both
For such a selection of LPF, the transfer function from the methods have almost equal transient time.
input to the new output X2new (s) is given by
kω 2 s2 + ω 2 1 V. DESIGN OF DC LOOP’S GAIN
− k (8)
s2 + kωs + ω 2 s2 + kωs + ω 2 τ s + 1 A. Design for QSG
and thus, its gain at s = 0 is zero and no dc offset transfers to Selection of parameter ko can be done based on the roots of
the new output. Apparently, this method is more prone to errors Δ(s). For a value of k = 1, the root locus of Δ(s) versus ko is
caused by high-frequency harmonics than the proposed method shown in Fig. 18. Small ko causes slow dc estimation and large
of this paper. The reason is that the proposed method of Fig. 12 ko causes oscillatory behavior in orthogonal signals. A tradeoff
offers a transfer function whose magnitude frequency response must be made to avoid both pitfalls. Let us for example assume
decays at a rate of −40 dB/dec at high frequencies while the that all three roots have equal real parts, i.e.,
transfer function in (8) decays with a slope of −20 dB/dec at
high frequencies. s3 + (k + ko )ωo s2 + ωo2 s + ko ωo3
Fig. 16 shows the frequency response of X1 /V for the con- = (s + α)(s + α + jβ)(s + α − jβ). (9)
ventional OSG and the proposed OSG. Notice that the alter-
native method of Fig. 15 has the same function as that of the Then, ko must satisfy
conventional method as far as x1 is concerned. Fig. 17 shows
the frequency response of X2 /V for the conventional OSG, the ko3 + 3kko2 + (3k 2 + 9)ko + k 3 − 4.5k = 0. (10)
alternative method, and the proposed method. The following Fig. 19 shows the real root of this equation (i.e., ko ) versus
observations are made. different values of k. This summarizes the design of ko for
1) The proposed method (and the alternative method of [6]) OSG, SOGI-FLL, and ANF.
does not change the filtering characteristics at point x1 .
Only a tiny degradation at lower frequencies is caused by
B. Design for EPLL
the proposed method but a tiny improvement at higher
frequencies is also obtained. It can be observed that the EPLL is equivalent to a BPF
2) As far as x2 is concerned, although the alternative method if its frequency estimation loop is disabled (i.e., μ2 = 0) and
offers some better filtering characteristics at low frequen- its amplitude/phase gains are identical, (i.e., μ1 = μ3 ). More
cies (subharmonics from zero to 50 Hz) it seriously de- precisely, if μ1 = μ3 = μ = kωo , then it becomes identical with
KARIMI-GHARTEMANI et al.: ADDRESSING DC COMPONENT IN PLL AND NOTCH FILTER ALGORITHMS 83

Fig. 18. Root locus of Δ(s) versus the new parameter k o for k = 1. Fig. 20. Performance of ANF and EPLL systems (conventional and modified)
to a 1 Hz frequency jump at 0.1 s and 0.02 p.u. dc jump at t = 0.2 s.

C. Linear Stability Analysis

The design process presented earlier for ANF and EPLL
serves as a linear stability analysis of those systems when the
frequency update law is disabled. Enabling the frequency es-
timation loop does not invalidate this stability result because
the frequency estimation loop is linearly decoupled from the dc
estimation loop.

VI. SIMULATION AND EXPERIMENTAL RESULTS

A unity amplitude sinusoidal signal at the frequency of 50 Hz
Fig. 19. Design of dc loop’s gain. that undergoes dc component and frequency variations is con-
sidered for simulations. The ANF parameters are set to k = 1,
the OSG.1 This analogy can be used to design μ0 based on the ko = 0.25, and γ = 30000. The EPLL parameters are set ac-
aforementioned design for ko . The following relationship then cordingly to exhibit similar responses, i.e., μ1 = μ3 = 2π50 =
holds 314, μ2 = 30000, and μ0 = 85. Simulations are performed in
MATLAB/Simulink.
μ0 = ko ωo . (11) Fig. 20 shows performances of both ANF and EPLL (con-
ventional and modified versions) to a 1 Hz frequency jump at
In summary, the EPLL parameters are selected as μ1 = μ3 = t = 0.1 s that is followed with a 0.02 jump in the dc component.
kωo and μ0 = ko ωo where ko and k are related according to The estimated frequency and the estimated dc components are
the curve of Fig. 19. The selection of frequency loop gain μ2 shown for comparison. It is observed that the proposed tech-
is made based on the phase/frequency characteristic equations, nique performs successfully to remove the error caused by the
i.e.,2 dc offset in both ANF and EPLL systems.
μ μ2 Another simulation addresses the case where the dc compo-
s2 + s + = 0. (12)
2 2 nent is decaying exponentially. Figs. 21 and 22, respectively,
Assuming, for example, that this loop has a damping ratio of show performances of the ANF and the EPLL systems in this
unity, the gain μ2 can be obtained from scenario. The error in the synthesized in-phase signal, the error

in the synthesized quadrature signal, the estimated frequency,
μ μ2 k 2 ωo2 and the actual and estimated dc’s are shown in parts (a)–(d).
=2 ⇒ μ2 = . (13)
2 2 8 Both modified ANF and modified EPLL follow the variations
in the dc component and remove the error from all internal
signals.
1 The EPLL still remains a nonlinear structure and this equivalence is approx-
The proposed modified EPLL is implemented on an Altera
imate and it becomes more accurate when the input signal is normalized or has FPGA development board of series Stratix II. The A/D conver-
an amplitude equal or around to unity. This, however, serves as a useful fact for
design purposes. sion is performed using 10 bits and the data are forwarded to
2 For normalized input signal, i.e., V equal to unity or around unity. the board. The conventional and modified EPLL structures are
o
84 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 23. Performance of the conventional EPLL in estimating the synchroniz-

ing signal when a large dc component is present. (a) Input signal and estimated
synchronizing signal S. (b) Harmonic content of the estimated synchronizing
signal.

Fig. 21. Performance of the ANF (conventional and modified) to a decaying

dc: (a) Per unit error in in-phase signal (b) Per unit error in quadrature signal.
(c) Estimated frequency in Hertz. (d) Actual and estimated dc in per unit
Fig. 24. Performance of the proposed EPLL in estimating the synchronizing
signal when a large dc component is present. (a) Input signal and estimated
synchronizing signal S. (b) Harmonic content of the estimated synchronizing
signal.

Fig. 25. Transient response of the proposed EPLL in detecting a jump of

−50 V in the input signal dc component.

Fig. 22. Performance of the EPLL (conventional and modified) to a decaying

dc: (a) Per unit error in in-phase signal (b) Per unit error in quadrature signal.
(c) Estimated frequency in Hertz. (d) Actual and estimated dc in per unit.

both implemented and compared. The realization operates at a

40 kHz sampling frequency. The input signal has an ac term Fig. 26. Transient response of the proposed EPLL to a 5 Hz frequency jump.
with 240 V rms and 60 Hz frequency. An exaggeratively large
dc component of −50 V is added to the ac signal in order to study
the performance of the proposed method. Fig. 23 shows the in- distortion from the estimated signals as shown in Fig. 24. The
put signal and the extracted synchronizing signal (S = sinφ) transient response of the proposed EPLL in tracking a jump in
using the conventional EPLL system. The presence of the dc the dc signal is shown in Fig. 25 where the dc component jumps
component causes distortions on the estimated synchronizing −50 V. The response of the proposed EPLL to a frequency
signal component. This distortion appears as a second harmonic jump from 60 to 65 Hz is shown in Fig. 26. The estimated dc
in this signal as shown in Fig. 23. The modified EPLL incorpo- exhibits small oscillations and settles back to the original value
rates the dc component in its modeling and, thus, removes the of −50 V.
KARIMI-GHARTEMANI et al.: ADDRESSING DC COMPONENT IN PLL AND NOTCH FILTER ALGORITHMS 85

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verters,” IEEE Trans. Power Electron., vol. 15, no. 3, pp. 431–438, May
2000.
[5] S. Nam, J. Park, S. Kang, and M. Kezunovic, “Phasor estimation in the
presence of dc offset and ct saturation,” IEEE Trans. Power Del., vol. 24,
no. 4, pp. 1842–1849, Oct. 2009. Masoud Karimi-Ghartemani (M’01–SM’09) re-
[6] M. Ciobotaru, R. Teodorescu, and V. Agelidis, “Offset rejection for PLL ceived the B.Sc. and M.Sc. degrees in electrical en-
based synchronization in grid-connected converters,” in Proc. 23rd Annu. gineering from the Isfahan University of Technology,
IEEE Appl. Power Electron. Conf. Expo., Feb. 2008, pp. 1611–1617. Isfahan, Iran, in 1993 and 1995, respectively and the
[7] N. Stringer, “The effect of DC offset on current-operated relays,” IEEE Ph.D. degree in electrical engineering from the Uni-
Trans. Ind. Appl., vol. 34, no. 1, pp. 30–34, Jan./Feb. 1998. versity of Toronto, ON, Canada, in 2004.
[8] M. Karimi-Ghartemani, H. Karimi, and A. Bakhshai, “A filtering tech- From 2005 to 2008, he was a Faculty Member at
nique for three-phase power systems,” IEEE Trans. Instrum. Meas., the Sharif University of Technology. He is currently
vol. 58, no. 2, pp. 389–396, Feb. 2009. a Researcher with the Queen’s Centre for Energy and
[9] M. Karimi-Ghartemani and M. Iravani, “Wide-range, fast and robust es- Power Electronics Research, Queens University, ON,
timation of power system frequency,” Electr. Power Syst. Res., vol. 65, Canada. His research interests include power system
no. 2, pp. 109–117, 2003. stability and control, grid integration of renewable energy systems, and power
[10] M. Karimi-Ghartemani and M. Iravani, “Measurement of harmonics/inter- quality.
harmonics of time-varying frequencies,” IEEE Trans. Power Del., vol. 20,
no. 1, pp. 23–31, Jan. 2005.
[11] M. Karimi-Ghartemani and M. Iravani, “A method for synchronization of
power electronic converters in polluted and variable-frequency environ-
ments,” IEEE Trans. Power Syst., vol. 19, no. 3, pp. 1263–1270, Aug.
2004.
[12] P. Rodriguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg,
“Advanced grid synchronization system for power converters under un- S. Ali Khajehoddin (S’04–M’10) received the B.Sc.
balanced and distorted operating conditions,” in Proc. 32nd Annu. Conf. and M.Sc. degrees in electrical engineering from the
IEEE Ind. Electron., Nov. 2006, pp. 5173–5178. Isfahan University of Technology, Isfahan, Iran, in
[13] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “A new single-phase PLL September 1997 and June 2000, respectively, and the
structure based on second order generalized integrator,” in Proc. 37th Ph.D. degree from Queens University, Kingston, ON,
IEEE Power Electron. Spec. Conf., Jun. 2006, pp. 1–6. Canada, in April 2010.
[14] L. Hsu, R. Ortega, and G. Damm, “A globally convergent frequency After completing his Masters, he established a
estimator,” IEEE Trans. Autom. Control, vol. 44, no. 4, pp. 698–713, Apr. company where he was involved in the development
1999. and production of digital meters and high-tech power
[15] M. Mojiri, M. Karimi-Ghartemani, and A. Bakhshai, “Estimation of power system analyzers for five years. He was a Postdoc-
system frequency using an adaptive notch filter,” IEEE Trans. Instrum. toral Researcher at Queens University, where he was
Meas., vol. 56, no. 6, pp. 2470–2477, Dec. 2007. involved in the design and implementation of compact and durable microin-
[16] M. Mojiri, M. Karimi-Ghartemani, and A. Bakhshai, “Time-domain signal verters for photovoltaic (PV) grid-connected systems. Since 2010, he has been
analysis using adaptive notch filter,” IEEE Trans. Signal Process., vol. 55, with SPARQ Systems Inc., Kingston, ON, Canada, working toward mass pro-
no. 1, pp. 85–93, Jan. 2007. duction and commercialization of micro inverters. He has filed four patents and
[17] M. Mojiri, M. Karimi-Ghartemani, and A. Bakhshai, “Processing of har- was awarded several scholarships, including the Mathematics of Information
monics and inter-harmonics using adaptive notch filter,” IEEE Trans. Technology and Complex Systems Industrial Postdoctoral Fellowship and the
Power Del., vol. 25, no. 2, pp. 534–542, Apr. 2010. Ontario Graduate Scholarship. His research interests include power electron-
[18] P. Rodriguez, R. Teodorescu, I. Candela, A. Timbus, M. Liserre, and ics, control systems, power quality, and renewable energy systems mainly PV
F. Blaabjerg, “New positive-sequence voltage detector for grid synchro- systems.
86 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Praveen K. Jain (S’86–M’88–SM’91–F’02) re- Alireza Bakhshai (M’03–SM’09) received the B.Sc.
ceived the B.E.(Hons.) degree from the University of and M.Sc. degrees from the Isfahan University of
Allahabad, India, in 1980, and the M.A.Sc. and Ph.D. Technology, Isfahan, Iran, in 1984 and 1986, respec-
degrees from the University of Toronto, ON, Canada tively, and the Ph.D. degree from Concordia Univer-
in 1984 and 1987, respectively, all in electrical sity, Montreal, QC, Canada, in 1997.
engineering. From 1986 to 1993 and from 1998 to 2004, he
He is currently a Professor and a Canada Research was a Faculty Member in the Department of Electri-
Chair at the Department of Electrical and Com- cal and Computer Engineering, Isfahan University of
puter Engineering, Queen’s University, Kingston, Technology. From 1997 to 1998, he was a Postdoc-
ON, Canada, and the Director of the Queen’s Centre toral Fellow at Concordia University. He is currently
for Energy and Power Electronics Research. He has with the Department of Electrical and Computer En-
supervised more than 75 Graduate Students, Postdoctoral Fellows and Research gineering, Queens University, Kingston, ON, Canada. His research interests
Engineers. He has published more than 350 technical papers (including more include high-power electronics, distributed generation, wind energy, smart grid,
than 90 IEEE Transactions papers) and has more than 50 patents (granted and control systems, and flexible ac transmission systems.
pending). He is also a Founder of CHiL Semiconductor Corporation, Tewks-
bury, MA (recently acquired by International Rectifier Corporation) and SPARQ
System, Kingston, ON, Canada. From 1994 to 2000, he was a Professor at Con-
cordia University. From 1990 to 1994, he was a Technical Advisor at Nortel Mohsen Mojiri received the B.Sc., M.Sc., and Ph.D
From 1987 to 1990, he was a Senior Space Power Electronics Engineer at Cana- degrees in electrical engineering from Isfahan Uni-
dian Astronautics Ltd. and a Design Engineer at ABB, in 1981. In 1980, he was versity of Technology, Isfahan, Iran, in 1996, 1998,
a Production Engineer at Crompton Greaves. In addition, he has consulted with and 2005, respectively.
Astec, Ballard Power, Freescale, General Electric, Intel, and Nortel. He was a faculty member at Kashan University
Dr. Jain is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELEC- from 2006 to 2009. He is currently with the Depart-
TRONICS and an Editor of International Journal of Power Electronics. He is ment of Electrical and Computer Engineering, Isfa-
also a Distinguished Lecturer of IEEE Industry Applications Society. He is a han University of Technology. His research interests
Fellow of the Engineering Institute of Canada and the Canadian Academy of include adaptive and nonlinear estimation, filtering
Engineering. He is the recipient of the 2011 IEEE Newell Award—the highest and control, signal processing techniques and algo-
field award in Power Electronics. rithms as applied to power systems control.