Estimation of PLL States in Grid Following Inverter

Operations
Shivam Rai* , Ayush Shankaram* , Aryan Singh*
Department of Electrical Engineering, IIT Roorkee
*
Corresponding Authors: shivam [email protected], ayush [email protected], aryan [email protected]

Abstract—The synchronization of grid-following inverters is ing the performance of grid-following inverters, ultimately
crucial for ensuring stable and efficient power injection into supporting the stability and reliability of modern power grids.
the grid, particularly in renewable energy applications. The
Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) II. G RID -F OLLOWING F REQUENCY I NVERTER S YSTEM
is widely employed for its simplicity and effectiveness in aligning
the inverter’s output with the grid voltage phase and frequency.
Inverters play a crucial role in converting electrical energy
However, under non-ideal grid conditions, such as voltage un- from direct current (DC) to alternating current (AC). On the
balance, harmonics, and frequency deviations, the accuracy of DC side, they are usually connected to a power source or
PLL state estimation becomes a challenge. This research focuses another power electronic interface, which can be modeled
on developing robust estimation techniques for PLL states in using a combination of a DC voltage source, a capacitor, and a
grid-following inverter operations using SRF-PLL. By leveraging
the computational capabilities of the F28379D microcontroller,
current source accounting for conversion losses. These losses
we aim to enhance real-time estimation accuracy and system are typically reflected as resistive elements when viewed from
resilience.. The findings contribute to improving the synchroniza- the AC side.
tion performance of grid-following inverters, thereby enhancing In grid-connected systems, three-phase inverters are widely
grid stability and reliability. employed to interact with the utility grid. Each inverter phase
is linked to the grid through a series resistor-inductor (RL)
I. I NTRODUCTION branch, establishing an inductive-resistive path. The common
The integration of renewable energy sources into modern connection point of all three phases to the grid is known as the
power grids has led to the widespread adoption of grid- Point of Common Coupling (PCC). Accurate synchronization
following inverters, which play a crucial role in ensuring with the grid is vital for stable and efficient energy exchange,
efficient and stable power injection. These inverters rely on and this is typically achieved through control mechanisms like
Phase-Locked Loops (PLLs) to synchronize with the grid Phase-Locked Loops
by accurately estimating the phase angle, frequency, and
magnitude of the grid voltage. Among various PLL structures,
the Synchronous Reference Frame Phase-Locked Loop (SRF-
PLL) is widely utilized due to its robust performance in
normal operating conditions. However, under non-ideal grid
scenarios such as voltage unbalance, harmonics, and frequency
deviations, the accuracy of PLL state estimation becomes
critical for maintaining grid stability and power quality.
In this research, we focus on the estimation of PLL states
in grid-following inverter operations using SRF-PLL. The
objective is to develop efficient estimation techniques that
enhance synchronization accuracy and improve dynamic per-
formance. The study leverages the capabilities of the F28379D Fig. 1. Schematic diagram of an inverter connected to the grid.
microcontroller to implement real-time state estimation, aim-
ing for a practical and scalable approach suitable for real-
world applications. Given the challenges posed by non-ideal III. S YNCHRONOUS R EFERENCE F RAME P HASE -L OCKED
grid conditions, investigating improved PLL state estimation L OOP (SRF-PLL)
methods is essential for ensuring resilient and reliable inverter The Synchronous Reference Frame Phase-Locked Loop
operation. (SRF-PLL) is a widely used control technique for synchroniz-
This paper presents an overview of PLLs in grid-following ing grid-connected inverters with the power grid. It ensures
inverters, highlighting key challenges associated with state accurate tracking of the grid voltage phase angle, frequency,
estimation. The findings of this research contribute to enhanc- and magnitude, which are essential for stable and reliable
operation. By transforming the three-phase AC voltage into
Identify applicable funding agency here. If none, delete this. a rotating reference frame, the SRF-PLL effectively converts
grid dynamics into DC quantities, simplifying the control The TMS320F28379D is a high-performance microcon-
process. troller from Texas Instruments’ C2000™ family, designed for
The SRF-PLL operates by aligning the grid voltage vec- real-time control applications. It features dual C28x CPUs,
tor with the direct axis in the rotating reference frame. A dual Control Law Accelerators (CLAs), and operates at 200
control loop continuously adjusts the estimated phase angle MHz, providing a total processing capability of 800 MIPS.
to maintain synchronization, using a proportional-integral (PI) The microcontroller includes 1 MB of flash memory, 204 KB
controller to regulate the quadrature-axis voltage component of RAM, and supports high-resolution 12-bit and 16-bit ADCs,
to zero. This ensures that the inverter remains in phase with making it well-suited for power electronics and grid-connected
the grid, facilitating efficient power injection and minimizing applications.
harmonic distortions. In grid-following inverter systems, estimating system states
Due to its robustness and effectiveness, the SRF-PLL is such as phase angle, frequency, and voltage magnitude is
commonly implemented in grid-following inverter applica- critical for maintaining synchronization with the power grid.
tions. However, its performance can be affected by grid distur- The F28379D microcontroller provides advanced analog-to-
bances such as voltage unbalance, harmonics, and frequency digital conversion (ADC) capabilities and floating-point pro-
variations. To enhance its adaptability, various modifications cessing, which enable real-time monitoring of inverter states.
and advanced filtering techniques are often integrated into the Additionally, its PWM modules, high-speed communication
SRF-PLL framework, improving its stability under non-ideal interfaces, and on-chip DSP functionalities allow precise con-
grid conditions. trol of inverter switching operations.
For this research, we leverage the F28379D to estimate the
dynamic states of grid-following inverters by implementing
Synchronous Reference Frame Phase-Locked Loop (SRF-
PLL) algorithms. The microcontroller is programmed using
Code Composer Studio (CCS), and real-time waveforms of
estimated states are observed using Digital Storage Oscil-
loscopes (DSO)/Cathode Ray Oscilloscopes (CRO). By pro-
cessing real-time grid voltage and current measurements, the
system can track state variations, improving synchronization
Fig. 2. Schematic diagram of an inverter connected to the grid. accuracy and ensuring stable inverter-grid operation.

A. Equations
To effectively manage a grid-connected converter system,
it is advantageous to simplify the system’s framework by
transforming the original three-phase coordinates into either
the αβ reference frame or the dq rotating reference frame.
Among these, the dq-frame is generally preferred for large-
scale applications due to its DC nature, which simplifies
control and reduces the need for high bandwidth. The trans-
formation from the three-phase system to the dq-frame is
performed using the following equation.
 
2π
 fa (t)
] cos[ρ(t) − 4π
  
fd (t) 2 cos[ρ(t)] cos[ρ(t) − 3 3
]  fb (t)  ,
= 2π
fq (t) 3 sin[ρ(t)] sin[ρ(t) − 3
] sin[ρ(t) − 4π
3
] fc (t)

where f (x) can represent the voltage and the current. ρ is Fig. 3. IC Circuit of F28379D.
the PCC voltage angle that allows for the frame conversion
and is achieved from PLL. The abc-frame can be retrieved as V. MATLAB S IMULATIONS
follows: To validate the theoretical understanding and develop an
    initial framework for implementation, MATLAB simulations
fa (t) cos[ρ(t)] sin[ρ(t)]   were conducted for the SRF-PLL under both ideal and non-
 fb (t)  = cos[ρ(t) − 2π ] 2π  fd (t)
3 sin[ρ(t) − 3 ] . ideal grid conditions. The primary objective of these simu-
fq (t)
fc (t) cos[ρ(t) − 4π3 ] sin[ρ(t) − 4π3 ] lations was to verify the behavior of the PLL in tracking
the phase and frequency of grid voltages, particularly in the
IV. R ESEARCH presence of voltage sags, harmonic distortion, and frequency
deviations.
 The simulations utilized a standard three-phase voltage The implementation architecture is divided into three major
source with configurable harmonic injection and imbalance stages:
features. The transformation from the abc frame to the dq 1) Signal Acquisition and Preprocessing: The analog
rotating reference frame was implemented using Park and voltage input is sampled using ADC configured at a 10
Clarke transforms. A PI controller was designed for regulating kHz sampling rate. The DC offset is removed before
the vq component to zero, which effectively ensured phase conversion into the α − β domain.
locking with the fundamental component of the grid voltage. 2) PLL Algorithm Execution: The core of the SRF-PLL is
executed inside an ISR triggered by the ADC interrupt.
The Park transformation is applied using the estimated
phase angle. A proportional-integral (PI) controller is
used to minimize the vq component and update fre-
quency and phase estimations.
3) Data Communication and Debugging: Real-time es-
timates of frequency and phase are transmitted over
UART using SCI to visualize data on external moni-
toring tools such as serial plotters or MATLAB.

Fig. 4. Simulink Diagram for State Estimation

Fig. 6. TMS320C2000 and F28379D Microcontroller while Testing

VII. A LGORITHMS AND C ODE S NIPPETS

The Phase-Locked Loop (PLL) is an essential component
for synchronizing grid-following inverters. It helps estimate
the grid frequency and phase angle in real-time to ensure
proper synchronization. This report presents the key compo-
nents of a PLL system implementation for grid synchroniza-
tion.
Fig. 5. 3 Phase Input Voltage with 400Volts RMS
In this system, the PLL is implemented using the SRF-PLL
technique, which employs a Park Transform to convert a three-
Simulink blocks were also constructed to emulate the ADC phase system into a rotating reference frame.
sampling, phase generation, and PI loop execution in real
time, which served as a critical reference for embedded
implementation using the TMS320F28379D microcontroller.
These simulations not only provided baseline expectations but
also highlighted corner-case scenarios for debugging during
hardware testing.
VI. CCS I MPLEMENTATION
The PLL estimation algorithm was implemented on the
Texas Instruments TMS320F28379D microcontroller using
Code Composer Studio (CCS). The code was written in C and
utilized the control peripherals of the microcontroller, such as
ADC, ePWM, and SCI modules.
A. PLL Initialization: SRF_PLL_init C. ADC Sampling and PLL Update: adcA1_isr
This function initializes the PLL parameters, including the In this interrupt service routine, the ADC samples the grid
initial frequency and phase angle. voltage and updates the PLL state.
void SRF_PLL_init(SRF_PLL *pll) { interrupt void adcA1_isr(void) {
pll->theta = 0.0f; // Initial phase float adc_result;
pll->freq = GRID_FREQ_NOM; // Nominal grid static float phase = 0.0f;
frequency (50Hz)
pll->v_q = 0.0f; // q-axis component adc_result = ((float)AdcaResultRegs.ADCRESULT0)
pll->integrator = 0.0f; // Initialize * 3.3f / 4095.0f; // ADC result scaled to
integrator voltage
}
// Generate synthetic test signal (optional)
Listing 1. PLL Initialization: SRF PLL init phase += 2.0f * PI * 50.0f / ADC_SAMPLE_RATE;
// Update phase for test signal
This initialization step ensures that the PLL starts with a
zero phase angle and frequency equal to the nominal grid // Single-phase alpha-beta Clark Transform
float alpha = adc_result - 1.65f; // Remove DC
frequency (50 Hz). offset
float beta = 0.0f; // Assume beta = 0 for
B. PLL State Estimation: SRF_PLL_run single-phase input
This function performs the core phase and frequency estima-
// Run PLL algorithm
tion based on the input α and β values (transformed voltages). SRF_PLL_run(&grid_pll, alpha, beta);
void SRF_PLL_run(SRF_PLL *pll, float alpha, float
// Update estimated frequency and phase
beta) {
est_freq = grid_pll.freq;
// Park transform
est_phase = grid_pll.theta;
float cos_theta = cosf(pll->theta);
float sin_theta = sinf(pll->theta);
// Clear interrupt flags
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
pll->v_q = (-alpha * sin_theta) + (beta *
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
cos_theta); // q-axis component
}
// PI Controller for frequency adjustment
Listing 3. ADC Sampling and PLL Update: adcA1 isr
float error = pll->v_q;
pll->integrator += (0.001f * 25.0f) * error; //
Integrator with a time step of 1ms
This ISR handles the ADC conversion and passes the
pll->freq = GRID_FREQ_NOM + (0.5f * error) + pll sampled values to the PLL. The phase and frequency estimates
->integrator; // Frequency estimation are updated continuously within this routine.
// Phase integration VIII. R ESULTS AND I MPROVISATIONS
pll->theta += (2.0f * PI / ADC_SAMPLE_RATE) *
pll->freq; // Phase update Based on simulations and theoretical evaluation of the SRF-
PLL on the TMS320F28379D platform, the following key
// Phase wrapping
if (pll->theta > (2.0f * PI)) pll->theta -= (2.0 insights were gathered:
f * PI); // Wrap phase around 360 degrees • The estimated grid frequency (fest ) maintained close
if (pll->theta < 0.0f) pll->theta += (2.0f * PI)
; // Ensure phase remains positive
tracking across variations typically ranging between 45–
} 55 Hz, with deviations generally remaining under 0.2 Hz.
• Estimated phase (θ) demonstrated good alignment with
Listing 2. PLL State Estimation: SRF PLL run
the synthetic grid voltage, verified through phase com-
This function implements the SRF-PLL algorithm. It first parison in simulation plots.
calculates the q-axis component of the voltage using the Park • The system showcased quick settling behavior, typically
Transform. Then, the PI controller adjusts the frequency based within 40–50 ms after initial startup under nominal con-
on the error, and the phase is integrated over time. ditions.
• Higher-order harmonic presence (e.g., 9th and above)
introduced mild oscillations in the PLL response, sug-
gesting the potential benefit of harmonic suppression
techniques.
The findings from both simulation and hardware demon-
strate that the system is on the right trajectory toward achieving
a robust, real-time estimation framework for SRF-PLL-based
grid-following inverters.
 Fig. 8. End Results Showing alpha waveform

frame (SRF) PLL algorithm was developed and deployed,

delivering accurate results under both simulated and real-time
conditions. Experimental outcomes, supported by MATLAB
simulations, demonstrate the robustness and responsiveness of
the proposed approach. Moving forward, the focus will shift
toward optimizing control strategies, integrating the solution
with practical inverter hardware, and assessing performance
under a wider range of grid scenarios.
X. F UTURE S COPE
This research successfully led to the development and
validation of a real-time PLL-based synchronization system
tailored for grid-following inverters. The TMS320F28379D
microcontroller was effectively utilized for executing time-
sensitive estimation and control algorithms. The system
demonstrated high accuracy in tracking grid voltage phase and
frequency, with its performance rigorously verified through
comprehensive MATLAB simulations and practical hardware
experiments.
With the core implementation complete, the next phase
Fig. 7. Q Output to Alpha-Beta to DQ Tranformation will focus on integrating the PLL system with a full inverter
control setup and evaluating its resilience under challenging
grid conditions, including voltage sags, harmonic distortions,
IX. C ONCLUSION and frequency fluctuations. Further refinements in the PLL
algorithm and data processing methods are anticipated to
The synchronization of grid-following inverters through enhance system responsiveness and stability. Ultimately, this
phase-locked loop (PLL) mechanisms is critical for the reliable work lays the foundation for more advanced power electronics
operation of power electronic systems connected to the grid. applications, supporting robust and adaptive synchronization in
This report outlines the successful design, implementation, and distributed energy systems.
evaluation of a microcontroller-based system for estimating
key PLL states, including grid phase and frequency. Using the XI. T IME L INE
TMS320F28379D microcontroller, real-time signal acquisition The project is divided into several key phases to ensure a
and processing were carried out effectively, validating its structured and systematic approach. The following timeline
capability for precise control tasks. A synchronous reference outlines the major tasks involved:
 • Phase 1: Literature Review – Understanding grid-
following inverters, SRF-PLL, and relevant estimation
techniques.
• Phase 2: Understanding TMS320F28379D – Exploring
the microcontroller’s capabilities, peripherals, and pro-
gramming environment.
• Phase 3: Developing PLL Algorithm – Implementing
and refining the phase-locked loop for synchronization.
• Phase 4: Implementation on Microcontroller – Cod-
ing and testing state estimation algorithms using Code
Composer Studio.
• Phase 5: Testing and Debugging – Verifying system
performance with real-time measurements in CCS.
• Phase 6: Final Report and Presentation – Documenting
the findings and preparing for evaluation.
This timeline serves as a guideline, ensuring that each stage
of the project is completed in a logical and efficient manner.
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