RFIC Design ELEN 351
Lecture 1: General Discussion
Instructor: Dr. Allen Sweet
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General Information
• Instructor: Dr. Allen Sweet
• Email:
[email protected]• Home work/project submissions: Place all
schematics, graphics, and layouts in a power point
or ms word file and email to instructor. Hard copy
is also acceptable.
• Grade: Based on homework, midterm, and
project.
• Reference books: See handout list for suggestions.
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Recommended General Software
• Ms Word
• Ms Power Point
• Snagit utility (demo at www.snagit.com)
• APPCAD (Available from Agilent)
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Simulator Options
• ADS by Agilent
• Ansoft Serenade (RF package is called
Harmonica). Student version is available at
www.ansoft.com/about/academics/sersv/ind
ex.cfm Note: the student version is limited
to only 25 nodes and 2 transistors.
• Genesys by Eagleware
• Golden Gate by Xpedian
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Layout tool Options
• ICEditor (demo is available at
www.iceditors.com, however files cannot
be saved)
• Mentor Graphics
• Cadence
• AutoCAD
• Fast CAD (demo is available at
www.fastcad.com, )
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Course Outline
• General RF/wireless concepts, simulators, simple
design example.
• Receiver/Transmitter architectural options
• Layout techniques
• PA Design
• LNA Design
• Mixer Design
• VCO Design
• Battery issues and tradeoffs, economics of RFICs
• Technology comparison
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What is an RFIC?
• Any integrated circuit for used in the frequency
range: 100 MHz to 6 GHz.
• Generally RFIC’s contain the analog front end of a
radio transceiver, or some part of it.
• RFIC’s can be the simplest SP1T switch, up to the
whole front end of a radio transceiver.
• RFIC’s are fabricated in a number of technologies:
Si Bipolar, Si CMOS, GaAs HBT, GaAs
MESFET/HEMT, and SiGe HBT are today’s
leading technologies.
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Typical Applications for RFICs
• Cellular / PCS phones
• Cellular / PCS infrastructure
• WLANS
• GPS
• BlueTooth
• Wireless PDAs
• Mobile Communications
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Basic Radio Link
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Path Loss Defines the Received
RF Signal Level
(In dB’s)
Signal to Noise ratio
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Shannon’s law gives Maximum
Data Rate in an RF Channel
• Rmax = BW LOG2( 1 + S/N), where BW is the
RF channel’s bandwidth in MHz and Rmax if the
Maximum possible data rate for this channel in
MBits per second.
• All practical MOD- DEMOD systems can only
approach Shannon’s limit.
• Radio Spectrum is a precious commodity! It must
be used wisely, to handle the growing amount of
wireless information flow.
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Multiple Access Techniques
Conserve Valuable Spectrum
• Frequency Division Multiple Access
(FDMA)
• Time Division Multiple Access (TDMA)
• Code Division Multiple Access (CDMA)
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FDMA
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TDMA
Data Packets
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CDMA
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Block Diagram of a CDMA
System
Note: Spreading and De Spreading codes are identical
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Two Port S Parameters
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Types of Device Models
• S Parameter: Limited to small signal gain and
match analysis only.
• Equivalent Circuit: Same limitations as the S
Parameter Model, except it is scalable with area.
• Load Pull Impedance: For PA design, limited in
usefulness to output circuit design only.
• Large Signal Model: No limitations, this is the
most useful class of models.With these models,
ALL measurable parameters can be simulated.
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Types of Large Signal Models
• GaAs HBT: Gummel-Poon, and VBIC
• GaAs MESFET: Curtice, TOM, Materka,
Statz, Tajima,
• GaAs HEMT: EE_HEMT
• Si Bipolar: Gummel-Poon
• CMOS: Many
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The Impedance Smith Chart
LINES OF CONSTANT
REACTANCE
INDUCTIVE
SHORT OPEN
(RESISTIVE AXIS)
Z0 POINT
CIRCLES OF
CAPACITIVE CONSTANT
RESISTANCE
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Impedance locus of a 10 ohm
Resistor in series with a 5 nH coil
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Impedance locus of a 10 ohm
Resistor in series with a 5 pF cap
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Impedance locus of an ideal 50
Ohm transmission line, Grounded
at one end
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RFIC Design Process Steps
• Specifications
• Identify Topology options (literature search)
• Choose a Foundry
• Obtain Foundry’s Device Models and Design
Rules
• Initial Simulations
• Choose final Topology
• Stability Analysis (Amplifiers only)
• Temperature Analysis
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RFIC Design Process Steps,
Continued
• Initial Layout
• Include all Layout Parasitic elements in Topology
• Minimize Layout Area, Preserving Performance
The Art of the Trade Off
• Complete Final Layout
• Create Test Cells for Critical Circuit Blocks
• DRC at the Foundry
• Assemble the Reticle, Tapeout
• Mask Making, Wafer Fabrication
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Homework Assignment #1:
Simulate the following Amplifier
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BIAS CHOKE
Circuit Details:
FEEDBACK
RESISTOR
OUTPUT
INPUT BLOCKING
BLOCKING CAP
CAP
TRANSISTOR
AREA=3 FINGERS
BASE BIAS
STABILIZING RESISTOR
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Gummel Poon InGaP/GaAs HBT
Device Model: 2x12 micron
emitter finger
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Simulated Gain/Match/DC
Conditions
GAIN
OUTPUT MATCH
INPUT MATCH
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Smith Chart Display: Amplifier’s
Input and Output Impedances
OUTPUT IMPEDANCE
INPUT IMPEDANCE
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Simulated Noise Figure
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Simulated Stability Factor (K)
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