Subject :VLSI Design

and technology
BE(E&TC)
Unit III
Digital Design issues

Prof.Surekha B. Puri
Contents
___________________________________
 Clock skew,
 Clock Distribution Techniques,
 Clock Jitter,
 Supply and Ground Bounce.
 Power Distribution Techniques,
 Power Optimization
 Interconnect Routing Techniques,
 Wire Parasitic,
 Signal Integrity Issues
 I/O Architecture
 Pad Design
 Architecture for low power.
Clock Skew
___________________________________
 Defined as: Maximum difference
in arrival times of clock signal to
any 2 latches/FF’s fed by the
network
 If clock at the capture F/F takes
more time to reach as compared to
the clock at the launch F/F, refer it Skew = max | t1 – t2 |
as Positive clock skew.
When the clock at the capture F/F
takes less time to reach at the
launch flop, referred to as
Negative Clock Skew.
Clock Skew
___________________________________
 Skew describes a relative delay or offset in time between two signals.
 Skew causes problem : combining two sets of values but are in fact combining a
different set of values.
 Skew between
 Two data signals
 A data signal and a clock or
 Between clock signals in multi-clock system
A circuit that introduces signal skew relative to a clock
___________________________________
Clock Skew
___________________________________

 Signal provided to latch is valid from 0 to 5ns but the clock edge
does not arrive at the latch until 6ns.

Latch will store garbage value.

Clock Skew and qualified clocks
___________________________________
Sources of Clock Skew
___________________________________

 If they are from external sources, they may arrive skewed.

The delays through the clock network may vary with position on the
chip.

 Qualified clocks may add delay to some clock destinations and not
others.

 Skew can vary with temperature due to temperature dependencies

on gate/buffer delay and wire delay.
Skew and Qualified Clocks
___________________________________

Model system for clock skew Timing in the

analysis in flip-flop-based skew model.
machines
Skew in Clock Distribution
___________________________________

Skew in a clock Dealing with

distribution tree. clock skew
Skew in Clock Distribution
___________________________________

very bad case: design has This case is better: no

both large clock skew and clock skew here but still
long wires that lead to large have long wires.
combinational delays.
Skew in Clock Distribution
___________________________________

This case is even better:This design reduces the combinational delay and
keeps the flip-flops within one island of clock skew.
Clock Skew: Positive Skew
Here, clock at FF2 takes longer to succeed in as compared to the time
taken by the clock to succeed in the FF1.
Recall that the setup check means that the data launched should reach the
capture flop at most setup time before the next clock edge.
As evident within the below the info launched from FF1 gets an
additional time adequate to the skew to succeed in FF2.Hence setup is
relaxed.
Hold check means that data launched should reach the capture flop at least
hold time after the clock edge
Hence the hold is further made critical incase of positive skew.
Clock Skew: Negative Skew
___________________________________
 Clock at FF1 takes longer to succeed in as compared to the time taken
by the clock to succeed in the FF2.
 As evident within the below the info launched from FF1 gets lesser
time adequate to the skew to succeed in FF2.
Hence setup is more critical. However, hold is relaxed.
Clock Distribution Techniques
___________________________________
The main job of the clock routing design is to control
clock skew from the clock pad to all the memory
elements.

Major obstacle to clock distribution is capacitance , with

resistance playing secondary but important role.

Clocking is a floor planning problem because clock

delays varies with position on the chip.

Clock Distribution Techniques
___________________________________

The clock distribution network or clock tree is the metal and buffer
network that distributes the clock to all clocked elements.

Clock trees are usually built by clock tree synthesis tool.

There are two complementary ways to enhance clock distribution:

• Physical design - The layout can be designed to make clock delays more
even, or at least more predictable.

• Circuit design -The circuits driving the clock distribution network can be
designed to minimize delays using several stages of drivers.
Styles of physical Clock networks
___________________________________
• H tree: Regular structure which allows
predictable delay.

• Balanced tree: takes opposite approach of

synthesizing a layout based on the characteristics
of the circuit to be clocked.
Network Types: H Tree
___________________________________
 Original H-tree
 One large central driver
 Recursive H-style structure to match wire-
lengths
 Halve wire width at branching points to scale
back reflections
 Wire adjust the load capacitance.
 Buffers wont to increase drive capability.
 Skew increases with physical distance .
 Memory elements are grouped together.
H Tree Problems
___________________________________
 Drawback to original tree concept
 slew degradation along long RC paths
 unrealistically large central driver
 Clock drivers can create large temperature gradients
(ex. Alpha 21064 ~30° C)
 non-uniform load distribution
 Inherently non-scalable (wire resistance skyrockets)
 Solution to some problems
 Introduce intermediate buffers along the way
 Specifically at branching points
Buffered Clock Tree
___________________________________
Buffered H Tree
___________________________________
 Advantages
 Ideally zero-skew
 Can be low power (depending on skew requirements)
 Low area (silicon and wiring)
 CAD tool friendly (regular)
 Disadvantages
 Sensitive to process variations
 Local clocking loads are inherently non-uniform
Balanced Tree
___________________________________
 Generated by placement and
routing.
 Clustering is used to guide
placement and a clocking tree is
synthesized based on the skew
information generated during
clustering.
 Tree is irregular in shape but has
been balanced during design to
minimize skew. A Balanced Clock Tree
 Wire width varied in the tree and
buffers can be added.
Clock Distribution Tree
___________________________________
 Two strategies used to distribute clock
 Driver chain: to drive entire load from single point
 Distributing drivers: through clock wiring, forming a
hierarchical clock distribution system
 Use even number of driver stages to avoid inverted clock.
 Capacitance and resistance analyzed; Buffer to be added.

Fig. A Clock Distribution

Tree
Clock Skew and Clock Balancing
___________________________________
 Clock skew
 Hold time violation is critical to working silicon
 Aggressive skew budget for high speed operation
 Large turn-around-time for clock tree synthesis at P&R stage
 Skew Source : process + voltage + temp + load + jitter
 Skew Budget == ( Target Cycle Time ) /20 , min clk->Q
 Solution
 CTS (Clock Tree Synthesis)
 Insert dummy delay at Synthesis  Over-design
 Clock Tree Style
___________________________________
1. H-Tree Model 3. Fanout Balance Tree Model
Less flexible Easy to construct
Net applicable to placement Weak for blest latch distribution

4. Spine and trunk Model (Fish and Bone)

2. Binary Tree Model
Easy to adjust Net Loading Skew Hardly influenced
Many dummy cells are needed by Process Scattering
Die size increase
Practical Problems in Clock Tree Synthesis
___________________________________
 Problems
 Large chip size due to SOC integration
 FF’s = enormous, memory
 Unbalanced FF distribution
 Top-level : Interconnect RC dominant
 Block-level : turn-around-time
 Iteration cost
 Test clock
 Multiple clock frequency
 Solution
 Plan from the early design stage
 Skew budgeting : 100ps @ 200MHz
Block Level Clock Tree
___________________________________
 Block-level clock skew
 Driver-limited
 Optimization of the buffer strength and number
 Clock tree synthesis
 Commercial tool
 Many iterations
 Long turn-around-time
 Clock tree planning
 Virtual clock tree generation
 Need engineering approximation
Real Clock Tree
___________________________________

Clock tree style

Trunk-and-Branch
 Virtual Clock Tree Model
___________________________________
 Assumption :Uniform distribution of clock buffers and flip-flops
 Model : Hierarchical trunk-and-branch

N=6 N=7 N=8

Top Level Clock Distribution
___________________________________
Clock Jitter
___________________________________
Clock network delay uncertainty.

 From one clock cycle to the next, the period is not exactly the same
each time.

 Maximum difference in phase of clock between any two periods is

jitter.

NOTES : JITTER J1 = t2 – t1
JITTER J2 = t3 – t2
Clock Jitter Types
___________________________________

 Period Jitter
Period jitter is that the deviation in cycle time of a clock signal with reference
to the perfect period over variety of randomly selected cycles(say 10K cycles).
It can be specified an average value of clock period deviation over the selected
cycles or can be the difference between maximum deviation & minimum
deviation within the selected group(peak-to-peak period jitter).

 Cycle to cycle Jitter

C2C is that the deviation in cycle of two adjacent clock cycles over a random
number of clock cycles. (say 10K). This is typically reported as a peak value
within the random group. This is wont to determine the high frequency jitter.
Clock Jitter Types
___________________________________
 Phase Jitter
In frequency domain, the effect being measured is phase noise. It is the
frequency domain representation of rapid, short-term, random fluctuations in the
phase of a waveform. This can be translated to jitter values for use in digital
design.

 Effects
• The jitter affects the clock delay of the circuit and the time the clock is
available at sync points, setup and hold of the path elements are affected
by it.
• Depending on whether the jitter causes to clock to be slower or faster,
there can be setup hold or setup violations in an otherwise timing clean
system. This will in turn lead to performance or functional issues for the
chip.
• So it is necessary that the designer knows the jitter values of the clock
signal and account for it while analyzing timing.
Supply and Ground Bounce
___________________________________
It can be defined as variations in ground voltage due to
impedance on the ground wires
Example : A and B are control inputs and turn on the NMOS
transistor at high logic (more than 0.7V).
The output is high when Q2 turns off and Q1 turns on.
Similarly, the output is low when Q2 turns on and Q1 turns off.
When the signal transitions from high to low, Q2 provides a
path for the current to flow from the output to ground.

A typical Output Circuit

There is some inductance in the very small lead wires between the chip itself and the
lead carrier of the package.

This inductance is very small, but it is significant. Consider what happens the
moment Q2 turns on and Q1 turns off.

A spike of current flows from the output through Q2 to ground. This current flows
through the inductance in the lead. The voltage across this inductance (V Ref B) is
directly related to the change in current as:

Effect of internal Inductance

Supply and Ground Bounce
___________________________________
di/dt is related to the rise (and/or fall) time of the device. The
faster the rise and fall times, the smaller dt is, the greater di/dt
(the change in current per unit time) is, and the higher the
voltage drop is across any inductance.
As Q2 turns on and the output voltage starts to fall, the voltage
between the output and Ref B falls just as before. The voltage at
Ref is relative to ground rises because of the current spike
through the lead inductance.
 Thus, V does not fall all the way, but "bounces" above ground
because of this inductive drop. This is the phenomenon called
ground bounce.
Power Distribution Techniques
___________________________________
Power distribution presents several significant problems.
First, design a global power distribution network that runs both VDD
and VSS entirely in metal.
Second, size wires properly so that they can handle the required currents.
Third, ensure that the transient behavior of the power distribution
network does not cause problems for the logic to which it supplies
current.
While keeping all these problems in mind, tackle two types of power
supply loss:
IR drops from steady state currents

 drops from transient current.

 Power Distribution Techniques
___________________________________
Power network planarity
Orient all the cells so that their VDD
pins are all on the same side of a
dividing line through the cell, are
guaranteed that a planar routing
exists.

Fig. A floor plan that isolates a ground pin

Metal Migration and Wire Sizing
 If too much current is carried through a
wire, the wire quickly disintegrates.
 Power lines are usually routed as trees,
with the power supply at the root and the
logic gates connected to the twigs.
Fig. Integrated power and ground trees
Power Distribution Techniques
___________________________________
Power distribution grids
In a large chip, power is distributed using several metal layers.
 The upper layers are larger in both width and height.
The layers closer to the silicon are smaller in both dimensions.
Global power distribution happens on the upper layers;
connections on the lower layers move power down to the
circuits.

Power Distribution in BELLMAC 32A

Interconnect Routing Techniques
___________________________________
Chip-level wiring design is usually divided into two phases:
 global routing assigns wires to routing channels between the blocks.
detailed routing designs the layouts for the wiring.
Global Routing
• Routing Algorithms
• Utilization as metric
• Line Probe Routing

Fig. Line Probe Routing

Interconnect Routing Techniques
___________________________________
Switchbox Routing
A switchbox may be used to route wires between
intersecting channels.
The track assignments at the ends of the channels define the
pins for the switchbox.
 It is often possible to define channels without requiring
switchboxes, but switchboxes may sometimes be necessary
in floor planning.
A switch Box formed at the
interconnection of two
channels
Power Optimization: Logic Gates
___________________________________
Reduce Power consumption of isolated gate logic
To make it change its output as few times as possible.
Number of unnecessary changes to a gate’s output.
The gate would not be useful if it never changed its output
value.
To reduce the number of unnecessary changes to a gate’s
output
Glitches and Power
_______________________________________________

Glitching in a simple logic network

 Sources of Glitches
___________________________________
• Some sources of glitches are more systematic and easier to
eliminate.

Glitching in a chain of adders.

 Signal Probabilities
___________________________________
• Need to be able to estimate the signal probabilities in the
network.

• The signal probability Ps is the probability that signal s is 1.

• The probability of a transition Ptr,s can be derived from the

signal probability, assuming that the signal’s values on clock
cycles are independent:

Ptr,s = 2Ps(1-Ps)
Delay-independent and delay-dependent power
estimation
___________________________________
There are two major ways to compute signal probabilities and power
consumption:
1. delay-independent and
2. delay-dependent.

Analysis based on delay-independent signal probabilities is less accurate

than delay-dependent analysis but delay-independent values can be
computed much more quickly.
The time/accuracy trade-offs for power estimation
track those for delay estimation:
1. circuit level methods are the most accurate and
costly;
2. switch-level simulation is somewhat less accurate
but more efficient;
3. logic-based simulation is less powerful but can
handle larger networks.
Wire Parasitic
___________________________________

Wires, vias and transistors all introduce parasitic elements into

our circuits.
Parasitic components are Resistance and capacitance
Diffusion wire capacitance
Bottom wall capacitance – depends on the diffusion area
Side wall capacitance – depends on the perimeter

Sidewall and bottomwall

capacitances of a
diffusion region
 Wire Parasitic
___________________________________
• The depletion region capacitance value is given by
permittivity
of Si

depletion
capacitance depletion
at zero bias region width Built in
voltage

Junction capacitance decreases as

reverse voltage increases
 Plate and fringe capacitances of a parallel-plate
capacitor
___________________________________

• Capacitance formed due to poly and metal wires.

• Plate capacitance : per unit area assumes infinite parallel plates
• Fringe Capacitance: due to changes in the electrical fields at the
edges of the plate.
Capacitive coupling between signals on
the same and different layers
___________________________________.
• Number of metal layers increases and the capacitance of the
substrate decrease.
• Wire to wire capacitance.
• Cm1m2 – capacitance between two different metal layers,
depends on are of overlap between two wires.
• Cw1w2 – two wires on same layer
Resistance per unit square is constant
___________________________________
• Wire resistance are computed by measuring size of the wire.
• Unit ohm per square
Signal Integrity
___________________________________

An engineering Practice

Ensures all signals transmitted and received correctly.
Ensure signals don’t interfere with one another in a
way to degrade reception.
Ensure signal don’t pollute the electromagnetic
spectrum.
At what point Signal Integrity becomes a problem
___________________________________

Length
Thickness
Width
Distance from surrounding traces and ground planes
Material used
Connections to the traces
Signal Integrity
___________________________________

Signal can loose it’s integrity is when it becomes

distorted or when SNR begins to degrade.

Signal distortion means that waveform of interest

begins to change shape.

The degree to which this happen before it becomes a

problem depends very much on application.
Signal Integrity Issues
___________________________________
 Rise Time and SI
 Transmission Lines,
 Reflection,
 Crosstalk
 Power/Ground Noise
 Rise Time and SI
___________________________________

 The silicon size is shrinking dramatically and therefore

the transistor channel length is greatly reduced into sub-micron
range.
 This trend results in today’s logic families operating at much
higher speed.
 Their rise and fall time are on the order of hundreds of
picosecond.
 Many SI problems are directly associated with dV/dt or dI/dt,
faster rise time significantly worsens a number of the noise
phenomena like ringing, crosstalk, and power/ground switching
noise.
 Rise Time and SI
___________________________________

• Systems with faster clock frequency usually have

shorter rise time, therefore they're going to be facing
more SI challenges.
• A product is working at 20Mhz clock frequency, it's
going to still get some SI problems that a 200MHz
system will have when modern logic families with fast
rise time are used.
Transmission Lines
___________________________________
1. All the transmission lines have basic parameters such as per-
unit-length
2. R (resistance),
3. L (inductance),
4. G (conductance) and
5. C (capacitance), unit-length time delay (inverse of the
propagation speed), and characteristic impedance.
Reflection
___________________________________
If the trace length is infinite, the wave/pulse will never
reflect and won’t distort the signal.

Make it look like an infinite length by terminating with

high impedance equal to characteristics impedance.

Wires must be absolutely identical everywhere along

the length.
Reflection
___________________________________
Reflections are not too bad problem if receiver is close enough
to sender.

Track length is short.

Reflection Coefficient: Value range between +1 to -1

+1 is for open end
-1 for short end
0 means the trace is perfectly terminated.
 Crosstalk
___________________________________
Crosstalk, caused by EM coupling between multiple transmission lines
running parallel.
The adjacent quiet signal lines which will cause false logic switching.

Crosstalk also will impact the timing on the active lines if multiple lines are
switching simultaneously.

Depending on the switching direction on each line, the extra delay

introduced may significantly increase/decrease the sampling window.
The amount of crosstalk is related to the

signal rise time, to the spacing between the lines, and

to how long these multiple lines run parallel to each
other.

Besides the crosstalk between traces, via coupling is

sometimes also important.
Guidelines for reducing the crosstalk
___________________________________
• Place traces in strip line environments.

• Minimize distance between trace and plane.

• Maximizes the separation between the traces

• Add ground guarding band in between the signal

lines
• One can make the lines space apart
Interleaved power/ground
________________________________________

VDD

VSS

VDD

VSS

VDD

VSS
Ground wires
___________________________________

VSS

sig1

VSS

sig2

VSS
Crosstalk example
___________________________________
 Power/Ground Noise
___________________________________
• In chip package and computer circuit board, power/ground
planes with vias form power distribution networks.
• Transient currents drawn by a large number of devices
switching simultaneously can cause voltage fluctuations
between power and ground planes.
• simultaneous switching noise (SSN), or Delta-I noise, or
power/ground bounce.
• SSN will hamper the signals thanks to imperfect return path
constituted by the power/ground distribution
I/O Architecture
___________________________________
• Pads and their associated drivers are distributed around the edge of the
chip.

• Advanced, high-density packaging schemes devote a layer of metal to pads

and distribute them across the entire chip face.

• Each pad must be large enough to have a wire (or a solder bump) soldered
to it.

• It must also include input or output circuitry, as appropriate.

Architecture of a pad frame
___________________________________
 Pad Frame
___________________________________
• Each pad is built to a standard width and height, for simplicity.
• Each pad has large VDD and VSS lines running through it.
• A pad includes a large piece of metal to which the external wire
is soldered.
• If the pad requires external circuitry, it is usually put on the side
of the pad closest to the chip core.
• The chip core fits in the middle of the pad ring.
• If the pad ring is not completely filled with pads, spacers are
added to keep the power lines connected.
• The placement of pads around the ring is usually determined
by the required order of pins on the package.

• The wires to the package cannot be crossed without danger of

shorting, so if the package pins are required in a certain order,
the pads must be arranged in that order.

• The order of pins on the package determines routability of the

board and electrical noise among other things.

• The order of pins on a package has been known to determine

which candidate design wins a design contest.
• The pad is much larger than any single wire connected to it, so
the current in each direction is limited by the outgoing wire.

• If we want to use multiple power pins to limit inductive voltage

drop, we can use several VDD and VSS pads around the ring.

• VDD and VSS pads are the easiest pads to design because they
require no circuitry each is a blob of metal connected to the
appropriate ring.
Pad Design
___________________________________

Pads and pad circuitry

• Pads used for input and output signals require

different supporting circuitry.

• A pad used for both input and output, sometimes

known by its trade name of Tri-state pin1, combines
elements of both inputs and output pads.
 Input pads
___________________________________

• The input pad may include circuitry to shift voltage levels or

otherwise condition the signal.

• The main job of an input pad is to protect the chip core from
static electricity.

• People or equipment can easily deliver a large static voltage to

a pin when handling a chip.

• MOS circuits are particularly sensitive to static discharge

because they use thin oxides.
• The gate oxide, which may be a few hundred Angstroms thick,
can be totally destroyed by a single static jolt, shorting the
transistor’s gate to its channel.

• An input pad puts protective circuitry between the pad itself

and the transistor gates in the chip core.

• Electrostatic discharge (ESD) can cause two types of problems:

dielectric rupture and charge injection.

• When the dielectric ruptures, chip structures can short

together.

• The charge injected by an ESD event can be sufficient to

damage the small on-chip devices.
 Output pads
___________________________________
• Electrostatic discharge protection is not needed for an
output pad because the pad is not connected to any
transistor gate.
• The main job of an output pad is to drive the large
capacitances seen on the output pin.
• Within the chip, λ scaling ensures that we can use
smaller and smaller transistors, but the real world
doesn’t shrink along with our chip’s channel length.
Output pads
___________________________________
 A three-state pad circuit
___________________________________
• Three-state pads, used for both input and output.
• Pad can not, used as an input and output simultaneously.
• Chip core is responsible for switching between modes.
• Pad requires electrostatic discharge protection for when the
pad is used as an input.
• An output driver for when it is used as an output, plus circuitry
to switch the pad between input and output modes.

Input_mode=1
 Boundary scan for pads
___________________________________

• Pads may also include circuitry to support boundary scan, which configures
the chip’s pins as an LSSD chain.

• Chips that support boundary scan can be chained to form a single scan path
for all the chips on a printed circuit board.

• Boundary scan makes the printed circuit board much easier to test because
it makes the chips separately observable and controllable.

• Boundary scan support requires some circuitry on the pins corresponding

to the chip’s primary inputs and outputs, along with a small controller and a
few pins dedicated to boundary scan configuration
Architecture for Low Power
___________________________________
• Power, thermal and reliability.

• High temperatures and temperature gradients can cause delays

to change, which may cause transient failures.

• High temperatures can also cause chips to permanently fail.

• Low-power design therefore becomes a critical concern

because of its dual implications: the high cost of high energy
and power consumption itself, and the thermal barriers to
reliability.
Power Controller
___________________________________
• Power controllers are in charge of dynamic power
management on a chip or a section of the chip.

• Power controllers are common in modern microprocessors

and large ASICs.

• A chip may have more than one power controller, each

managing a different part of the chip.

• These power controllers are generally controlled by

software.
Contd..
___________________________________

A power controller and its connections to the rest of the system

 Power minimization through control
___________________________________
• Implementing a power-down mode requires implementing
three major changes to the system architecture:
1. Conditioning the clock in the powered-down section by a
power down control signal;
2. adding a state to the affected section’s control that
corresponds to the power-down mode;
3. further modifying the control logic to ensure that the
power-down and power-up operations do not corrupt the state
of the powereddown section or the state of any other section
of the machine.
 Power control
___________________________________

Gate Power Control

Data Latching,
Clock Gating,
Architecture-Driven Voltage Scaling
Dynamic Voltage and Frequency Scaling
 Gate Power Control
___________________________________

• Depending on the type of gate used, its power consumption

may be controlled in several ways.
• The gate’s power supply voltage may be controlled directly, in
which case the power controller would talk to the power supply
module.
• A related technique is changing the substrate voltage in a
region, as is done for VTCMOS gates; this requires fabrication
support, such as triple wells.
• Some gates, such as MTCMOS, are controlled by a direct input.
 Data Latching
___________________________________

• Glitch reduction reduces power consumption by eliminating

unnecessary circuit activity.
• If we will not use the output of a unit, then we should not allow
its inputs to change, which would cause unnecessary
transitions to flow through the unit.
• We can use conditional clocks on existing latches to hold data
values that are not used.
• We can also add latches to units with combinational inputs; of
course, that requires adjusting the overall clocking to ensure
that values arrive at the proper times.
Clock Gating
___________________________________
• The conditional clock for the power-down mode must be
designed with all the caveats applied to any conditional
clock—the conditioning must meet skew and edge slope
requirements for the clocking system.

• Static or quasi-static memory elements must be used in the

powered-down section for any state that must be preserved
during power-down.
• The power-down and power-up control operations must be
devised with particular care.
• Not only must they put the powered-down section in the
proper state, they must not generate any signals that cause the
improper operation of other sections of the chip, for example
by erroneously sending a clear signal to another unit.
• Power-down and power-up sequences must also be designed to
keep transient current requirements to acceptable levels—in
many cases, the system state must be modified over several
cycles to avoid generating a large current spike.
Architecture-Driven Voltage Scaling
___________________________________
• Power and supply voltage
• Trading parallelism for clock rate
• Power improvement
Contd..
___________________________________

before

after

Increasing parallelism to counteract scaled power supply

voltage.
Dynamic Voltage and Frequency Scaling
___________________________________
• Dynamic voltage and frequency scaling (DVFS) was
developed
to control the power consumption of microprocessors. Like
architecture- driven voltage scaling, DVFS relies on the fact
that performance varies as while power consumption varies
as .
• Unlike architecture-driven voltage scaling, DVFS is a dynamic
technique—both the clock frequency and power
consumption vary during operation.
• DVFS relies on the fact that microprocessors do not always have to run at
full speed in order to finish all their tasks.
• If the microprocessor’s workload does not require all available CPU
performance, then we can slow down the microprocessor to the lowest
available performance level that meets the current demand.
• The power controller for DVFS controls the microprocessor power
consumption through a combination of clock frequency and power supply
changes.
• The power controller needs a simple algorithm to determine the proper
clock frequency and power supply settings from a load estimate.
• A software interface allows the operating system or other programs to tell
the power controller the required performance.
• This software interface updates a register that is visible to the power
controller; that register is the interface between the system-level load
estimate and the commands to the clock generator and power supply.
Thank you !!!!!