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Interview Questions

1. Synchronous reset samples reset with the clock edge, providing filtering of glitches but requiring clock presence. Asynchronous reset applies reset immediately without waiting for a clock edge, making it faster but more sensitive to glitches. 2. Inter-assignment delays specify the delay on the left side, delaying the entire statement. Intra-assignment delays specify the delay on the right side, delaying only the right side evaluation. 3. Gate delays model signal propagation delays through gates from input to output. Transport delays model propagation through inertialess wires. Inertial delays model gates, rejecting pulses shorter than the delay time. Wire delays specify propagation delays through nets or from gate inputs to outputs.

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45 views2 pages

Interview Questions

1. Synchronous reset samples reset with the clock edge, providing filtering of glitches but requiring clock presence. Asynchronous reset applies reset immediately without waiting for a clock edge, making it faster but more sensitive to glitches. 2. Inter-assignment delays specify the delay on the left side, delaying the entire statement. Intra-assignment delays specify the delay on the right side, delaying only the right side evaluation. 3. Gate delays model signal propagation delays through gates from input to output. Transport delays model propagation through inertialess wires. Inertial delays model gates, rejecting pulses shorter than the delay time. Wire delays specify propagation delays through nets or from gate inputs to outputs.

Uploaded by

Mannava Premkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1.

Difference between synchronous and asynchronous reset


Synchronous reset
Synchronous reset means reset is sampled with respect to clock. In other words,
when reset is enabled, it will not be effective till the next active clock edge.
Advantages:
1. gives a completely synchronous circuit
2. Provides filtering for the reset signal, so circuit will not be affected by glitches. (Special
case: If glitch happens at the active clock edge, reset signal will be affected.)
3. Will meet reset recovery time, as the deassertion will happen within 1 clock cycle.
Disadvantages:
1. Reset needs to be stretched, if it is not long enough to be seen at the active clock edge.
2. Requires presence of clock to reset the circuit.
3. Asynchronous reset may be required if there are internal tri state buffers.
4. It is slow.
5. Synthesis will not be able to easily differentiate reset from other signals. So this has to
be taken care while doing synthesis. Otherwise it may lead to timing issues.
6. If there are gated clocks for power saving, this type of reset won’t be suitable.
Asynchronous reset
In asynchronous reset, reset is sampled independent of clk. That means, when
reset is enabled it will be effective immediately and will not check or wait for the clock
edges.
Advantages :
1. Reset gets the highest priority.
2. It is fast.
3. Does not require presence of clock to reset the circuit.
Disadvantages:
1. Reset line is sensitive to glitches.
2. May have metastability issues

2. Difference between inter assignment delay and intra assignment


delay
Inter Assignment Delays
An inter-assignment delay statement has delay value on the left-hand side of the
assignment operator.
Inter assignment are those delay statements where the execution of the entire
statement or assignment got delayed.
In Verilog, Inter assignment delays often correspond to the inertial delay or the VHDL's
regular delay statements.
// Delay is specified on the left side  
#<delay> <LHS> = <RHS>  
It indicates that the statement itself is executed after the delay expires, and is the most
commonly used form of delay control.
Intra Assignment Delays
Intra assignment delay indicates that the statement itself is executed after the delay
expires, and it is the most commonly used form of delay control.
They can be used with blocking and non-blocking assignments. If a statement with intra-
assignment timing controls is encountered during simulation, then the expression will be
evaluated, and its value will be stored.
Then, the statement's execution will be suspended until the time specified by the delay
control expires. Changes in the expression value up to the time of the event will be
ignored.
// Delay is specified on the right side  
<LHS> = #<delay> <RHS>  
An intra-assignment delay is declared to the right-hand side of the assignment operator.
This indicates that the statement is evaluated, and the values of all signals on RHS are
captured first.

3. Gate delay, transport delay, inertial delay, wire delay,


contamination delay
Gate Delay
Verilog gate delays specify how values propagate through nets or gates. The gate delay
declaration specifies a time needed to propagate a signal change from the gate input to its
output.
The gate delay declaration can be used in gate instantiations.
Transport delay
Model delay through elements with no inertia, e.g., wires
No inertia, so all input events are propagated to output signals
Any pulse, no matter how short, is propagated
In order to model this delay the keyword transport must be specified in the code
Inertial delay
Suitable for modelling delays through devices with inertia (e.g. logic gates)
Pulses shorter than a device’s delay are not propagated to its output
If a gate has an ideal inertia delay T, in addition to delaying the input signals by time T,
any pulse with a width less than T is rejected
Wire delay
Delays specify a time in which assigned values propagate through nets or from inputs to
outputs of gates
Contamination delay

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