ENCS3310

Advanced Digital Design

Lecture 3
How Verilog deals with time
Introduction

 Verilog simulation tells us how our design responds

to changes in inputs
 We want to know
 How fast can our design go?
 Will it produce spurious outputs (glitches)?

 We will look at
 How Verilog simulations work
 How signals change with time
 How we specify delays on gates
Synthesis and Modelling

 Verilog for synthesis:

 assign c = a + b;
 Input to synthesis tool
 Written by human being
Synthesis and Modelling
 Output of synthesis tool:
 Netlist to accomplish required function
Synthesis and Modelling
 What’s this?

 Model of real-world component

 Enables simulator to predict performance of synthesized
circuit, by tracking delays of the components that build the
circuit
 To simulate timings we need to model delay
The Delay in Gates

a
b
c
10 ns

 Whenever a or b changes, c computes a new

value
 c doesn’t get this value until 10 ns later
Time units
and #(10ns)(c,b,a); // inserting delay to a gate
assign #(10ns) c = a & b;//inserting delay to assign

Unit Name Meaning

PS picosecond 10-12 seconds
NS nanosecond 10-9 seconds
US microsecond 10-6 seconds
MS millisecond 10-3 seconds
S second
Time units
module ckt2 (x,y,z);
input x,y;
output z;
wire n1, n2;

and #(10ns)g1(n1,x,y);
and #(10ns)g2(n2,n1,y);
xor #(15ns)g3(z,n2,x);
endmodule

 Smallest unit of time: delta (in case no delay was specified)

 Delta: “a moment” or “an instant”
How Verilog processes delays

 Example:
 Build a circuit from two gates
 AND gate: delay = 10 ns
 XOR gate: delay = 15 ns
 Example circuit
Example_circuit
Gates are connected where
x n1
same wire name appears in
g1 g3 z
y output list of one gate and
g2 n2 input list of another

module ckt2 (x,y,z);

input x,y;
output z;
wire n1, n2;

and #(10ns)g1(n1,x,y);
and #(10ns)g2(n2,n1,y);
xor #(15ns)g3(z,n2,x);
endmodule
 Example circuit (Another way of
Modelling delay to assign)
Example_circuit

x n1
g1 g3 z
y

g2 n2

module ckt2 (x,y,z);

input x,y;
output z;
wire n1, n2;

assign #(10ns)n1= x & y;

assign #(10ns)n2=n1 & y;
assign #(15ns)z= n2 ^ x;
endmodule
Simulation

 Give it some example inputs:

 At time zero, x=’0’ and y=’1’.
 (So n1=’0’, n2=’0’ and z=’0’.)
 At time 100 ns, x becomes ‘1’
Example_circuit

x n1
g3 0
y
g1
0 z

g2 n2
100 ns 0
How does Verilog simulate this?
 The simulator maintains an event queue. Lists
 What value each signal has now
 What value it will get in future

 Simulator advances through time, updating event queue

 Verilog simulation
Example_circuit x
0 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 0
Signal Name: x y n1 n2 z
Present value: 0 1 0 0 0
Next value: 1
Event time: 100

 Advance to time of next event on queue

 Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value:
Event time:

 All gates with x on input list recompute their outputs

 Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value: 1 1
Event time: 110 115

 Advance to time of next event on queue

 Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 110
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 0
Next value: 1
Event time: 115

 All gates with n1 on input list recompute their outputs

 Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 110
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 0
Next value: 1 1
Event time: 120 115

 Advance to time of next event on queue

 Verilog simulation
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 115
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 1
Next value: 1
Event time: 120

 All gates with z on input list recompute their outputs

 Verilog simulation
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 115
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 1
Next value: 1
Event time: 120

 Advance to time of next event on queue

 Verilog simulation
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 120
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 1
Next value:
Event time:

 All gates with n2 on input list recompute their outputs

 Verilog simulation
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 120
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 1
Next value: 0
Event time: 135

 Advance to time of next event on queue

 Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 135
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:

 Nothing left on queue: continue to end of simulation time

Verilog simulation
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 200
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:
Glitches
Example_circuit x
x n1
y
g1 g3 z
y
n1
g2 n2
n2
z
0 50 100 150 time

 For x=0, y=1 static output is 0

 For x=1, y=1 static output is also 0
 However, output goes briefly to 1: glitch
 Detecting these glitches is an important goal of
simulation
Glitches
Example_circuit x
x n1
y
g1 g3 z
y
n1
g2 n2
n2
z
0 50 100 150 time

 Glitch occurred because of gate delays

 x input to g3 settles immediately
 n2 input settles after delay of g1 and g2
 If gate delay was not modelled, glitch would not
be detected
Delta delay
 Problem:
 We don’t know delay when we are doing the
design
 If gates don’t have a delay, simulation could
be wrong
 Solution:
 We don’t specify a delay
 Verilog inserts a delay: delta for gates and
assign statements
 Delta is smallest possible instant of time
 A “moment”; an “instant”
 Example circuit
Example_circuit
Gates are connected where
x n1 same wire name appears in
g1 g3 z
y output list of one gate and
g2 n2 input list of another

module ckt2 (x,y,z);

input x,y;
output z;
wire n1, n2;

and g1(n1,x,y);
and g2(n2,n1,y);
xor g3(z,n2,x);
endmodule
 Verilog simulation:  delay
Example_circuit x
0 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 0
Signal Name: x y n1 n2 z
Present value: 0 1 0 0 0
Next value: 1
Event time: 100

 Advance to time of next event on queue

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value:
Event time:

 All gates with x on input list recompute their outputs

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value: 1 1
Event time: 100+ 100+

 Advance to time of next event on queue

Verilog simulation:  delay
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100 +
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 1
Next value:
Event time:

 All gates with n1 or z on input list recompute their outputs

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100 +
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 1
Next value: 1
Event time: 100+2

 Advance to time of next event on queue

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 100 +2
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 1
Next value:
Event time:

 All gates with n2 on input list recompute their outputs

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 1
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 100 +2
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 1
Next value: 0
Event time: 100+3

 Advance to time of next event on queue

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 100+ 3
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:

 Nothing left on queue: continue to end of simulation time

 Verilog simulation:  delay
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 200
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:

 Glitch has been correctly simulated

Verilog simulation:  delay

 In Verilog assignment always has delay:

 assign c = a + b;
is treated as if it said
 assign c = a + b AFTER delta;

 The statement runs whenever a RHS value

changes
 c computes a new value, but does not get
this value until a delta time later
 This delay ensures correct simulation
Questions
x1
x2
n1 AND gate delay 10 ns
y

n2
OR gate delay 15 ns
x3

x4

Question 1

What is the behaviour of n1, n2 and y when the inputs do this:

 Questions
(a) (b)

(c) (d) (e)

Inertial behaviour
and #(10)(c,b,a);

a
b
c
10 ns 10 ns
 c follows inputs, but with 10 ns delay
 Delay is measure of inertia
 Gate cannot respond over time periods smaller
than 10 ns
What if input pulse is too narrow?
and #(10ns)(c,b,a); // inserting delay to a gate
assign #(10ns) c = a & b; //inserting delay to assign

a
b
c
10 ns

 Gate cannot respond over time periods smaller

than 10 ns
 If input pulse is narrower than this, output does
not change: inertial behaviour
Inertial behaviour in Verilog

 In Verilog simulation, inertial situations

manifest themselves as collisions on the
event queue
 Example circuit
Example_circuit
Gates are connected where
x
g1
n1
g3
same wire name appears in
z
y output list of one gate and
g2 n2 input list of another

module ckt2 (x,y,z);

input x,y;
output z;
wire n1, n2;

and #(10ns)g1(n1,x,y);
and #(10ns)g2(n2,n1,y);
xor #(25ns)g3(z,n2,x);
endmodule
 Verilog simulation: Inertial example
Example_circuit x
0 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 0
Signal Name: x y n1 n2 z
Present value: 0 1 0 0 0
Next value: 1
Event time: 100

 Advance to time of next event on queue

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value:
Event time:

 All gates with x on input list recompute their outputs

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
0 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 100
Signal Name: x y n1 n2 z
Present value: 1 1 0 0 0
Next value: 1 1
Event time: 110 125

 Advance to time of next event on queue

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 110
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 0
Next value: 1
Event time: 125

 All gates with n1 on input list recompute their outputs

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
0
z
0 50 100 150 time
Time = 110
Signal Name: x y n1 n2 z
Present value: 1 1 1 0 0
Next value: 1 1
Event time: 120 125

 Advance to time of next event on queue

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 120
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value: 1
Event time: 125

 All gates with n2 on input list recompute their outputs

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 120
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value: 1, 0
Event time: 125, 145

 Multiple events on queue for z: later over-writes earlier

 Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 135
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:

 Nothing left on queue: continue to end of simulation time

Verilog simulation: Inertial example
Example_circuit x
1 y
x n1 0
y
g1
1 g3 z
n1
1 g2 n2
n2
1
z
0 50 100 150 time
Time = 200
Signal Name: x y n1 n2 z
Present value: 1 1 1 1 0
Next value:
Event time:
Inertial behaviour
Example_circuit x
x n1
y
g1 g3 z
y
n1
g2 n2
n2
z
0 50 100 150

 Output does not glitch

 Inputs to g3 were unequal for 20 ns
 g3 cannot output a pulse narrower than 25 ns
 Corresponds to inertial behaviour of real devices
Inertial behaviour in Verilog

 In Verilog simulation, inertial situations

manifest themselves as collisions on the
event queue
 Later event over-writes earlier event
 This ensures inertial behaviour
Questions
x1
x2
n1 AND gate delay 10 ns
y

n2
OR gate delay 15 ns
x3

x4

Question 2

What is the behaviour of n1, n2 and y when the inputs do this:

(the pulse width is 9 ns)
 Questions
(a) (b)

(c) (d) (e)

Summary

 We want to know timing behaviour of designs

 Verilog simulation
 shows how outputs respond to sequence
of inputs
 proceeds by tracking evolution of event
queue through time
 Verilog assignments always have delay, even
if we don’t specify delay
 Inertial behaviour is ensured by only allowing
one entry for each signal on event queue