Digital Logic & Timing
Propagation and Contamination Delay
Combinational logic is characterized by its propagation delay and
contamination delay.
The propagation delay tpd is the maximum time from when an input
changes until the output or outputs reach their final value.
The contamination delay tcd is the minimum time from when an input
changes until any output starts to change its value (reaction time).
tpd
a y a
tcd
Propagation Delay
a y
VDD VDD
50% 50%
VSS VSS
Propagation Delay
Critical Path
a delay
Critical Path
a=1®0 n1
n1
b=1
n2 n2
c=0
y=1®0
d=1 y
Short Path time
Short Path
delay
d
a=1 n1
y
b=1
n2
c=0
y=1®0
d=1®0 time
The causes of delay in circuits include the time required to charge the capacitance in a circuit and the
speed of light.
tpd and tcd may be different for many reasons, including different
• rising and falling delays
• multiple inputs and outputs, some of which are faster than others
• circuits slowing down when hot and speeding up when cold
Flip-Flop Delay/Check Arcs
Setup Check
D Q
Clk2Q Delay
Hold Check
CLK
Setup Check
IN Tperiod - Tsetup
F2 OUT
F1
CLK
Launch Flop Capture Flop
Launch edge
Clock at F1
Clock at F2 Ts
Capture edge
Tperiod - Tsetup
Setup Check - Latency
Tperiod - Tsetup
IN
F2 OUT
0.5ns F1
CLK
Launch Capture
Ideal clock
Launch edge
0.5ns
Clock at F1
Clock at F2 0.5ns Ts
Tperiod - Tsetup Capture edge
Setup Check – Latency (BC)
Tcapture -Tlaunch - Tsetup
IN
F2 OUT
0.5ns F1
CLK
Launch 0.5ns Capture
Ideal clock
Launch edge
0.5ns
Clock at F1
Clock at F2 1ns Ts
Tcapture -Tlaunch - Tsetup Capture edge
Setup Check – Latency (WC)
Tcapture -Tlaunch - Tsetup
IN
F2 OUT
0.5ns F1
0.5ns
CLK
Launch Capture
Ideal clock
Launch edge
Clock at F1 1ns
Clock at F2 0.5ns Ts
Tcapture -Tlaunch - Tsetup Capture edge
Setup Check – Latency (WC)
Tcapture -Tlaunch - Tsetup
IN
F2 OUT
0.5ns F1
0.5ns
CLK
Launch Capture
Launch edge
Clock at F1
Clock at F2 Ts 0.5ns
Skew
New Original
Tcapture -Tlaunch - Tsetup Capture Capture
Edge Edge
Hold Check
IN Thold⩽ Tp⩽Tperiod - Tsetup
F2 OUT
F1
CLK
Launch Flop Capture Flop
Launch edge New Launch edge
Clock at F1
Clock at F2 Ts Th
Capture edge
Hold Check – Alternate diagram
IN Thold⩽ Tp⩽Tperiod - Tsetup
Tp F2 OUT
F1
CLK
Launch Flop Capture Flop
Launch edge
Clock at F1
Clock at F2 Th Ts
Capture edge
Thold⩽ Tp⩽Tperiod - Tsetup
Hold Check - Latency
Thold⩽ Tp⩽Tperiod - Tsetup
IN
F2 OUT
0.5ns F1
CLK
Launch Capture
Ideal clock
Launch edge
0.5ns
Clock at F1
Clock at F2 0.5ns Th Ts
Capture edge
Thold⩽ Tp⩽Tperiod - Tsetup
Hold Check – Latency (BC)
Tcapture -Tlaunch - Tsetup
IN
F2 OUT
0.5ns F1
0.5ns
CLK
Launch Capture
Ideal clock
Launch edge
Clock at F1 1ns
Clock at F2 0.5ns Th Ts
Tcapture -Tlaunch - Tsetup Capture edge
Hold Check – Latency (WC)
0.5n+ Thold⩽ Tp⩽Tperiod - Tsetup
IN
F2 OUT
0.5ns F1
CLK
Launch 0.5ns Capture
Ideal clock
Launch edge
Clock at F1
Clock at F2 0.5ns 0.5ns Ts
0.5+Th
0.5n+Thold⩽ Tp⩽Tperiod - Tsetup Capture edge
False Paths
U1 U2
data1
Q A
A
F1 4ns
Y Q
1ns Y 1ns
F3
data2 Q B B
2ns 3ns
F2
clock
sel
What is the maximum delay through the combo logic? 6ns/5ns/4ns/3ns?
False Paths
U1 Logical False Path U2
data1
Q A
A
F1 4ns
Y Q
1ns Y 1ns
F3
data2 Q B B
2ns 3ns
F2
clock
sel
Critical Path = 5ns
False Paths exclusive clocks
D D D
F1 F2 F3
Sel
fclk
clk clk period fclk period
3ns 2ns
4 Possible timing paths:
1. clk to clk
2. clk to fclk <- False path
3. fclk to fclk
4. fclk to clk <- False path
False Paths – Asynchronous Clocks
D D D
F1 F2 F3
clk1 clk2 clk1
clk period fclk period
3ns 2ns
4 Possible timing paths:
1. clk to clk
2. clk to fclk <- False path
3. fclk to fclk
4. fclk to clk <- False path
Synchronization with two FFs
ASYNCIN SYNCIN
META
Di Qa D1 Q1 D2 Q2
(asynchronous
input)
clock2 CLK CLK CLK Synchronous
FF1
system
FF2
clock
(system clock)
1. Q1 can switch in the beginning of #1 cycle and Q2 will write the new value of Q1 in #2 cycle
2. FF1 appears in metastable state, its output increases and eventually reaches high level. Q2
registers accurate data in #2 cycle
Propagation Delay – Simplified Model for Setup
IN
F2 OUT
F1
CLK
F1 Launch F2 Capture
Max Propagation Delay Setup Uncertainty
Period (for single clock design)
Propagation Delay – Simplified Model for Hold
IN
F2 OUT
F1
CLK
F1 Launch
Min
Propagation Delay
Uncertainty Hold
F2 Capture
Input Delay Max)
External Block My Design
Internal Logic
IN Delay
A C D F2 OUT
F1
CLK Input
Delay
F1 Launch F2 Capture
Input Delay Internal Logic Delay Setup Uncertainty
Period (for single clock design)
Input Delay Min
F1 Launch
Input
Delay
Min Internal
Logic Delay
Uncertainty Hold
F2 Capture
Output Delay Max
My Design External Block
External Logic
IN Delay
F1 A C D F2
CLK Internal
Logic
Delay
F1 Launch F2 Capture
Internal Logic Delay External Logic Delay Setup Uncertainty
Output Delay
Period (for single clock design)
Output Delay Min
F1 Launch
Ext
Logic
Delay
Min Internal
Logic Delay
Uncertainty Hold
F2 Capture
Flip-Flop Delay/Check Arcs – Recovery/Removal
Asyn. Rst
Setup Check
D Q D Q
Clk2Q Delay Recovery Check
Hold Check
Removal Check
CLK CLK
Recovery & Removal
Asyn. RST
Ideal clock
D Q
Recovery Check
Removal Check
CLK
Tremoval Trecovery
CLK
RST
Basic Logic Circuit
NAND/NOR Gate
Multiplexers
x0
S X0 X1 y
x0 0 0 x 0 y
y
0 1 x 1 x1
x1 1 x 0 0
1 x 1 1
S S
Mux 2:1 ln Verilog
Verilog
module mux2(input [3:0] d0, d1, input s, output [3:0] y);
assign y = s ? d1 : d0;
endmodule
In SystemVerilog, internal signals are usually declared as logic.
System Verilog
module mux2(input logic [3:0] d0, d1, input logic s,
output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule
Mux 4:1
in0 u
Multiplexer 4:1
in1
v
y
in0 00
in2 w
in1 01
y
in2 10
In3
x
in3 11
a0 nota0
a1 a0
a1
nota1
Mux 4:1 Verilog Implementation
module multiplexer4_1 (y, in0, in1, in2, in3, a0, a1);
output y;
input in0, in1, in2, in3, a0, a1;
reg y;
always @ (in0 or in1 or in2 or in3 or a0 or a1)
case ({a1, a0})
2’ b00: y = in0;
2’ b01: y = in1;
2’ b10: y = in2;
2’b11: y = in3;
endcase
endmodule
module multiplexer4_1 (y, in0, in1, in2, in3, a0, a1);
output y;
input in0, in1, in2, in3, a0, a1;
assign y = a0 ? (a1 ? in3 : in1) : (a1 ? in2 : in0);
endmodule
Demultiplexer
module demultiplexer1_to_4(out,in,s);
output reg[0:3]out; out[0]
input in;
out[1]
input [1:0]s; in
out[2]
always @(s , in)
case (s) // Switch based on control signals out[3]
2'b00:out={in,3’bz};
2'b01:out={1’bz,in,2’bz};
2'b10:out={2’bz,in,1’bz}; s[0] s[1]
2'b11:out={3’bz,in};
default:out =4’bz;
endcase
endmodule
Decoders
• The function of binary decoder is to convert binary input code to unary
output code. The number of inputs is usually less than the number of
outputs.
• Binary (full) decoder: n inputs, 2n outputs (n-to-2n).
Inputs Outputs The input code word A1A0
represents an integer in range
En A1 A0 Y3 Y2 Y1 Y0 0 – 3.
0 X X 0 0 0 0
The output code word has
1 0 0 0 0 0 1 Yi=1, if A1A0 is binary
1 0 1 0 0 1 0 representation of i.
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Decoder in Verilog
module decode
(input [2:0] A, En, output reg 3’ b010: Yout = 8’ b 00000100;
DC [7:0] Yout);
y0 3’ b011: Yout = 8’ b 00001000;
y1 always @ (En or A) 3’ b100: Yout = 8’ b 00010000;
A0
y2 begin
A1 3’ b101: Yout = 8’ b 00100000;
y3
A2 if (!En) 3’ b110: Yout = 8’ b 01000000;
y4
y5 Yout = 8' b00000000; 3’ b111: Yout = 8’ b 10000000;
En y6 else default: Yout = 8’ b 00000000;
y7 case ( A ) endcase
3’ b000: Yout = 8’ b 00000001; end
3’ b001: Yout = 8’ b 00000010; endmodule
Decoder Schematic
A0
Y0
A1 Y1
Y2
En Y3
Decoder in Verilog (For Statement)
module dec4to16(a,en,y);
input [3:0] a;
input en;
output reg [0:15] y;
integer k;
always @(a or en)
for (k=0; k<=15; k=k+1)
if(a==k&&en==1)
y[k]=1;
else y[k]=0;
endmodule
Decoder in SystemVerilog
module decoder3_8(input logic [2:0] a,
output logic [7:0] y);
DC always_comb
y0
y1 case(a)
A0 y2 3’b000: y = 8’b00000001;
A1 y3 3’b001: y = 8’b00000010;
A2 y4 3’b010: y = 8’b00000100;
y5 3’b011: y = 8’b00001000;
y6 3’b100: y = 8’b00010000;
y7 3’b101: y = 8’b00100000;
3’b110: y = 8’b01000000;
3’b111: y = 8’b10000000;
default: y = 8’bxxxxxxxx;
endcase
endmodule
Encoder
• The function of binary encoder is to convert input code (unary) to output code (binary) (2n-to-n).
The number of inputs is usually more than the number of outputs.
Inputs – D0,D1, . . ., Di, . . .
Di&Dk=0; if Dk=1, yout = k.
D3 D 0D 1D 2D 3 A 1A 0 G
D2 A1 0 0 0 1 1 1 1
D1 A0 0 0 1 0 1 0 1
D0 G 0 1 0 0 0 1 1
1 0 0 0 0 0 1
0 0 0 0 0 0 0
A and B are the ordinary outputs and V is valid bit indicator.
This third output V is set to 1 when one or more inputs are equal to 1.
When all the inputs to the encoder are equal to 0, there is no any valid input, and thus the output V is set to 0.
Priority Encoder 4-to-2
After minimization
A1=D3+D2; A0=D3 + ~D2×D1;
G= A1+D1+D0;
D3 A0
D2
D1
A1
G
D0
Priority Encoder 8-to-3
module priority_encoder(data,Y, gs);
input [7:0] data;
output reg [2:0] Y;
output reg gs;
integer k;
always @(data)
begin
Y=3’ b0;
gs=0;
for (k=0; k<8; k=k+1)
if (data[k])
begin
Y=k;
gs=1;
end
end
endmodule
Priority Circuit (System Verilog)
module priority_circuit (input logic [3:0] a,
output logic [3:0] y);
always_comb
if (a[3]) y <= 4'b1000;
else if (a[2]) y <= 4'b0100;
else if (a[1]) y <= 4'b0010;
else if (a[0]) y <= 4'b0001;
else y <= 4'b0000;
endmodule
In Verilog and SystemVerilog, if statements must appear inside of
always statement
Full Adder
• The function of the full adder is to add two binary digits and a carry that
might be generated or propagated by the previous stage.
cin
Inputs Outputs s
a b cin s cout a
0 0 0 0 0 b
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 cout
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Cout=a ×b +cin×(a Åb)
Standard approach – 6 gates
Alternative Implementation
cin
s
a
b
p
g cout
g=a×b
P=cin× (aÅ b)
Full Adder
In SystemVerilog, internal signals are usually declared as logic.
module fulladder (input logic a, b, cin,
output logic s, cout);
assign {s,cout} = a + b + cin;
endmodule
Comparators
Comparator is the circuit whose function is to determine which of two binary numbers A and B is equal (or
large, less . . .).
a a b aÅb ~(aÅb)
f 0 0 0 1
b
0 1 1 0
a 1 0 1 0
f 1 1 0 1
b
XOR and XNOR can be considered as 1-bit comparators.
Verilog Description for n-bit Comparator
module compare (compout, a,b);
parameter size = 32;
output compout;
input [size-1:0] a;
input [size-1:0] b;
assign compout = (a==b);
endmodule
Comparator Circuit
Using XNOR Using NOR
4-Bit Comparator
a3
b
a23
b2
a1 A==B
b
a01
b0
A<B
A>B
Tri-State Buffers
A tri-state buffer allows multiple sources to share a single party line, as long as
only one device ”talks” at a time.
En A Y
En=0
En 0 0 Hi-Z
Y A Y
A 0 1 Hi-Z
Noninverting, active- En=1 1 0 0
high enable. A Y 1 1 1
En En En
A Y A Y A Y
Noninverting, Inverting, active- Inverting, active-
active-low enable high enable low enable
Tri-State Buffers
A
{S1S0} 3 0 1
S0 A 0
S1 B 1 E
B
2 Sdata
E 3
C D A B
Dead time
D
To avoid fighting control logic must
guarantee a dead time on the line
in which no one drives.
Tri-State Buffers
module tristate (en, a, y); Using continuous assignment and
input a, en; ternary conditional operator
output y;
reg y; module tristate (en, a, y);
input a, en;
always @ (a or en)
output y;
if (en)
y = a; assign y = en ? a : 1’bz;
else endmodule
y = 1’bz;
endmodule
Tri-State Example
sb0
sb1
Bus
sb2 rb0
rb3 rb2 rb1
sb3
DC DC
Source Dest.
address address
Alternative Implementation with MUX
src0
src1
Bus
MUX
src2
En1 En2
srcsel
DMX dstsel
src3
dst3 dst2 dst1 dst0
Parity Circuit
Daisy-chain connection
in1
in2
in3
in4
in5
in6
in7
in8 odd
Y=in1Åin2Åin3Åin4Åin5Åin6Åin7Åin8
T = (n-1)t, where t - one XOR-gate delay
Parity Structure
Tree structure
in1
in2
in3
in4
odd
in5
in6
in7
in8
T = élog2nù t The tree structure is faster.
Parity Circuit using Verilog
module parity_using_function (
data_in , parity_out);
output parity_out ;
input [31:0] data_in; module parity_using_reduction
wire parity_out ; (data_in , parity_out );
function parity;
output parity_out ;
input [31:0] data;
integer i; input [31:0] data_in ;
begin parity = 0; assign parity_out = ^data_in;
for (i = 0; i < 32; i = i + 1) endmodule
begin parity = parity ^ data[i];
end
end
endfunction
always @ (data_in)
begin
parity_out = parity(data_in); end
endmodule
Recursive Function
function automatic [31:0] fac;
input [15:0] n;
if (n == 1)
fac = 1;
else
fac = n * fac(n-1); //recursive function call
endfunction
Fibonacci Sequence 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55 …
module Fibonacci (clk, rst, fibout) ;
input clk, rst;
output [31:0] fibout;
reg [31:0] prev, curr;
always @(posedge clk, negedge rst)
begin
if (!rst)
begin
prev <= 0;
curr <= 1;
end
else
begin
prev <= curr;
curr <= curr + prev;
end
end
assign fibout = prev;
endmodule
