IC OVERVIEW
RTL DESIGN AND VERIFICATION
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COURSE INTRODUCTION
Khóa Học Thiết Kế Vi Mạch Cơ Bản - Trung Tâm Đào Tạo Thiết Kế Vi Mạch ICTC
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COURSE INTRODUCTION
SUMMARY
HOMEWORK
QUESTION
SELF-LEARNING
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Session 11: Verilog
Fundamental – Part 5 – 1. Initial block
Verilog For Verification 2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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SYMBOL MEANING
SUMMARY
HOMEWORK
QUESTION
SELF-LEARNING
5
1. Initial block
2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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Initial Block
▪ Initial block is procedural block.
▪ Initial block is enabled at time 0 and is executed only once until all statements are finished.
initial
statement0
initial begin
statement1
Statement1 is
statement2 executed at time 0.
statement3 Statements are
end executed in-order.
▪ Statement0 and statement1 are executed at time 0. Which one is executed first is based on tool
vendor.
▪ Initial block is un-synthesizable. It is often used for simulation purpose.
▪ Initial block MUST be written inside module.
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Initial Block And Delay Statement
▪ Use delay statement (#) in initial block to generate timing dependencies.
▪ Below 2 initial block run parallel at time 0.
▪ The first initial block finishes first. The second initial block finishes after 90ns and terminate the
simulation
module tb
[0ns ]: a gets value 0
reg a; [10ns]: a gets value 1
initial begin
a = 0; [40ns]: a gets value 0
#10 a = 1; [90ns]: end simulation
#30 a= 0;
end
initial begin
#90 $finish;
end What if the second initial block as the delay of 30ns only?
endmodule
$finish is a Verilog system task that tells the simulator to end the current simulation.
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Initial Block And Delay Statement
Questions: what’s the value of a[1:0] at 0ns, 10ns, 20ns, 30ns?
reg [1:0] a;
initial begin
a <= 2’b00;
a <= #20 2’b01;
a <= #10 2’b10;
end
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Initial Block And Delay Statement
Questions: what’s the value of a[1:0] at 0ns, 10ns, 20ns, 30ns?
reg [1:0] a;
initial begin [0ns ]: a[1:0] gets value 2’b00
a <= 2’b00; [10ns]: a[1:0] gets value 2’b10
a <= #20 2’b01; [20ns]: a[1:0] gets value 2’b01
a <= #10 2’b10; [30ns]: a[1:0] keeps value 2’b01
end
Do not use non-blocking assignment in the initial block
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Initial Block And Delay Statement
Practice: generate below waveform in testbench using initial block.
Clock period is 100ns
Simulation END
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INITIAL VS ALWAYS
Initial Always
In this, each block assignments continues to
In this, each block assignment executes in
execute in simulation time 0 and repeats
the 0 simulation time and continues for the
forever depending on the sensitivity list
next specified sequence
event
The simulation in this block continues
This block is executed only once forever. If wait construct is there then it will
be held during simulation session
It is non-synthesizable construct It is synthesizable construct
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Wait and @
Beside “#”, we have other timing control method: “wait” or “@”
▪ wait statement:
o Syntax: wait (condition)
o Wait statement pause the execution of current procedure until the condition is true.
▪ @: event control operator
o Syntax: @(event expression)
o Used to wait for specific events occur, such as changes in signal values.
initial begin initial begin
… …
wait( ready == 1’b1); //wait ready become 1 before sending data @( posedge clk); //wait clk rising edge
send_data(…); …
end @(data); //wait for any change in data
end
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1. Initial block
2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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FOR LOOP
▪ For loop can be used in initial block.
▪ Syntax:
for (initial_condition; condition; step_assignment) begin
..statement..
end
module test_bench; Current loop 0
integer i; Current loop 1
Current loop 2
initial begin
…
//Note that i++ operator does not exist in Verilog,
//Only support in Systemverilog Current loop 9
for(i = 0; i<10; i=i+1) begin
$display(“Current loop %0d”,i);
end
end
endmodule
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REPEAT
▪ Repeat can be used in initial block, to execute a set of statemens N times.
▪ Syntax:
repeat (number)
Single statement initial begin Clock of above
clk = 0; practice can be
#50; generated using
repeat (number) begin repeat
repeat (6) #50 clk = ~clk;
Multiple statements end
end
initial begin
…
repeat (5) @(posedge clk); Wait 5 posedge clk
… Then do something
end
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WHILE
▪ While are looping constructs that execute the given set of statements as
long as the condition is true
▪ Syntax: initial begin cnt = 0
while( cnt < 10) begin cnt = 1
while (condition) begin $display(“cnt = %d”, cnt);
cnt = 2
[statements] cnt = cnt+1;
end …
end
$display(“End loop”); cnt = 9
end End loop
initial begin
while( data_valid == 1’b0); Wait data_valid signal = 1’b1
Then continue
$display(“data is valid”);
end
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1. Initial block
2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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TASK
▪ Function is meant to do some processing on the input and return a single
value, while a task can have multiple output.
▪ Can define tasks in two ways as below
task task_name; task task_name (
input_declaration; input <range> arg1,
output_declaration; output <range> arg2,
inout_declaration; ….
These are );
begin equivalent begin
[statements] [statements]
end end
endtask endtask
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TASK
▪ Different with function, task can have timing control statements (“#” or
“@” or “wait”) inside.
task delay_100ns;
input a; Output y is delayed 100ns than
output y; input a
begin
#100 y = a;
end
endtask
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TASK INVOKE
module tb;
reg in; Task need to be called inside procedure.
reg out;
Output of tasks are given value when the
initial begin
task completed. Then if you read “out”
between 100ns and 200ns, it will return 0.
in = 0;
out = 0;
#100 in = 1;
delay_100ns( in, out); //task invoked
end
task delay_100ns;
input a; Task need to be declared inside module
output y;
begin
#100 y = a;
end
endtask
endmodule
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TASK VS FUNCTION
Function Task
Can not have time, executes in the same simulation time Consume simulation time
unit
Can not enable a task Can enable others task and functions
Should have at least one input argument and can not Can have zero or more arguments of any type
have output or inout arguments
Can return only a single value Can not return a value but can achieve the same effect
using output arguments
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TASK PRACTICE
Practice: Create a task to perform swapping between two 8-bit reg variables .
Hint: need to use “inout” so that value can be swapped directly.
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VERILOG SYSTEM TASK
The system tasks are used to perform some operations like displaying the messages, terminating
simulation, generating random numbers, etc
System task Description
To display strings, variables, and expressions immediately in the
$display
active region.
To monitor signal values upon its changes and executes in the
$monitor
postpone region.
To display strings, variables, and expressions at the end of the
$strobe
current time slot i.e. in the postpone region.
$finish End simulation
$random Return a random 32-bit integer
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VERILOG SYSTEM TASK FORMAT
The display system tasks use various format specifiers to print the values
Format specifiers Description
%c To display ASCII character
%s To display string
%t To display the current time
%f To display real numbers in decimal format. (Ex. 3.14)
%e To display real numbers in scientific format. (Ex. 2e20)
%x To display hexa number
%o To display octal number
%d To display decimal number
%b To display binary number
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COMPILER DIRECTIVE
We already learn `define, `include, `ifdef in previous session
Compiler directives Description
`define To define text macros (Similar #define in C language
`include To include entire content from another Verilog file into
existing file during compilation
`ifdef ...`endif Conditional compiler directives that behave as if…else
`ifdef ...`else ...`endif conditional statement
`timescale To specify time units and precision for the module
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TIMESCALE
▪ Verilog simulation depends on how time is defined.
▪ The `timescale compiler directive specifies the time unit and precision for the simulation.
▪ Syntax: `timescale <time_unit>/<time_precision>
`timescale 1ns/1ps
`timescale 10us/100ns
▪ The time_unit is the measurement of delays and simulation time while the time_precision specifies how
delay values are rounded before being used in the simulation.
`timescale 1ns/1ns `timescale 1ns/1ps
… …
initial begin initial begin
#1 $display(“T=%t at time #1”, $realtime); //result is 1 #1 $display(“T=%t at time #1”, $realtime); //result is 1000
#0.49 $display(“T=%t at time #1”, $realtime); //result is 1 #0.49 $display(“T=%t at time #1”, $realtime); //result is 1490
#0.5 $display(“T=%t at time #1”, $realtime); //result is 2 #0.5 $display(“T=%t at time #1”, $realtime); //result is 1990
#0.51 $display(“T=%t at time #1”, $realtime); //result is 3 #0.51 $display(“T=%t at time #1”, $realtime); //result is 2500
end end
… …
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1. Initial block
2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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TESTBENCH
▪ A test bench is a program which generate inputs to DUT and observe the output.
▪ A test bench does not have to be synthesized. Hence, we can use all features of Verilog
programming on the test bench development.
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TESTBENCH
▪ Testbench diagram for an OR gate module
module or_gate (a,b,z);
input wire a;
tb
input wire b;
output wire z; or_gate
Input tb_a a
z tb_z Output
control tb_b b control
assign z = a | b;
logic logic
endmodule
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TESTBENCH
module tb ;
▪ Example of test bench for an OR gate module wire tb_a, tb_b, tb_z;
or_gate u_dut (.a( tb_a ), .b( tb_b ), .z ( tb_z ));
tb initial begin
tb_a = 0;
tb_b = 0;
#10;
or_gate $display(“Case 1: a=%b b=%b”,tb_a, tb_b);
Input tb_a a
z tb_z Output if( tb_z === 0 ) begin
control tb_b b control $display(“PASSED);
logic logic end else begin
$display(“FAILED. Exp: 0 Actual: %b”, tb_z);
$finish;
end
#10;
tb_a = 0;
tb_b = 1;
$display(“Case 2: a=%b b=%b”,tb_a, tb_b);
….
end
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endmodule
TESTBENCH USING GOLDEN MODEL
Golden model is a no-timing program, which generates the expected result
DUT
Pattern
generator
Golden
model
Checker
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1. Initial block
2. Loop
3. Task
.
4. Testbench
5. DV flow recap
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REVIEW DV DESIGN FLOW
Let’s review again the DV Flow and see how we can apply into this course
Identify Verification Scope - Scope: unit test only
and Method
- Method: direct test only
- Analyze requirement from
Design Requirement
the practice / homework Analysis
Create Verification - Verification plan only
Specification and Plan
- Build direct test environment Build Test Environment and
- Write testcase based on Test Case (Scenario)
verification plan - Compile
Run Simulation and Debug - Run simulation
- Debug result
- Analyze and improve Check and Improve
coverage Coverage
- Review and feedback by
Verification Review instructor 34
VERIFICATION PLAN EXAMPLE
Let’s see again our previous counter example.
The later projects in this course need to follow this style.
clk
reset_n count_overflow
count_en counter count[7:0]
count_clr
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VERIFICATION PLAN EXAMPLE
▪ Test bench hierrachy
tb
clk
clk/reset gen reset_n overflow
dut
counter monitor
count_en count[7:0]
Stimulus gen count_clr
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VERIFICATION PLAN EXAMPLE
▪ Verification item list example. Later on it should be written in excel
ID Item name Description
1 cnt_init After reset is released, the counter initial value is 8’h00 and remain the same while counter_en is
0.
2 cnt_up When “counter_en” is High, counter start counting up.
3 cnt_stop When “counter_en” is negated from High to Low, the counter stops and remain the same value.
When “counter_en” is resumed from Low to High, the counter can resume counting from the stop
value
4 cnt_clr When “counter_clr” is High, counter is cleared to 8’h00, regardless of “counter_en” value
(counter_clear has higher priority).
5 cnt_reset When rst_n is asserted during operating, the counter is initialized to 8’h00.
6 cnt_overflow The overflow flag is asserted when counter reached 8’hff and negated to Low in 1 cycle.
The counter is initialized to 8’h00 and count up normally after overflow (if counter_en is still High).
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VERIFICATION PLAN EXAMPLE
The recommended verification item list.
The more detail of the verification item list, the more chance to find bugs of the design
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Session 11
Homework1: Write tb to realize below waveform
A BUS protocol include master and slave. Master send read/write request, slave receive the request.
Write master read/write logic using Verilog task to realize below waveform (for master only)
▪ Clock frequency is 200Mhz. All signals need to be generated based on clock using “@” operator.
▪ Master write task: generate paddr[15:0], pwrite, psel, penable, pwdata[31:0]: value of paddr & pwdata can be any value.
Initial value of all master signals are 0.
▪ Master read task: generate paddr[15:0], pwrite, psel, penable: value of paddr can be any value
▪ Don’t need to care PREADY & PRDATA in the below waveform. Initial value of all master signals are 0.
▪ Hint: must wait for clock edge to drive the master signals.
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Session 11
Homework2(*): add slave logic
▪ Slave has pready signal indicates the transfer is completed.
▪ Pready is 1 immediately or sometimes after both psel and penable is 1 (this perid can be randomize)
▪ When master write (pwrite = 1), only when slave’s pready is 1, master signals: psel, penable, pwrite,
pwdata are negated as the waveform
▪ When master read (pwrite = 0), only when slave’s pready is 1, master signals psel, penable, pwite are
negated as the waveform, slave generate prdata[31:0] and master read task print out prdata[31:0]
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