EE/CSE371 SystemVerilog Quick Reference Sheet
Max Arnold, Justin Hsia
Signal Basics Module Definition
logic var1; // single-bit wire/value // separate port list and declarations
logic [7:0] var2; // 8-bit packed array (bus) module calculate (in1, in2, out1);
input logic in1;
4'b1101 // 4-bit constant (equivalently: 4'd13, 4'hD)
input logic [3:0] in2;
{expr1, ..., exprN} // concatenation output logic out1;
{6{expr}} // replication <code>
endmodule
parameter [1:0] S_idle = 2'd0; // named parameter
enum {S_0, S_1} state; // enumerated state variable // combined port list and declarations
module calculate (input logic in1,
Basic Operators input logic [3:0] in2,
~, &, |, ^, ~&, ~|, ~^ // Boolean operators output logic out1);
!, &&, ||, == // logical operators <code>
assign out = expr; // continuous assignment endmodule
cond ? true_expr : false_expr // ternary operator module calculate_testbench (); // no ports for
<testbench code> // testbenches
endmodule
begin // start of code block, '{' in C/Java
<code>
Module Instantiation
end // end of code block, '}' in C/Java logic sig1, sig2; // by position (discouraged)
calculate c1 (sig1, sig2);
if, else, for, while // syntax similar to C/Java
logic in1, out1; // implicitly by name
case (state) // case has no fallthrough calculate c2 (.in1, .out1);
2'd0: <code> // constant specified
S_1: <code> // named value specified logic sig1, sig2; // explicitly by name
default: <code> // catch-all case calculate c3 (.in1(sig1), .out1(sig2);
endcase logic in1, sig1, out1; // match all remaining by name
repeat (num) <statement>; // repeat num times calculate c4 (.*);
calculate c5 (.in1(sig1), .*);
Procedural Blocks
always_comb begin // for combinational logic
Module Parameterization
var1 = var2 | var3; // blocking assign (=) module calc #(parameter width=4) // parameter list
end ( <port list> );
<code>
always_ff @(posedge clk) begin // for sequential logic endmodule
var1 <= var2 | var3; // non-blocking assign (<=)
end calc #(8) c6 (.*); // positional param
calc #(.width(8)) c7 (.*); // explicit param
initial // starts at beginning of simulation
Testbench Timing Controls Generate Statement
// Note: oftentimes <statement> is empty genvar i;
generate
#10 <statement>; // wait 10 time units
for (i = 0; i < 16; i++) begin : label1
#(num) <statement>; // wait num time units
// structures to be generated go here, including
// wait until next rising edge of clock // modules, always blocks, and assign statements.
@(posedge clk) <statement>; module1 m1 (.in(arr[i]), .out(outArr[i]));
always_ff @(posedge clk)
Testbench Simulated Clock <code>
logic clk; end
parameter CLOCK_PERIOD = 10; // arbitrary choice endgenerate
initial begin
clk <= 0;
forever #(CLOCK_PERIOD/2) clk <= ~clk;
end
System Tasks for Simulation
// outputs once when encountered (+newline)
// outputs once when encountered (no newline)
// outputs anytime one of its signal changes (+newline)
// returns current time (in time format)
$time
// interrupts simulation (for examination)
$stop;
Format String Escape Sequences
"%0b %0h %0d" // binary, hex, decimal
"%1.2f %1.2e" // real (decimal), real (scientific)
"%c %s" // ASCII character, string
"%0t" // time format
