Introduction to Hardware Description Languages (HDL)

Course Description
This course provides an introduction to Hardware Description Languages (HDL),
focusing on the design and implementation of digital systems. Students will learn
the fundamental principles of HDLs, particularly Verilog and/or VHDL, and their
application in modeling, simulating, and synthesizing digital hardware. Emphasis
will be placed on FPGA-based implementation and testing of digital designs.

Course Objectives
1. By the end of the course, students should be able to:
2. Understand the basic syntax and semantics of Verilog and/or VHDL.
3. Design combinational and sequential circuits using HDL.
4. Simulate and verify digital designs using industry-standard tools.
5. Implement and test designs on FPGA development boards.
6. Apply HDL principles in solving real-world digital design problems.

Course Outline

Lecture Topics
1. Introduction to Hardware Description Languages
 Overview of HDL (Verilog/VHDL)
 Advantages of HDL over schematic-based design
 Design flow and toolchain

2. Basics of Verilog/VHDL Syntax

 Data types, operators, and constructs
 Structural, behavioral, and dataflow modeling

3. Modeling Combinational Circuits

 Logic gates and Boolean expressions
 Multiplexers, decoders, encoders, and arithmetic circuits

4. Sequential Circuits
 Flip-flops, latches, and registers
 Counters and finite state machines (FSMs)
5. HDL Simulation and Debugging
 Writing testbenches
  Simulation tools and waveform analysis

6. Synthesis and Implementation

 Design constraints and optimization
 FPGA architecture and programming

7. Advanced Topics
 Parameterized modules
 Memory modeling
 Interface protocols (e.g., UART, SPI)

Laboratory Activities
1. Introduction to simulation tools (ModelSim, Vivado, etc.)
2. Basic circuit simulation and debugging
3. Combinational circuit design and implementation
4. Sequential circuit design and testing
5. FPGA configuration and testing
6. Capstone project: Design, simulate, and implement a real-world digital
system.

Assessment Methods
 Class Participation: 10%
 Assignments and Quizzes: 20%
 Laboratory Work: 30%
 Midterm Exam: 20%
 Final Project and Presentation: 20%

Learning Resources
Textbooks
1. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis
2. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with
Verilog Design

References
1. IEEE Standard for Verilog Hardware Description Language
 2. User manuals and documentation for FPGA development tools

Policies
 Attendance: Students must attend at least 80% of the classes to pass.
 Deadlines: Assignments and projects must be submitted on or before the
specified deadlines.
 Academic Integrity: Plagiarism and cheating will result in disciplinary actions.
 Safety: Follow all safety protocols during laboratory sessions.

Week 1: Introduction to Hardware Description Languages

 Objective: Understand the purpose and benefits of HDLs.
  Topics:
1. Overview of HDLs (Verilog/VHDL).
2. Comparison of HDL with schematic-based design.
3. Design flow and toolchain introduction.

 Materials: Lecture slides, examples of HDL projects.

 Activities:
1. Discussion on digital design challenges and HDL's role.
2. Explore design tools used in the course.

 Assignment: Write a summary on the advantages of HDLs and the typical

design flow.

Lab 1: Tool Setup and Introduction

 Objective: Install and configure HDL tools.
 Activities:
1. Install simulation software (e.g., ModelSim).
2. Perform a basic walkthrough of the environment.
 Output: Screenshot of successfully set up environment.

Reporters:
 Robel Sagranada
 Aaron Quijano

Week 2: Basics of Verilog/VHDL Syntax

 Objective: Familiarize with HDL syntax and structure.
  Topics:
1. Data types, operators, and constructs.
2. Hierarchical design: Modules and instances.
3. Behavioral vs structural modeling.

 Materials: Code examples, reference materials.

 Activities:
1. Analyze basic Verilog/VHDL examples.
2. Interactive coding session.

 Assignment: Write a Verilog code snippet for a 2-input AND gate.

Lab 2: Basic Circuit Simulation

 Objective: Simulate simple combinational circuits.

 Activities:
1. Simulate a 2-input AND gate.
2. Verify output using a waveform viewer.

 Output: Simulation report and waveform screenshot.

Reporters:
 Jaimiel Sipat
 Christopher Custona
 Jordan Basalo

Week 3: Modeling Combinational Circuits

 Objective: Apply HDL to design combinational logic.

 Topics:
1. Logic gates, multiplexers, decoders, and adders.
2. Boolean equations to HDL conversion.
  Materials: Truth tables, HDL examples.

 Activities:
1. Step-by-step coding of a 4:1 multiplexer.
2. Group activity: Simulate and verify designs.

 Assignment: Implement and simulate a 3-bit binary adder in HDL.

Lab 3: Combinational Circuit Implementation

 Objective: Design and test combinational circuits.

 Activities:
1. Implement a 4:1 multiplexer.
2. Verify functionality using test inputs.

 Output: Simulation results and a working design.

Reporters:
 Eds Buhian
 Grace Paredes

Week 4: Flip-Flops, Registers, and Basic Sequential Circuits

 Objective: Understand the fundamental building blocks of sequential
circuits.

 Topics:
1. Flip-flops (D, T, JK): Functionality and HDL modeling.
2. Registers and their role in digital systems.
3. Clocking and timing considerations.
  Materials: Timing diagrams, HDL examples.

 Activities:
1. Code and simulate various flip-flop types.
Implement a shift register in HDL.

 Assignment: Write HDL code for a 4-bit shift register and simulate its
operation.

Lab 4: Flip-Flop and Register Implementation

 Objective: Simulate and verify basic sequential building blocks.

 Activities:
1. Write HDL models for D, T, and JK flip-flops.
2. Simulate a 4-bit shift register in HDL.

 Output: Simulation waveforms of flip-flops and shift registers.

Reporters:
 Kyla Ocampo
 Ian Sibuma

Week 5: Counters and Finite State Machines (FSMs)

 Objective: Design more complex sequential circuits using FSMs.

 Topics:
1. Asynchronous and synchronous counters.
2. FSM design: Mealy vs Moore machines.
3. State diagrams and HDL implementation.
  Activities:
1. Design a 4-bit up/down counter.
2. Create and simulate an FSM for a traffic light controller.

 Assignment: Document and submit the HDL design for an FSM-based

vending machine.

Week 5: Counter and FSM Design

 Objective: Implement and simulate counters and FSMs.

 Activities:
1. Code and simulate a 4-bit synchronous counter.
2. Design and verify a state machine for an elevator control system.

 Output: FSM simulation results with accompanying state diagrams.

Reporters:
 Al Francis Babia
 Kier Vasquez

Week 6: HDL Simulation and Debugging

 Objective: Write and debug testbenches.

 Topics:
1. Simulation tools and methodologies.
2. Waveform analysis.

 Materials: Tool documentation, sample testbenches.

 Activities:
 1. Hands-on debugging of given HDL codes.
2. Analyze waveforms for errors.

 Assignment: Develop a testbench for the FSM designed previously.

Lab 6: FPGA Programming

 Objective: Implement HDL designs on FPGA hardware.
 Activities:
1. Synthesize and load a binary counter on an FPGA.
2. Test using on-board switches and LEDs.
 Output: FPGA demonstration video or live presentation.

Reporters:
 Lester Arcon
 Ruiz Medina

Week 7: Synthesis Process and Constraints

 Objective: Explore synthesis and constraints in HDL design for FPGA.

 Topics:
1. Synthesizable vs non-synthesizable HDL constructs.
2. Design constraints: Timing and area.
3. Introduction to FPGA architecture.

 Activities:
1. Optimize a combinational circuit for speed and area.
2. Analyze the impact of constraints using synthesis tools.
  Assignment: Optimize and synthesize a 4-bit ripple-carry adder for FPGA.

Week 7: Synthesis and Constraint Optimization

 Objective: Apply synthesis techniques and analyze results.

 Activities:
1. Synthesize a 4-bit adder with FPGA tools.
2. Apply timing and area constraints to optimize the design.
3. Compare resource utilization and timing reports.

 Output: Optimized design files and synthesis reports.

Reporters:
 Jude Paglinawan
 Third Aragon

Week 8: FPGA Design Flow and Programming

 Objective: Implement and test designs on FPGA.

 Topics:
1. Steps in the FPGA design flow: Synthesis, place, route, and programming.
2. FPGA resources: CLBs, LUTs, DSPs, and I/Os.
3. Debugging on FPGA hardware.

 Activities:
1. Implement a binary counter on FPGA.
2. Test the counter using board switches and LEDs.

 Assignment: Implement and demonstrate the traffic light controller FSM on

FPGA.
Week 8: FPGA Programming and Debugging
 Objective: Implement designs on FPGA hardware and test functionality.

 Activities:
1. Load and test the binary counter design on FPGA.
2. Debug FPGA designs using LEDs and switches.

 Output: Working FPGA implementation with testing logs.

Reporters:
 Joseph Jeremy Garcia
 Christian Ponce

Week 9: Parameterized Modules and Memory Modeling

 Objective: Understand parameterized modules and memory components in
HDL.

 Topics:
1. Parameterization: Benefits and syntax.
2. Designing reusable modules with parameters (e.g., configurable
counters).
3. Memory modeling: ROM, RAM, and FIFOs.
4. Memory interfaces and timing considerations.

 Activities:
1. Analyze HDL examples of parameterized counters and memory modules.
2. Discuss challenges in memory design for FPGAs.
  Assignment: Design a parameterized 4-bit counter with reset and enable
signals.

Week 9: Parameterized Modules and Memory Simulation

 Objective: Simulate and verify parameterized designs and memory modules.

 Activities:
1. Design a parameterized counter (e.g., configurable bit width and
direction).
2. Simulate a simple memory module (e.g., an 8x8 RAM with read/write
functionality).
3. Verify memory operations using waveforms and debugging tools.

 Output:
1. Parameterized counter HDL file and simulation results.
2. Memory module HDL file, simulation waveforms, and debug logs.

Reporters:
 Mike Bryan Simpan
 Josh Xyrus Nocon

Week 10: Communication Interfaces and Protocols

 Objective: Implement and test digital communication protocols in HDL.

 Topics:
 1. Overview of UART, SPI, and I2C protocols.
2. HDL implementation of UART: Transmitter and receiver design.
3. Verifying protocol functionality using testbenches.
4. Interfacing an HDL-based UART module with FPGA and external devices.

 Activities:
1. Analyze a UART transmitter HDL code.
2. Discuss debugging techniques for communication protocols.

 Assignment: Write and simulate HDL for a UART receiver

Week 10: UART Protocol Implementation and FPGA Testing

 Objective: Design, simulate, and implement a UART-based communication
system.

 Activities:
1. Implement a UART transmitter and receiver in HDL.
2. Simulate the UART system to verify data transmission and reception.
3. Load the UART design onto FPGA and interface with a PC using a serial
terminal tool (e.g., PuTTY).
4. Test UART functionality by sending and receiving messages.

 Output:
1. Working UART design files, simulation results, and FPGA test logs.
2. Captured screenshots of successful communication via serial terminal.

Revised Lesson Plan

Week 1: Introduction to Hardware Description Languages (HDL)

Lecture Topics
 Overview of HDL: Verilog and VHDL.
 Advantages of HDL over schematic-based design.
 The digital design flow and toolchain.

Learning Objectives
 Understand the role of HDL in digital design.
 Explain the design flow from coding to FPGA implementation.

Laboratory Activity
 Install HDL simulation tools (ModelSim).
 Familiarization with the HDL environment.
Output: Successfully installed and configured HDL tools.

Week 2: Basics of Verilog/VHDL Syntax

Lecture Topics
 Verilog and VHDL syntax and structure.
  Data types, operators, and basic constructs.
 Modules, entities, and architectures.

Learning Objectives
 Write simple HDL modules using correct syntax.
 Understand how modules are structured.

Laboratory Activity
 Write and simulate a basic HDL module (e.g., AND gate, OR gate).
 Debug errors and analyze waveforms.

Output: HDL implementation of basic gates with successful simulation.

Week 3: Combinational Circuit Design

Lecture Topics
 Modeling combinational circuits.
 Boolean expressions, multiplexers, decoders, and arithmetic circuits.
  Structural, behavioral, and dataflow modeling.

Learning Objectives
 Model and simulate combinational logic circuits.
 Compare structural, behavioral, and dataflow descriptions.

Laboratory Activity
 Write and simulate Verilog/VHDL code for a 4-to-1 multiplexer and 2-to-4
decoder.
 Test combinational logic using waveform analysis.

Output: HDL implementations of a multiplexer and decoder.

Week 4: Sequential Circuit Basics

Lecture Topics
 Introduction to sequential circuits.
 Flip-flops: SR, D, JK, and T.
  Latches and registers.

Learning Objectives
 Understand the operation of flip-flops and registers.
 Design basic sequential components in HDL.

Laboratory Activity
 Implement D flip-flop and JK flip-flop in HDL.
 Simulate the behavior of a 4-bit register.

Output: Simulated HDL implementations of flip-flops and registers.

Week 5: Finite State Machines (FSM)

Lecture Topics
 Basics of FSM: Mealy and Moore models.
 Designing FSMs in HDL.
 Applications of FSMs in digital systems.
Learning Objectives
 Model FSMs in Verilog/VHDL.
 Simulate and analyze FSM behavior.

Laboratory Activity
 Implement a simple FSM (e.g., traffic light controller) in HDL.
 Test and debug using waveform simulation.

Output: HDL implementation and simulation of a traffic light controller.

Week 6: Testbenches and Simulation

Lecture Topics
 Writing testbenches for HDL designs.
 Understanding simulation results: waveforms and timing.
 Debugging techniques.
Learning Objectives
 Develop testbenches to verify HDL designs.
 Debug and analyze simulation outputs.

Laboratory Activity
 Create a testbench for an FSM design.
 Verify functionality and troubleshoot errors.

Output: HDL testbench and functional simulation of FSM.

Week 7: Synthesis and Implementation

Lecture Topics
 Synthesis process and constraints.
 Basics of FPGA architecture.
 Mapping HDL designs to FPGA hardware.

Learning Objectives
  Synthesize HDL designs for FPGA implementation.
 Understand the role of design constraints.

Laboratory Activity
 Synthesize a 4-bit counter and generate a bitstream for FPGA programming.
 Load and test the design on an FPGA board.

Output: FPGA-implemented 4-bit counter.

Week 8: Parameterized Modules and Memory Modeling

Lecture Topics
 Parameterized modules: Generalizing HDL designs.
 Modeling RAM and ROM in HDL.

Learning Objectives
 Use parameters to create flexible HDL designs.
 Model and simulate basic memory components.
Laboratory Activity
 Create a parameterized N-bit adder in HDL.
 Model and simulate a 4x4 RAM.

Output: Parameterized adder and simulated RAM module.

Week 9: Interface Protocols and Final Project Preparation

Lecture Topics
 Overview of interface protocols: UART, SPI, I2C.
 Using HDL to implement simple communication protocols.
 Guidelines for final project development.

Learning Objectives
 Implement basic communication protocols in HDL.
 Begin planning and prototyping the final project.
Laboratory Activity
 Implement a UART transmitter and receiver in HDL.
 Begin prototyping the final project.

Output: Simulated UART design and initial project documentation.

Week 10: Final Project Presentation

Activity:
 Present and defend final projects that integrate multiple HDL concepts (e.g.,
a simple processor or a control system).

Output: Completed final project and presentation.