SCHOOL OF ENGINEERING AND TECHNOLOGY
ELECTRONIC ENGINEERING DEPARTMENT
Course Title: Digital Devices and Systems
Course Code: EEE 2103
Course Facilitator: Eng. R. Duri
[email protected]COURSE DESCRIPTION
Building upon the foundation of digital electronics and computer organization and
architecture, this course delves deeper into the design and implementation of digital systems.
It emphasizes the practical application of theoretical concepts through hands-on experience
with hardware description languages (HDLs) and programmable logic devices (PLDs).
Course Objectives
Master the fundamentals of digital system design.
Develop proficiency in hardware description languages (HDLs) for modelling and
simulating digital circuits.
Gain hands-on experience with programmable logic devices (PLDs) for rapid
prototyping.
Understand the principles of finite state machines (FSMs) and their applications.
Apply acquired knowledge to design and implement complex digital systems.
Course Learning Outcome
At the end of this course the student should be able to:
Understand how to describe a digital system using a Hardware Description
Language.
Model complex combinational logic in Verilog.
Model complex sequential logic in Verilog including state machines and counters.
Incorporate pre-existing logic cores into your Verilog design.
Understand the HDL design flow including synthesis and place/route and its effect
on timing.
Perform logic simulations on your digital designs (pre and post synthesis
Prototype digital systems on an FPGA.
ASSESSMENT
Students shall be assessed on:
Theoretical coursework made up of three assignments and two tests – 15 %
Practical coursework- 25%
An end of semester examination – 60%
LECTURE ETHICS
Students with less than 50% in coursework marks will not be allowed to write the final
exam.
Any form of plagiarism in any assignment, test, practical and the final exam will have
the results of all students involved nullified. Honesty and professionalism are encouraged.
If a student is absent for more than 80% of the lectures, he/she will not be allowed to
write the exam.
No student is allowed in the lecture room 15 min after the lecturer has begun the lecture.
Submit assignments as scheduled. No late assignments will be accepted. In some cases
typed assignments and/or softcopies are required for submission, format of presentation
required is font type Times New Roman, font size 12, spacing 1.5, and justified text.
A continuous assessment test is a “must sit” requirement and should be taken seriously
like the final examination.
COURSE OUTLINE
UNIT I: Introduction to Hardware Description Languages (HDLs)
Overview of HDLs: VHDL and Verilog
HDL syntax and structure
Verilog Data Types
UNTIT II: MODELING COMBINATIONAL CIRCUITS USING VERING
Modelling digital components: gates, flip-flops, registers
Design of combinational and sequential circuits using HDLs
Simulation and verification techniques
UNIT III: Finite State Machines (FSMs)
Introduction to FSMs
FSM design methodologies: Moore and Mealy models
UNIT IV: STATE MINIMIZATION TECHNIQUES
State reduction techniques
FSM implementation using HDLs
FSM applications: controllers, sequencers
Modelling FSM using Verilog
UNIT V: Programmable Logic Devices (PLDs)
Introduction to PLDs: PROM, PAL, PLA, FPGA and CPLD architectures
Design flow for PLD-based systems
HDL synthesis for PLDs
Timing constraints and optimization
Case studies of PLD-based designs
UNIT VI: Digital System Design and Implementation
Top-down design methodology
Hierarchical design
Design for testability
Timing analysis and optimization
Real-world design examples (e.g., digital clocks, traffic lights, microprocessors)
Course Assessment
Students shall be assessed on:
Theoretical coursework made up of three assignments and two tests – 15 %
Practical coursework- 25%
An end of semester examination – 60%
LECTURE ETHICS
Students with less than 50% in coursework marks will not be allowed to write the
final exam.
Any form of plagiarism in any assignment, test, practical and the final exam will
have the results of all students involved nullified. Honesty and professionalism are
encouraged.
If a student is absent for more than 80% of the lectures, he/she will not be allowed
to write the exam.
No student is allowed in the lecture room 15 min after the lecturer has begun the
lecture.
Submit assignments as scheduled. No late assignments will be accepted. In some
cases typed assignments and/or softcopies are required for submission, format of
presentation
required is font type Times New Roman, font size 12, spacing 1.5, and justified
text.
A continuous assessment test is a “must sit” requirement and should be taken
seriously like the final examination.
Assignments and projects: Practical application of HDL coding, FSM design, and
PLD implementation.
Examinations: Theoretical understanding of the course material.
Laboratory work: Hands-on experience with hardware and simulation tools.
LABORATORY EXERCISES
EXPERIMENT 1: LOGIC GATES
EXPERIMENT 2: COMBINATIONAL LOGIC
a) 2 TO 4 DECODER
b) 8 to 3 encoder
c) 4 x 1 Multiplexer
d) 8 X 1 Multiplexer
e) Demultiplexer
f) 4 bit binary to gray code converter
EXPERIMENT 3: FULL ADDER
Write a Verilog code to describe functioning of a full adder using:
a) Data flow modeling
b) Structural modeling
c) Behavoural modeling
EXPERIMENT 4: DFLIP FLOP
EXPERIMENT 5: T-FLIP FKOP
EXPERIMENT 5: COUNTER
a) 4-bit synchronous counter
b) 4-bit asynchronous counter
Recommended Textbooks
Digital Design and Computer Architecture by David Harris and Sarah Harris
Introduction to Logic Design by M. Morris Mano
HDL Design: A Practical Guide to VHDL and Verilog by Peter J. Ashenden
