EE227 - Digital Logic Design
Spring 2018
Credit Hours: 3 Pre-Requisite: None
Course Instructor: Omer Ali Email: [email protected]
Folder: \\Xeon\fall2018\DLD (A ) Office Hours: TBA
Objectives:
Upon completion of the course students will:
Understand different Number systems & Boolean Algebra
Design combinational and sequential circuits
Understand the internal working of different components of a digital computer
Design moderately complex sequential digital circuits using techniques studied in this course
Be able to undertake Computer Architecture course in future
Important Instructions:
According to the university policy:
o You have to secure at least 50% marks to pass the course.
o For ‘A’ grade the student must secure at least 80% marks in the course.
Plagiarism is not tolerable in any of its form; minimum penalty would be an ‘F’ grade in the course
without prior warning.
You bear all responsibility for protecting your assignments. If anyone else submits your assignment,
you will be considered equally responsible.
Text Book:
M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals (4th Edition Updated, Prentice
Hall)
Reference Books:
- John F. Wakerly, Digital Design: Principles and Practices (3rd Edition, Pearson Education, 2001)
- Thomas L. Floyd, Digital Fundamentals (7th Edition, Prentice Hall, 2000)
Syllabus and Schedule:
Topics Text # of
Lectures
DIGITAL SYSTEMS AND INFORMATION Chapter 1 3
Digital computers and Binary Numbers
Other base numbers (base-8, base-16 etc.)
Number base conversions
COMBINATIONAL LOGIC CIRCUITS Chapter 2 6
Binary Logic and Introduction to Logic Gates
Timing Diagrams
Introduction to Boolean Algebra
Standard forms
Positive and Negative Logic
Boolean Functions and their implementation
Canonical and Standard Forms (Minterms, Maxterms,
Conversions)
Minimization of Boolean functions using K-Map
Don't Care States
Universal gates and implementation of Boolean functions using
universal gates
COMBINATIONAL LOGIC DESIGN Chapter 3 1
Combinational Circuits
Analysis Procedure
Design Procedure
Midterm I
COMBINATIONAL LOGIC DESIGN (Continued) Chapter 3 4
Decoders
Encoders
Multiplexers
Demultiplexer
ARITHMETIC FUNCTIONS AND HDLs Chapter 4 2
Binary Adders (Half Adder, Full Adders, Binary Ripple Carry
Adder, Carry Look ahead Carry Adder)
Binary Subtractor
Binary Adder/Subtractor
Binary Multipliers
Code Conversion
Magnitude Comparator
Parity Generators/ Checkers
Design Applications
1’s and 2’s Complements
Unsigned and Signed numbers and Arithmetic operations
(Addition, subtraction, Multiplication and Division)
SEQUENTIAL CIRCUITS Chapter 5 5
Introduction to Sequential Circuits
Introduction to Latches
Introduction to Flip Flops
Type of Flip Flops
Analysis of Sequential Circuits
Design Procedures
Introduction to develop state diagram and state table
State reduction excitation tables
Midterm II
REGISTERS AND REGISTER TRANSFERS Chapter 7 4
Registers
Counters
Synchronous/Asynchronous
Shift Registers
Serial Shift Registers
Loading Registers
Parallel Registers
Ripple Counters
Synchronous Binary Counters
Other Counters
MEMORY BASICS Chapter 8 2
Read-Only Memories
Programmable Logic Array Devices
Random Access Memory
Static and Dynamic RAM
Array of RAM ICs
Memory construction using RAM Integrated Circuits
A/D & D/A Converters (optional) * 1
Final Exam
* Material not in the text book will be provided to you in the class.
Evaluation Criteria:
Assignments + project 15%
Quizzes 15%
Midterm(2) 30%
Final 40%
