1

DIGITAL SIGNAL PROCESSING (18EC52)

MODULE-5
AS PER 2018 SCHEME
DIGITAL SIGNAL PROCESSORS
Topics Explained 2

 Von Neumann Architecture

 Harvard Architecture
 DSP Hardware Units
 Fixed point format
 Floating point Format
 IEEE Floating point formats
 Fixed point digital signal processors
 Floating point processors
 FIR and IIR filter implementations in Fixed point systems
Architecture of Microprocessors 3

Microprocessor architecture can be classified as

 Von Neumann Architecture
 Harvard Architecture

The design of general purpose microprocessors and microcontrollers is

based on the Von Neumann architecture.

Digital Signal Processors (DSPs) are designed with Harvard Architecture.

Von Neumann Architecture 4

The main components of a processor designed with Von Neumann

Architecture are
 Arithmetic Logic Unit
 Program Control Unit
 Address Generator
 A single, shared memory for programs and data
 A single bus for memory access

Fig. 1 shows the block diagram of a general purpose microprocessor based on

Von Neumann Architecture.
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Fig. 1 . Block diagram of a general purpose microprocessor based on Von

Neumann Architecture
 6

Von Neumann architecture has one common memory unit for both
program and data.
The central processing unit (CPU) fetches an instruction from memory
and decodes it to figure out what operation to do, then executes the
instruction.
Hence, fetching and execution cycles will happen in serial fashion.
The instruction has two parts: the opcode and the operand.
 The opcode tells the CPU what to do.
 The operand tells the CPU what data to operate on.
 7

 After an instruction is completed, the cycles will resume for the next
instruction.
 Since the processor proceeds in a serial fashion, it causes most units to
stay in a wait state which will result in slowing down the speed of
execution.
Harvard Architecture 8
The main components of a processor designed with Von Neumann
Architecture are
 Arithmetic Logic Unit Program Memory Address Bus
 Program Control Unit  Data Memory Address Bus
 Address Generator  Multiplier Accumulator (MAC)
 Program Memory Unit
 Data Memory  Shift Unit

Fig. 2 shows the block diagram of a general purpose microprocessor based on

Harvard Architecture.
 9

Fig. 2 . Block diagram of a general purpose microprocessor based on

Harvard Architecture
 10
 Harvard architecture has two separate memory units - one is dedicated
to the program code, while the other is dedicated for data.
 To accommodate two memory spaces, two corresponding address buses
and two data buses are used.
 This means that the Harvard processor can fetch the program instruction
and data in parallel at the same time.
 There is an additional unit called a multiplier and accumulator (MAC),
which is dedicated for the digital filtering operation.
 The last additional unit, the shift unit, is used for the scaling operation
for fixed-point implementation when the processor performs digital
filtering.
 11

Fig. 3. Execution cycle based on Von Neumann architecture

Fig. 4. Execution cycle based on Harvard architecture

 12
 Fig. 3 shows the execution cycle based on Von Neumann architecture.
 Instruction fetch and execute cycles take place in serial fashion.
 Fig. 4 shows the execution cycle based on Harvard architecture.
 While the current instruction is being executed, the next instruction to be
executed is fetched.
 This is called pipelining.
 Pipelining dramatically increases the processing speed.
 13

The Harvard architecture is preferred for all digital signal processors due
to the requirements of most DSP algorithms, such as filtering,
convolution, and FFT, which need repetitive arithmetic operations,
including multiplications, additions, memory access, and heavy data flow
through the CPU

For other applications, such as those dependent on simple microcontrollers

with less of a timing requirement, the Von Neumann architecture may be a
better choice, since it offers much less silica area and is thus less
expansive.
Digital Signal Processor (DSP) Hardware Units 14

Some of the special units in a DSP are

 Multiplier and Accumulator (MAC)
 Shifter
 Address Generator
Multiplier and Accumulator (MAC) 15

 MAC is a special hardware unit for enhancing the speed of digital filtering.
 Fig. 5 shows a typical MAC unit used in DSP.
 It has a pair of input registers, each holding a 16-bit input to the multiplier.
 The result of the multiplication is accumulated in a 32-bit accumulator
unit.
 The result register holds the double precision data from the accumulator.
 16

Fig. 5. The multiplier and accumulator (MAC) dedicated to DSP

Shifter 17

 Consider a 3-bit data word

(011)2 = (3)10
 Shifting (011)2 to the right gives (001)2 = 1 10
 It is as good as dividing 3 by 2 and then truncating the fractional part.
 Consider a 3-bit data word
(011)2 = (3)10
 Shifting (011)2 to the left gives (110)2 = 6 10
 It is as good as multiplying 3 by 2.
 A DSP requires these operations to be done quite often.
 Hence, it uses a special hardware unit for shifting.
 18
Address Generators
 In a DSP, data samples are stored in a circular buffer.
 Figure 6 describes the basic mechanism of circular buffering for a buffer
having eight data samples.
 19

Fig. 6. Illustration of circular buffering

 20

 In circular buffering, a pointer is used and it always points to the newest

data sample.
 After the next sample is obtained from analog to digital converter (ADC),
the data will be placed at the location of 𝑥(𝑛 − 7) and the oldest sample
is pushed out.
 Thus, the location for 𝑥(𝑛 − 7) becomes the location for the current
sample.
 The original location for 𝑥(𝑛) becomes the location of the past sample
𝑥(𝑛 − 1).
 For each new data sample, only one location on the circular buffer needs to
be updated.
 21

 The circular buffer acts like a first-in/first-out (FIFO) buffer, but every data
sample on the buffer need not be moved.
 This will significantly enhance the processing speed.
 Fig. 7 gives a simple illustration of 2-bit circular buffer.
 22

Fig. 7. Circular Buffer and Equivalent FIFO Operation

 23
 Initially, the buffer is storing the samples a,b,c,d and the pointer is
pointing to (storing the address of ) the latest sample d.
 The equivalent FIFO buffer is shown on the right.
 When the new sample e comes in, it will be stored in the place of the
oldest sample i.e., a and pointer now points to the position of e.
 Note that only one position in the circular buffer is updated.
 But, if the same operation is to be implemented with the help of FIFO
buffer, all the 4 locations are to be updated.
 24
Number Representation in DSP
 A fixed-point DSP represents data in 2’s complement integer format and
manipulates data using integer arithmetic.
 A floating-point DSP represents numbers using a mantissa (fractional part)
and an exponent in addition to the integer format and operates data using
floating-point arithmetic
 25
2’s complement Number Representation
Converting a decimal number into its 2’s complement requires the following
steps:
 Convert the magnitude in the decimal form into its binary number using the
required number of bits.
 If the decimal number is positive, no further operation is required.
 If the decimal number is negative, then perform 2’s complement operation.
 To perform 2’s complement operation, negate each bit and then add logic 1 to
the answer.
 26

Ex. 1 : Convert 3 into 3-bit 2’s complement representation.

3 10 = 011 2

Ex. 2 : Convert -3 into 3-bit 2’s complement representation.

3 10 = 011 2

Since the decimal number is –ve, we have to find the 2’s complement of
011 2
 27

Let us negate each bit of 011.

We get 100.

Let us add 1 to 100. We get 101.

Hence −3 10 = 101 as per 2’s complement representation.

 Decimal Number 2’s Complement 28
3 011
2 010
1 001
0 000
-1 111
-2 110
-3 101
-4 100

Table 1 : 3-bit 2’s complement number representation

 29

Ex. 3 : Perform 𝟐 × −𝟏 using 2’s complement method.

 30

2’s complement of 00010 is 11110.

Discard the first two bits. We get 110 which is equal to −2.

−2 is within the range. (Refer to Table 1)

 31

Ex. 4 : Perform 𝟐 × −𝟑 using 2’s complement method.

 32
 2’s complement of 00110 is 11010.

 Discard the first two bits. We get 010 which is equal to 2.

 But the product of 2 and −3 is −6.

 We are getting wrong answer because −6 cannot be represented with

3-bits in 2’s complement method (Refer to Table 1).

 We say that OVERFLOW has occurred.

 33
 Now, lets design a binary number system which can prevent
multiplication overflow.

 One such number system is FRACTIONAL number system.

 The product of two fractions is another fraction.

 Hence, multiplication overflow can be avoided.

 34
Q-2 Format
 In Q-2 format, there are 2 magnitude bits and 1 sign bit.
Decimal Number Decimal Fraction 2’s Complement
3 3/4 0.11
2 2/4 0.10
1 1/4 0.01
0 0 0.00
-1 -1/4 1.11
-2 -2/4 1.10
-3 -3/4 1.01
-4 -4/4= -1 1.00

Table 2 : A 3-bit 2’s complement system using fractional number representation

 35
 In Q-2 format, the most –ve number that can be represented is -1

−2 3
 The most +ve number is 1 − 2 =
4

 There are 23 = 8 different levels

−2 1
 Each interval is of size 2 =
4
 36
𝟐 𝟑
Ex. 5 : Perform × − using Q-2 number system.
𝟒 𝟒

𝟐 𝟑 3
We know that × − = −
𝟒 𝟒 8

 Now, lets see how we can perform this operation in Q-2 number
system.
 37

 2’s complement of 0.0110 is 1.1010

 Let us convert 1.1010 into decimal and check if we get the right
product.
 38

 In 1.1010, first bit is 1 which indicates that the answer is –ve.

 Let us convert 1.1010 into decimal.

 2’s complement of 1.1010 is 0.0110

 39

1.1010 2 = −(0 ∗ 2−1 + 1 ∗ 2−2 + 1 ∗ 2−3 + 0 ∗ 2−4

1 1
= −( + )
4 8
3
= −
8
which is the right answer.

But, if we discard last two bits and retain only 3 bits, then we get 1.10

Let us convert 1.10 into decimal.

 40

In 1.10 the first bit 1 indicates that the number is –ve.

2’s complement of 1.10 is 0.10

Therefore,

1.10 = −(1 ∗ 2−1 + 0 ∗ 2−2 )

1
= −
2
 41

3
 The actual answer was −
8

1
 But we are getting −
2

 This is due to truncation error.

1 3 1 1 1
 Error = − − − = − = which is less than
2 8 8 8 4
 42
Q-15 Format
 In Q-15 format, there are 15 magnitude bits and 1 sign bit.

 The most –ve number that can be represented is -1

 The most +ve number is 1 − 2−15

 There will be 216 levels

 Each interval is of size 2−15

Ex. 6 : Find the signed Q-15 representation of 0.560123.
43

Table 3 : Conversion process of 0.560123 into Q-15 format

 44

Hence,

0.560123 = 0.100011110110010

Note that first bit is 0 because the number is +ve.

 45
Ex. 7 : Find the signed Q-15 representation of -0.560123.
 First, consider the magnitude 0.560123

 In Ex. 6, we have seen

0.560123 = 0.100011110110010

 2’s complement of
0.100011110110010 = 1011100001001110

 Therefore, −0.560123 = 1011100001001110

Ex. 8 : Convert Q-15 signed number 𝟎. 𝟏𝟎𝟎𝟎𝟏𝟏𝟏𝟏𝟎𝟏𝟏𝟎𝟎𝟏𝟎 46
to decimal number.

 First bit is 0. That means number is +ve.

 The equivalent decimal value is

2−1 + 2−5 + 2−6 + 2−7 + 2−8 + 2−10 + 2−11 + 2−14
= 0.560120
Ex. 9 : Convert Q-15 signed number 𝟏. 𝟏𝟏𝟎𝟏𝟎𝟏𝟏𝟏𝟎𝟎𝟎𝟎𝟎𝟏𝟎 47
to decimal number.
 First bit is 1. That means number is -ve.

 Therefore, lets first convert into its 2’s complement format.

 2’s complement of 𝟏. 𝟏𝟏𝟎𝟏𝟎𝟏𝟏𝟏𝟎𝟎𝟎𝟎𝟎𝟏𝟎 is

0.001010001111110
 Its decimal equivalent is
− 2−3 + 2−5 + 2−9 + 2−10 + 2−11 + 2−12 + 2−13 + 2−14
= −0.160095
 48

Ex. 10 : Add 𝟏. 𝟏𝟏𝟎𝟏𝟎𝟏𝟏𝟏𝟎𝟎𝟎𝟎𝟎𝟏𝟎 and 𝟎. 𝟏𝟎𝟎𝟎𝟏𝟏𝟏𝟏𝟎𝟏𝟏𝟎𝟎𝟏𝟎

in Q-15 format.

The result is 0.011001100110100

Ex. 11 : Find the product of 𝟎. 𝟐𝟓 and 𝟎. 𝟓 in Q-3 fixed point 2’s
49
complement format.
In Q-3 format, 0.25 = 0.010 and 0.5 = 0.100
 50

Dropping the least significant bits and retaining only 4 bits, we get 0.001

Note : If we convert 0.001 into decimal value, we get 2−3 which is equal
to 0.125 which is the product of 0.25 and 0.5.
Floating Point Format 51

 Floating point format is used to increase the dynamic range of number

representation.
 The general format for floating point number representation is given by
𝑥 = 𝑀2𝐸
where M is the mantissa or fractional part in Q format and E is the
exponent.
 52

 If we assign 12 bits for the mantissa and 4 bits for the exponent, the
format looks as follows.
 53
 The most –ve number we can represent in this format is
1.00000000000 2 ∗ 2 0111 2 = −1 ∗ 27 = −128.0

 The most +ve number we can represent in this format is

0.11111111111 2 ∗ 2 0111 2 = (1 − 2−11 ) ∗ 27 = 127.9375

 The smallest +ve number is given by

0.00000000001 2 ∗ 2 1000 2 = (2−11 ) ∗ 2−8 = 2−19
Ex. 12 : Convert 𝟎. 𝟏𝟔𝟎𝟏𝟐𝟑𝟎 into floating point number. 54
𝟎.𝟏𝟔𝟎𝟏𝟐𝟑𝟎
 We first scale the number 𝟎. 𝟏𝟔𝟎𝟏𝟐𝟑𝟎 to = 0.640492
2−2

 Note that this choice of scaling is not unique. We can also scale the number
by 20 or 2−1

 We can write 𝟎. 𝟏𝟔𝟎𝟏𝟐𝟑𝟎 = 0.640492 ∗ 2−2

 Then we convert 0.640492 into Q-11 format to get 010100011111

 Refer to Ex. 6 to learn how to convert 0.640492 into Q-11 format

 55

 In 2’s complement format, we have −2 = 1110

 Cascading the exponent bits and the mantissa bits yields

1110010100011111
Ex. 13 : Convert −𝟐𝟎. 𝟒𝟑𝟎𝟓𝟐𝟕 into floating point number. 56

−20.430527
 We first scale the number -𝟐𝟎.𝟒𝟑𝟎𝟓𝟐𝟕 to = −0.638454
25

 Note that this choice of scaling is not unique

 We can also scale the number by 26 or 27

 We can write −20.430527 = −0.638484 ∗ 25

 Here the fractional part is−0.638484 and the exponent part is 5.

 57
 Therefore, exponent bits should be 0101

 Converting the number 0.638454 using Q-11 format gives

010100011011

 Refer to Ex. 6 to learn how to convert 0.638454 into Q-11 format

 Using 2’s complement we may write

−0.638454 = 101011100101
 58
 Cascading the exponent bits and mantissa bits, we get
0101101011100101
 59

Ex. 14 : Add 𝟎. 𝟔𝟒𝟎𝟏𝟑𝟔𝟕𝟏𝟖 ∗ 𝟐−𝟐 and −𝟎. 𝟔𝟑𝟖𝟏𝟖𝟑𝟓𝟗𝟑 ∗ 𝟐𝟓 using

floating point format.
 Before addition, we change the first number to have the same exponent as the
second number so that its easy to add the two numbers.

 𝟎. 𝟔𝟒𝟎𝟏𝟑𝟔𝟕𝟏𝟖 ∗ 𝟐−𝟐 = 𝟎. 𝟔𝟒𝟎𝟏𝟑𝟔𝟕𝟏𝟖 ∗ 𝟐−7 ∗ 25 =

0.0050010681 ∗ 25

 Now, we may proceed to add the two numbers.

 60

 First let us represent both the numbers in floating point format.

 𝟎. 𝟔𝟒𝟎𝟏𝟑𝟔𝟕𝟏𝟖 ∗ 𝟐−7 ∗ 25 = 0.0050010681 ∗ 25 =

0101 000000001010

 −𝟎. 𝟔𝟑𝟖𝟏𝟖𝟑𝟓𝟗𝟑 ∗ 𝟐𝟓 = 0101 101011100101

 We know that 𝑀1 2𝐸 + 𝑀2 2𝐸 = 𝑀1 + 𝑀2 2𝐸

 Therefore, lets add the mantissa part of both the numbers.

 61

By cascading the exponent and mantissa parts, we get the floating point
number as 0101 101011101111
 62
Ex. 15 : Multiply the following using floating point format.

𝟏𝟏𝟏𝟎 𝟎𝟏𝟎𝟏𝟎𝟎𝟎𝟏𝟏𝟏𝟏𝟏 = 𝟎. 𝟔𝟒𝟎𝟏𝟑𝟔𝟕𝟏𝟖 ∗ 𝟐−𝟐

and
𝟎𝟏𝟎𝟏 𝟏𝟎𝟏𝟎𝟏𝟏𝟏𝟎𝟎𝟏𝟎𝟏 = −𝟎. 𝟔𝟑𝟖𝟏𝟖𝟑𝟓𝟗𝟑 ∗ 𝟐𝟓

 We know that 𝑀1 2𝐸1 ∗ 𝑀2 2𝐸2 = 𝑀1 𝑀2 2(𝐸1+𝐸2) .

 Therefore, lets multiply the mantissa parts and add the exponent parts.
 63

 𝐸1 + 𝐸2 = 1110 + 0101 = 0011 which is equal to 3 as expected.

 Now lets find the product of mantissa.

 𝑀1 = 𝟎૚𝟎૚𝟎𝟎𝟎૚૚૚૚૚ and 𝑀2 = 101011100101

 The first bit in 𝑀2 is 1 which indicates that the number is negative.

 Therefore, lets find the 2’s complement of 𝑀2

 64
 2’s complement of 𝑀2 = 010100011011

 Now, we multiply two positive mantissas and truncate the result to 12 bits to
get
010100011111 ∗ 010100011011 = 001101000100

 But we know that the product is –ve.

 Therefore, we take the 2’s complement of 001101000100 to get

110010111100
 65
 Finally, we cascade 4-bit exponent and 12-bit mantissa to get the final answer.

 Final answer is 0011 110010111100

IEEE Floating Point Formats 66
 IEEE stands for Institute of Electrical and Electronics Engineers

 It was formed in 1963 with the objectives of the educational and

technical advancement of electrical and electronic engineering,
telecommunications, computer engineering and allied disciplines

 There are two types of IEEE floating-point formats

 One is the IEEE single precision format, and the other is the IEEE
double precision format.
IEEE Single Precision Format (IEEE 754) 67

 There are totally 32 bits in this format

 1 sign bit, 8 exponent bits and 23 fraction bits
 To convert IEEE Single Precision Format into decimal number, we
can make use of the following formula.
𝐝𝐞𝐜𝐢𝐦𝐚𝐥 𝐯𝐚𝐥𝐮𝐞 = −𝟏 𝒔 ∗ 𝟏. 𝑭 ∗ 𝟐 𝑬−𝟏𝟐𝟕
 68
Ex. 16 : Convert the following number in the IEEE single precision format to
the decimal format
𝟏𝟏𝟎𝟎𝟎𝟎𝟎𝟎𝟎. 𝟎𝟏𝟎 . . . 𝟎𝟎𝟎𝟎
 𝑠=1
 𝐸 = 27 = 128
 𝐹 = 0 ∗ 2−1 + 1 ∗ 2−2 = 0.25
 𝐝𝐞𝐜𝐢𝐦𝐚𝐥 𝐯𝐚𝐥𝐮𝐞 = −𝟏 𝒔 ∗ 𝟏. 𝑭 ∗ 𝟐 𝑬−𝟏𝟐𝟕
= −1 1 ∗ 1.25 ∗ 2 128−127
= −2.5
IEEE Double Precision Format (IEEE 754) 69

 There are totally 64 bits in this format

 1 sign bit, 11 exponent bits and 52 fraction bits
 To convert IEEE Double Precision Format into decimal number, we
can make use of the following formula.
𝐝𝐞𝐜𝐢𝐦𝐚𝐥 𝐯𝐚𝐥𝐮𝐞 = −𝟏 𝒔 ∗ 𝟏. 𝑭 ∗ 𝟐 𝑬−𝟏𝟎𝟐𝟑
 70
Ex. 17 : Convert the following number in the IEEE double precision format
to the decimal format
𝟎𝟎𝟏𝟎𝟎𝟎 … 𝟎. 𝟏𝟏𝟎 … 𝟎𝟎𝟎𝟎
 𝑠=0
 𝐸 = 29 = 512
 𝐹 = 1 ∗ 2−1 + 1 ∗ 2−2 = 0.75
 𝐝𝐞𝐜𝐢𝐦𝐚𝐥 𝐯𝐚𝐥𝐮𝐞 = −𝟏 𝒔 ∗ 𝟏. 𝑭 ∗ 𝟐 𝑬−𝟏𝟐𝟕
= −1 0 ∗ 1.75 ∗ 2 512−1023
= 1.75 ∗ 2 −511
Fixed Point Digital Signal Processors 71

 Texas Instruments, Motorola, Analog Devices are some of the

manufacturers of Fixed Point Digital Signal Processors.

 Block diagram of a typical TMS320C54x fixed point processor is

shown in the following figure.
Basic Architecture of TMS320C54x Family 72
Basic Architecture of TMS320C54x Family 73

 These processors are based on Harward Architecture, ie, separate

memory units are provided for program and data.

 Four data buses and four address buses are accommodated to work with
the data memories and program memories in parallel to speed up the
operation.

 The program memory address bus and program memory data bus are
responsible for fetching the program instruction
Basic Architecture of TMS320C54x Family 74

 C and D data memory address buses and the C and D data memory data
buses deal with fetching data from the data memory.

 E data memory address bus and the E data memory data bus are
dedicated to moving data into data memory.

 E memory data bus can also access the I/O devices.

Basic Architecture of TMS320C54x Family 75

 Computational units consist of an ALU, a MAC, and a shift unit.

 ALU has two independent 40-bit accumulators, which are able to do

40-bit addition

 The multiplier is capable of performing 17-bit multiplications.

 Shift unit is of 40-bit long.

Basic Architecture of TMS320C54x Family 76

 The program control unit fetches instructions via the program memory
data bus.

 In order to speed up memory access, there are two address generators

available: one responsible for program addresses and one for data
addresses.

 Processing speed is 40 MIPS (Million Instruction sets Per Second).

Floating Point Processors 77

 Texas Instruments and Analog Devices are the major manufacturers of

Floating Point Digital Signal Processors.

 Using floating point arithmetic offers the advantages such as getting rid
of overflows, round-off errors, truncation errors and coefficient
quantization errors.

 Hence, in terms of coding, we do not need to scale down input samples

to avoid overflow.
Floating Point Processors 78

 One of the prominent floating point processor families is TMS320C3x

family from Texas Instruments.
A Typical TMS320C3x Floating-Point Digital 79
Signal Processor
Features of TMS320C3x Floating-Point Digital 80

Signal Processors
 These processors are based on Harward Architecture, ie, separate
memory units are provided for program and data.

 A program cache memory is employed to enhance the execution of

commonly used codes.

 There also exist memory buses and data buses for direct-memory
access (DMA) for simulataneous I/O and CPU operations.
Features of TMS320C3x Floating-Point Digital 81

Signal Processors
 ALU is capable of operating both integer and floating-point arithmetic.

 The multiplier operates single-cycle multiplications on 24-bit integers

and on 32-bit floating-point values

 Using parallel instructions to perform a multiplication, an ALU will cost

a single cycle, which means that a multiplication and an addition are
equally fast
Features of TMS320C3x Floating-Point Digital 82

Signal Processors
 The CPU register file offers 28 registers, which can be operated on by
the multiplier and ALU.

 The special functions of the registers include eight extended 40-bit

precision registers for maintaining accuracy of the floating-point results.

 Eight auxiliary registers can be used for addressing and for integer
arithmetic.
Features of TMS320C3x Floating-Point Digital 83

Signal Processors
 These registers provide internal temporary storage of internal variables
instead of external memory storage, to allow performance of arithmetic
between registers.

 In this way, program efficiency is greatly increased.

 Processing speeds up to 16.7 MIPS can be achieved.

Features of TMS320C3x Floating-Point Digital 84

Signal Processors
 Three floating-point formats are supported.
 A short 16-bit floating-point format has 4 exponent bits, 1 sign bit, and
11 mantissa bits.
 A 32-bit single precision format has 8 exponent bits, 1 sign bit, and 23
fraction bits.
 A 40-bit extended precision format contains 8 exponent bits, 1 sign bit,
and 31 fraction bits.
Finite Impulse Response (FIR) and Infinite 85

Impulse Response (IIR) Filter implementation in

Fixed-Point systems
 In the fixed point system, we prefer input data, filter coefficients, and
processed output data to be in the Q-format.

 In this way, we can avoid overflow due to multiplications and can

prevent overflow due to addition by scaling down input data
 86
 To avoid overflow for an adder, we can scale the input down by a
scale factor S, which can be determined by the equation
∞

𝑆 = 𝐼𝑚𝑎𝑥 |ℎ 𝑘 |
𝑘=0
= 𝐼𝑚𝑎𝑥 ℎ 0 + ℎ 1 + ...
where ℎ 𝑘 is the impulse response of the filter.

 Scaling down of the input by a factor of S will guarantee that the

output of the adder is in Q-format
 87
 When some of the FIR coefficients are larger than 1, which is beyond
the range of Q-format representation, coefficient scaling is required

 Scaling down the coefficients will make them less than 1, and later the
filtered output will be scaled up by the same amount before it is sent to
Digital to Analog Converter (DAC).
 88
Ex. 18 : Given the FIR filter
𝒚 𝒏 = 𝟎. 𝟗𝒙 𝒏 + 𝟑𝒙 𝒏 − 𝟏 − 𝟎. 𝟗𝒙 𝒏 − 𝟐
𝟏
with a passband gain of 4. Assume that the input range occupies only th of
𝟒
full range, develop the DSP implementation equation in Q-15 fixed point
system.

 From the given difference equation, we note that impulse response

ℎ 𝑛 = 0.9, 3, −0.9

1
 The scaling factor 𝑆 = ∗ 0.9 + 3 + 0.9 = 1.2
4
 89
 We select 𝑆 = 2 (a power of 2)

 One of the samples of ℎ[𝑛] is greater than 1 i.e., 3 which cannot be

represented in Q-15 format.
(Recall : Only fractional values can be represented in Q format)

 Therefore, coefficient scaling must be done.

 Let us choose scaling factor B = 4 which is a power of 2 and it is greater

than 3.
 90
 We have to scale input down by a factor 𝑆 = 2

 We have to scale the coefficients of impulse response down by a factor 𝐵 =

4

 Then the new input and new impulse response respectively will be
𝑥𝑛 ℎ𝑛
𝑥𝑠 𝑛 = and ℎ𝑠 𝑛 = = 0.225, 0.75, −0.225
2 4

 Then the new difference equation will be

𝑦𝑠 𝑛 = 0.225 ∗ 𝑥𝑠 𝑛 + 0.75 ∗ 𝑥𝑠 𝑛 − 1 − 0.225 ∗ 𝑥𝑠 𝑛 − 2
 91

 Effectively, we have scaled down the output by a factor

𝐵∗𝑆 =4∗2=8

 Therefore, the required output

𝑦 𝑛 = 8𝑦𝑠 𝑛
 92

Fig. 8. Direct Form 1 (DF-I) Implementation of the FIR Filter

 93
Ex. 19 : The following IIR filter
𝒚 𝒏 = 𝟐𝒙 𝒏 + 𝟎. 𝟓𝒚 𝒏 − 𝟏
uses direct form 1 and the maximum input is 𝟎. 𝟐𝟓.
Develop the DSP implementation equations in the Q-15 fixed-point system.

 Let us find the transfer function of the filter.

 Taking Z-transform, we get
𝑌 𝑧 = 2𝑋 𝑧 + 0.5𝑧 −1 𝑌 𝑧
𝑌 𝑧 1 − 0.5𝑧 −1 = 2𝑋 𝑧

𝑌𝑧 2 2𝑧
Transfer function 𝐻 𝑧 = = =
𝑋𝑧 1−0.5𝑧 −1 𝑧−0.5
 94
 To find the impulse response, we have to find the inverse Z-transform of
𝐻𝑧

𝑧
 We know that inverse Z-transform of = 𝑎𝑛 𝑢 𝑛
𝑧−𝑎

 Therefore, impulse response of the given IIR filter,

ℎ 𝑛 = 2 ∗ 0.5𝑛 ∗ 𝑢 𝑛
= 2 1, 0.5, 0.25, . . .
 95
∞
 The scaling factor 𝑆 = 0.25 ∗ 𝑛=0 |ℎ 𝑛|

1
= 0.25 ∗ 2 ∗
1−0.5

=1

 If 𝑆 ≤ 1 we need not perform input scaling.

 96
 Then we need to check if we have to perform scaling of impulse response.

 The highest sample of impulse response is 2 which cannot be represented with

Q-15 format.
(Recall : Only fractional values can be represented with Q format.)

 Therefore, it is necessary to perform coefficient scaling, i.e., scaling down

samples of impulse response.
 97
 Let us choose a scaling factor of 𝐶 = 4, because 4 is greater than 2 and it is a
power of 2.

 With these scaling factors, 𝑆 = 1 and 𝐶 = 4, we can get the difference

equation representation of the filter as follows.
𝑥𝑛
𝑥𝑠 𝑛 = =𝑥 𝑛
𝑆
1
𝑦𝑠 𝑛 = 𝑦 𝑛
𝐶
1
= 2𝑥 𝑛 + 0.5𝑦 𝑛 − 1
4
 98
 Therefore,
𝑦𝑠 𝑛 = 0.5𝑥 𝑛 + 0.125𝑦 𝑛 − 1

 Effectively, we have scaled down the output by a factor

𝑆∗𝐶 =1∗4=4

 Therefore, the required output

𝑦 𝑛 = 4𝑦𝑠 𝑛
 99

Fig. 9. Direct Form 1 Implementation of the IIR Filter

Questions from VTU Model Question Paper 100

Q.No. Question Page No.

9(a) With the block diagram explain Digital signal processors 8
based on the Harvard architecture (6 Marks)
9(b) Discuss briefly the following special Digital Signal 14
Processor hardware units.
a) Multiplier and Accumulator (MAC) Unit
b) Shifters
c) Address Generators
(3+2+5=10 Marks)
Questions from VTU Model Question Paper 101

Q. No. Question Page No.

9(c) Convert the following decimal numbers into Q-15 43
representation. (4 Marks)
a) −0.1958
b) 0.560123
Questions from VTU Model Question Paper 102

Q. No. Question Page No.

10(a) Given the FIR filter 88
𝒚[𝒏]=𝟎.𝟗𝒙[𝒏]+𝟑𝒙[𝒏−૚]−𝟎.𝟗𝒙[𝒏−𝟐]
with a passband gain of 4. Assume that the input range
occupies only ૚/𝟒 th of full range, develop the DSP
implementation equation in Q-15 fixed point system.
(6 Marks)
Questions from VTU Model Question Paper 103

Q. No. Question Page No.

10(b) Discuss the following IEEE Floating – Point Formats. 67
(i) Single Precision Format
(ii) Double Precision Format
(6 Marks)
Questions from VTU Model Question Paper 104

Q. No. Question Page No.

10(c) With the diagram explain the basic architecture of 71
TMS320C54x family processor.
(6 Marks)