Name:jaya krishna
Affiliation (Institution/Company):KL UNIVERSITY HYDERABAD
Title of Internship Program Undertaken: Verification using System Verilog
Assignment No and Title : - Assignment for Verification using Verilog
Important Instructions:
1) All assignment results should be computer screenshot or computer typed. Handwritten and
scanned copies shall not be considered for evaluation
2) Due date for all assignment submission is 1 Week from the last date of internship
3) All assignment questions should be captured along with solutions/answers.
4) Code snippets, simulation results should be captured properly
5) Use only the JPEG image format for capturing the simulation results and name/label the results
appropriately.
6) The description of answers should be short and crisp. Provide only the required information,
answered copied or cut and pasted from google shall not be considered.
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
DESIGN FOR 4 BIT SERIAL ADDER
module apb_add_master (input logic pclk,
input logic preset_n,
input logic[1:0] add_i,
output logic psel_o,
output logic penable_o,
output logic [31:0] paddr_o,
output logic pwrite_o,
output logic [31:0] pwdata_o,
input logic [31:0] prdata_i,
input logic pready_i);
typedef enum logic[1:0] {ST_IDLE, ST_SETUP, ST_ACCESS} apb_state_t;
apb_state_t state_q;
apb_state_t nxt_state;
logic apb_state_setup;
logic apb_state_access;
logic nxt_pwrite;
logic pwrite_q;
logic [31:0] nxt_rdata;
logic [31:0] rdata_q;
always_ff @(posedge pclk or negedge preset_n)
if (~preset_n)
state_q <= ST_IDLE;
else
state_q <= nxt_state;
always_comb begin
nxt_pwrite = pwrite_q;
nxt_rdata = rdata_q;
case (state_q)
ST_IDLE:
if (add_i[0]) begin
nxt_state = ST_SETUP;
nxt_pwrite = add_i[1];
end else begin
nxt_state = ST_IDLE;
end
ST_SETUP: nxt_state = ST_ACCESS;
ST_ACCESS:
if (pready_i) begin
if (~pwrite_q)
nxt_rdata = prdata_i;
nxt_state = ST_IDLE;
end else
nxt_state = ST_ACCESS;
default: nxt_state = ST_IDLE;
endcase
PRIVATE & CONFIDENTIAL
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end
assign apb_state_access = (state_q == ST_ACCESS);
assign apb_state_setup = (state_q == ST_SETUP);
assign psel_o = apb_state_setup | apb_state_access;
assign penable_o = apb_state_access;
assign paddr_o = {32{apb_state_access}} & 32'hA000;
always_ff @(posedge pclk or negedge preset_n)
if (~preset_n)
pwrite_q <= 1'b0;
else
pwrite_q <= nxt_pwrite;
assign pwrite_o = pwrite_q;
assign pwdata_o = {32{apb_state_access}} & (rdata_q + 32'h1);
always_ff @(posedge pclk or negedge preset_n)
if (~preset_n)
rdata_q <= 32'h0;
else
rdata_q <= nxt_rdata;
endmodule
TEST BENCH FOR 4BIT SERIAL ADDER
`define CLK @(posedge pclk)
module apb_slave_tb ();
logic pclk;
logic preset_n;
logic[1:0] add_i;
logic psel_o;
logic penable_o;
logic [31:0] paddr_o;
logic pwrite_o;
logic [31:0] pwdata_o;
logic [31:0] prdata_i;
logic pready_i;
always begin
pclk = 1'b0;
#5;
pclk = 1'b1;
#5;
end
apb_add_master APB_MASTER (.*);
initial begin
preset_n = 1'b0;
add_i = 2'b00;
repeat (2) `CLK;
PRIVATE & CONFIDENTIAL
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preset_n = 1'b1;
repeat (2) `CLK;
add_i = 2'b01;
`CLK;
add_i = 2'b00;
repeat (4) `CLK;
add_i = 2'b11;
`CLK;
add_i = 2'b00;
repeat (4) `CLK;
$finish();
end
always_ff @(posedge pclk or negedge preset_n) begin
if (~preset_n)
pready_i <= 1'b0;
else begin
if (psel_o && penable_o) begin
pready_i <= 1'b1;
prdata_i <= $urandom%32'h20;
end else begin
pready_i <= 1'b0;
prdata_i <= $urandom%32'hFF;
end
end
end
initial begin
$dumpfile("apb_master.vcd");
$dumpvars(2, apb_slave_tb);
end
endmodule
USER SPACE
2. APB MEMORY
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
DESIGN CODE FRO APB
`timescale 1ns/1ps
`define DATAWIDTH 32
`define ADDRWIDTH 8
`define IDLE 2'b00
`define W_ENABLE 2'b01
`define R_ENABLE 2'b10
module APB_Slave(
input PCLK,
input PRESETn,
input [`ADDRWIDTH-1:0] PADDR,
input PWRITE,
input PSEL,
input [`DATAWIDTH-1:0] PWDATA,
output reg [`DATAWIDTH-1:0] PRDATA,
output reg PREADY);
reg [`DATAWIDTH-1:0] RAM [0:2**`ADDRWIDTH -1];
reg [1:0] State;
always @(negedge PRESETn or negedge PCLK) begin
if (PRESETn == 0) begin
State <= `IDLE;
PRDATA <= 0;
PREADY <= 0;
end
else begin
case (State)
`IDLE : begin
PRDATA <= 0;
if (PSEL) begin
if (PWRITE) begin
PRIVATE & CONFIDENTIAL
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State <= `W_ENABLE;
end
else begin
State <= `R_ENABLE;
end
end
end
`W_ENABLE : begin
if (PSEL && PWRITE) begin
RAM[PADDR] <= PWDATA;
PREADY <=1;
end
State <= `IDLE;
end
`R_ENABLE : begin
if (PSEL && !PWRITE) begin
PREADY <= 1;
PRDATA <= RAM[PADDR];
end
State <= `IDLE;
end
default: begin
State <= `IDLE;
end
endcase end
end
endmodule
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
TEST BENCH FOR APB MEMORY
`timescale 1ns/1ps
`define DATAWIDTH 32
`define ADDRWIDTH 8
`define IDLE 2'b00
`define W_ENABLE 2'b01
`define R_ENABLE 2'b10
module APB_Slave_tb ();
reg PCLK;
reg PRESETn;
reg [`ADDRWIDTH-1:0] PADDR;
reg PWRITE;
reg PSEL;
reg [`DATAWIDTH-1:0] PWDATA;
wire [`DATAWIDTH-1:0] PRDATA;
wire PREADY;
integer i;
integer j;
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,APB_Slave_tb);
PCLK = 0;
PRESETn = 0;
#10
PRESETn = 1;
PSEL = 0;
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
#10
Write;
Read;
#20;
#10000;
$finish;
end
always #1 PCLK = ~PCLK;
APB_Slave DUT(PCLK,
PRESETn,
PADDR,
PWRITE,
PSEL,
PWDATA,
PRDATA,
PREADY );
task Write;
begin
// #1;
for (i = 0; i < 2**`ADDRWIDTH; i=i+1) begin
@(negedge PCLK) begin
// @(negedge PCLK) begin
PSEL = 1;
PWRITE = 1;
PADDR = i;
PWDATA = i;
$display("PADDR %h, PWDATA %h ",PADDR,PWDATA);
PRIVATE & CONFIDENTIAL
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// end
end
// #2;
// PSEL = 0;
end
// PSEL = 0;
end
endtask
task Read;
begin
for (j = 0; j< 2**`ADDRWIDTH; j= j+1) begin
@(negedge PCLK) begin
PSEL = 1;
PWRITE = 0;
// @(negedge PCLK) begin
// end
// @(negedge PCLK) begin
PADDR = j;
// PSEL = 0;
$display("PADDR %h, PRDATA %h ",PADDR,PRDATA);
// end
end
end
end
endtask
endmodule
output for apb memory:
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
USER SPACE
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
