TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

D High-Performance Floating-Point DSP D 144-Pin Plastic Quad Flat Package

– TMS320C32-60 (5 V) ( PCM Suffix ) 5 V
33-ns Instruction Cycle Time D Eight Extended-Precision Registers
330 Million Operations Per Second
(MOPS), 60 Million Floating-Point
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Operations Per Second (MFLOPS), 30
Register Arithmetic Units (ARAUs)
Million Instructions Per Second (MIPS)
– TMS320C32-50 (5 V) D Two Low-Power Modes
40-ns Instruction Cycle Time D Two- and Three-Operand Instructions
275 MOPS, 50 MFLOPS, 25 MIPS D Parallel Arithmetic Logic Unit (ALU) and
– TMS320C32-40 (5 V) Multiplier Execution in a Single Cycle
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
D Block-Repeat Capability

D 32-Bit High-Performance CPU

D Zero-Overhead Loops With Single-Cycle
Branches
D 16- / 32-Bit Integer and 32- / 40-Bit
D Conditional Calls and Returns
Floating-Point Operations
D 32-Bit Instruction Word, 24-Bit Addresses
D Interlocked Instructions for
Multiprocessing Support
D Two 256 × 32-Bit Single-Cycle, Dual-Access
D One External Pin, PRGW, That Configures
On-Chip RAM Blocks
the External-Program-Memory Width to
D Flexible Boot-Program Loader 16 or 32 Bits
D On-Chip Memory-Mapped Peripherals: D Two Sets of Memory Strobes (STRB0 and
– One Serial Port STRB1) and One I / O Strobe (IOSTRB)
– Two 32-Bit Timers Allow Zero-Glue Logic Interface to Two
– Two-Channel Direct Memory Access Banks of Memory and One Bank of External
(DMA) Coprocessor With Configurable Peripherals
Priorities
D Separate Bus-Control Registers for Each
D Enhanced External Memory Interface That Strobe-Control Wait-State Generation,
Supports 8- / 16- / 32-Bit-Wide External RAM External Memory Width, and Data Type Size
for Data Access and Program Execution
From 16- / 32-Bit-Wide External RAM
D STRB0 and STRB1 Memory Strobes Handle
8-, 16-, or 32-Bit External Data Accesses
D TMS320C30 and TMS320C31 Object Code (Reads and Writes)
Compatible
D Multiprocessor Support Through the HOLD
D Fabricated using 0.7 µm Enhanced and HOLDA Signals Is Valid for All Strobes
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)

description
The TMS320C32 is the newest member of the TMS320C3x generation of digital signal processors ( DSPs) from
Texas Instruments. The TMS320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-µm
triple-level-metal CMOS technology. The enhancements to the TMS320C3x architecture include a
variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA
coprocessor with configurable priorities, flexible boot loader, relocatable interrupt-vector table, and edge- or
level-triggered interrupts.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and TI are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Copyright  1996, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

pin assignments

PCM PACKAGE †
( TOP VIEW )

STRB1_B2 / A –2

STRB0_B2 / A –2
STRB0_B3 / A –1
STRB1_B3 / A –1
STRB1_B0
STRB1_B1

STRB0_B0
STRB0_B1

IOSTRB

V SUBS
HOLDA
RESET
PRGW

DV DD

CLKIN
DV DD
DV SS

DV SS
HOLD
CV SS

CV SS
V DDL
V DDL
V SSL

IV SS
IACK

R/W
INT3
INT2
INT1
INT0

RDY
XF1
XF0
NC

NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
DR0 1 108 H3
DVDD 2 107 H1
FSR0 3 106 D0
CLKR0 4 105 D1
CLKX0 5 104 D2
FSX0 6 103 D3
DX0 7 102 DVDD
IVSS 8 101 D4
SHZ 9 100 D5
TCLK0 10 99 D6
TCLK1 11 98 D7
DVDD 12 97 D8
EMU3 13 96 D9
EMU0 14 95 VSSL
VDDL 15 94 VSSL
VDDL 16 93 DVSS
EMU1 17 92 CVSS
EMU2 18 91 D10
VSSL 19 90 DVDD
MCBL / MP 20 89 D11
CVSS 21 88 IVSS
DVSS 22 87 D12
A23 23 86 VDDL
A22 24 85 VDDL
A21 25 84 D13
A20 26 83 D14
A19 27 82 D15
A18 28 81 D16
DVDD 29 80 D17
A17 30 79 DVDD
A16 31 78 D18
A15 32 77 D19
A14 33 76 D20
A13 34 75 D21
CVSS 35 74 DVSS
DVSS 36 73 CVSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
A12

A10

V SSL
V SSL

D31
D30
D29
D28
D27
D26

D25

D24
D23
D22
A9
A8
A7
A6

A5
A4
A3
V DDL
V DDL
A2

A1

A0
A11

CVSS
DV SS

IV SS
NC

DVDD

DVDD

DVDD

DVDD

NC

† NC=No internal connection

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

Pin Assignments
PIN PIN PIN PIN PIN
NUMBER NAME NUMBER NAME NUMBER NAME NUMBER NAME NUMBER NAME
1 DR0 30 A17 59 DVDD 88 IVSS 117 RDY
2 DVDD 31 A16 60 D31 89 D11 118 IVSS
3 FSR0 32 A15 61 D30 90 DVDD 119 IOSTRB
4 CLKR0 33 A14 62 D29 91 D10 120 STRB0_B3 / A–1
5 CLKX0 34 A13 63 D28 92 CVSS 121 STRB0_B2 / A–2
6 FSX0 35 CVSS 64 D27 93 DVSS 122 STRB0_B1
7 DX0 36 DVSS 65 D26 94 VSSL 123 STRB0_B0
8 IVSS 37 NC 66 IVSS 95 VSSL 124 VDDL
9 SHZ 38 A12 67 D25 96 D9 125 VDDL
10 TCLK0 39 DVDD 68 DVDD 97 D8 126 STRB1_B3/ A–1
11 TCLK1 40 A11 69 D24 98 D7 127 VSSL
12 DVDD 41 A10 70 D23 99 D6 128 STRB1_B2/ A–2
13 EMU3 42 A9 71 D22 100 D5 129 DVDD
14 EMU0 43 A8 72 NC 101 D4 130 STRB1_B1
15 VDDL 44 A7 73 CVSS 102 DVDD 131 STRB1_B0
16 VDDL 45 A6 74 DVSS 103 D3 132 R/W
17 EMU1 46 DVDD 75 D21 104 D2 133 PRGW
18 EMU2 47 A5 76 D20 105 D1 134 RESET
19 VSSL 48 A4 77 D19 106 D0 135 CVSS
20 MCBL / MP 49 A3 78 D18 107 H1 136 DVSS
21 CVSS 50 VDDL 79 DVDD 108 H3 137 XF0
22 DVSS 51 VDDL 80 D17 109 NC 138 XF1
23 A23 52 A2 81 D16 110 VSUBS 139 IACK
24 A22 53 CVSS 82 D15 111 CVSS 140 INT0
25 A21 54 DVSS 83 D14 112 DVSS 141 INT1
26 A20 55 A1 84 D13 113 CLKIN 142 INT2
27 A19 56 VSSL 85 VDDL 114 HOLDA 143 INT3
28 A18 57 VSSL 86 VDDL 115 HOLD 144 NC
29 DVDD 58 A0 87 D12 116 DVDD

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

pin functions
This section provides signal descriptions for the TMS320C32 device. The following table lists each signal, the
number of pins, operating modes, and a brief signal description. The following table groups the signals
according to their function.

TMS320C32 Pin Functions

CONDITIONS
PIN WHEN
TYPE† DESCRIPTION
SIGNAL IS
NAME NO.
IN HIGH Z‡
EXTERNAL-BUS INTERFACE (70 PINS)
A23 – A0 24 O/Z 24-bit address port of the external-bus interface S H R
D31 – D0 32 I/O/Z 32-bit data port of the external-bus interface S H R
Read / write for external-memory interface. R / W is high when a read is performed
R/W 1 O/Z S H
and low when a write is performed over the parallel interface.
IOSTRB 1 O/Z External-peripheral I / O strobe for the external-memory interface S H
External-memory access strobe 0, byte enable 3 for 32-bit external-memory
STRB0_B3 / A –1 1 O/Z S H
interface, and address pin for 8-bit and 16-bit external-memory interface
External-memory access strobe 0, byte enable 2 for 32-bit external-memory
STRB0_B2 / A –2 1 O/Z S H
interface, and address pin for 8-bit external-memory interface
External-memory access strobe 0, byte enable 1 for the external-memory
STRB0_B1 1 O/Z S H
interface
External-memory access strobe 0, byte enable 0 for the external-memory
STRB0_B0 1 O/Z S H
interface
External-memory access strobe 1, byte enable 3 for 32-bit external-memory
STRB1_B3 / A –1 1 O/Z S H
interface, and address pin for 8-bit and 16-bit external-memory interface
External-memory access strobe 1, byte enable 2 for 32-bit external-memory
STRB1_B2 / A –2 1 O/Z S H
interface, and address pin for 8-bit external-memory interface
External-memory access strobe 1, byte enable 1 for the external-memory
STRB1_B1 1 O/Z S H
interface
External-memory access strobe 1, byte enable 0 for the external-memory
STRB1_B0 1 O/Z S H
interface
Ready. RDY indicates that the external device is prepared for an external-
RDY 1 I
memory interface transaction to complete.
Hold signal for external-memory interface. When HOLD is a logic low, any
ongoing transaction is completed. A23 – A0, D31 – D0, IOSTRB, STRB0_Bx,
HOLD 1 I STRB1_Bx, and R / W are placed in the high-impedance state, and all
transactions over the external-memory interface are held until HOLD becomes a
logic high or the NOHOLD bit of the STRB0 bus-control register is set.
Hold acknowledge for external-memory interface. HOLDA is generated in
response to a logic low on HOLD. HOLDA indicates that A23 – A0, D31 – D0,
IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are in the high-impedance state and
HOLDA 1 O/Z S
that all transactions over the memory are held. HOLDA is high in response to a
logic high of HOLD or when the NOHOLD bit of the external bus-control register
is set.
Program memory width select. When PRGW is a logic low, program is fetched as
a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are
PRGW 1 I
performed to fetch a single 32-bit instruction word. The status of PRGW at device
reset affects the reset value of the STRB0 and STRB1 bus-control register.
A23 – A0 24 O/Z 24-bit address port of the external-bus interface S H R
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

TMS320C32 Pin Functions (Continued)

CONDITIONS
PIN WHEN
TYPE† DESCRIPTION
SIGNAL IS
NAME NO.
IN HIGH Z‡
CONTROL SIGNALS (9 PINS)
Reset. When RESET is a logic low, the device is in the reset condition. When
RESET 1 I RESET becomes a logic high, execution begins from the location specified by the
reset vector.
INT3 – INT0 4 I External interrupts
Interrupt acknowledge. IACK is generated by the IACK instruction. This signal can
IACK 1 O/Z S
be used to indicate the beginning or end of an interrupt-service routine.
MCBL / MP 1 I Microcomputer boot loader / microprocessor mode
External flags. XF1 and XF0 are used as general-purpose I / Os or used to support
XF1 – XF0 2 I/O/Z S R
interlocked-processor instructions.
SERIAL PORT SIGNALS (6 PINS)
Serial-port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
CLKX0 1 I/O/Z S R
transmitter.
DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the
FSX0 1 I/O/Z S R
transmit-data process over DX0.
Serial-port 0 receive clock. CLKR0 is the serial-shift clock for the serial-port 0
CLKR0 1 I/O/Z S R
receiver.
DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R
Frame-synchronization pulse for receive. The FSR0 pulse initiates the
FSR0 1 I/O/Z S R
receive-data process over DR0.
TIMER SIGNALS (2 PINS)
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
TCLK0 1 I/O/Z S R
an output, TCLK0 outputs pulses generated by timer 0.
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
TCLK1 1 I/O/Z S R
an output, TCLK1 outputs pulses generated by timer 1.
CLOCK SIGNALS (3 PINS)
CLKIN 1 I Input to the internal oscillator from an external clock source
H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S
H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S
RESERVED (5 PINS)
EMU0 – EMU2 3 I Reserved for emulation. Use 18 kΩ – 22 kΩ pullup resistors to 5 V.
EMU3 1 O/Z Reserved for emulation S
Shutdown high impedance. When active, SHZ shuts down the ’C32 and places
all 3-state I/O pins in the high-impedance state. SHZ is used for board-level testing
SHZ 1 I to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts
’C32 memory and register contents. Reset the device with SHZ high to restore it
to a known operating condition.
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

TMS320C32 Pin Functions (Continued)

CONDITIONS
PIN WHEN
TYPE† DESCRIPTION
SIGNAL IS
NAME NO.
IN HIGH Z‡
POWER / GROUND
CVSS 7 I Ground
DVSS 7 I Ground
IVSS 4 I Ground
DVDD 12 I + 5-V dc supply§
VDDL 8 I + 5-V dc supply§
VSSL 6 I Ground
VSUBS 1 I Substrate, tie to ground
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling capacitor is 0.1 µF.

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

functional block diagram

Program
Cache
(64 × 32)
RAM
Block 0
(256 × 32)
RAM
Block 1
(256 × 32) ÉÉÉ Boot
ROM

32 24 24 32 24 32 24 32
A23 – A0
32 D31 – D0
IR PDATA Bus
R/W
PC PADDR Bus RDY
24 External
HOLD
Memory
DDATA Bus Interface HOLDA

Multiplexer
RESET PRGW
DADDR1 Bus
INT(3-0)
IACK DADDR2 Bus
XF(1,0)
H1
Controller

DMADATA Bus
H3
MCBL / MP DMAADDR Bus
CLKIN
VDD Multiplexer STRB0_B3/A–1
VSS
STRB0_B2/A–2
SHZ DMA Controller STRB0
STRB0_B1
EMU0–3
STRB0 Control Reg. STRB0_B0
DMA Channel 0
STRB1 STRB1_B3/A–1
Global-Contol Register
Multiplexer STRB1_B2/A–2
Source-Address Register STRB1 Control Reg. STRB1_B1
CPU1 Destination-Address Reg. STRB1_B0
IOSTRB
IOSTRB
CPU2 Transfer-Counter Reg.

Peripheral Address Bus

IOSTRB Control Reg.

Peripheral Data Bus

DMA Channel 1

ÉÉÉÉ
REG1
Global-Control Register
REG2
Serial Port

ÉÉÉÉÉ
ÉÉÉÉ
Source-Address Register
32 32 40 40 FSX0
CPU1

REG1

REG2

Destination-Address Reg.
Serial Port- DX0

ÉÉÉÉ
ÉÉÉÉÉ
32-Bit Transfer-Counter Reg. Control Reg.
Multiplier Barrel CLKX0
Shifter Receive/Transmit FSR0

ÉÉÉÉ
(R/X)Timer Register
ALU DR0
40 Data-Transmit
Register CLKR0
40
40 Data-Receive
Extended- 40 Register
40 Precision
Registers 40
32
(R0–R7)

Timer 0
DISP0, IR0, IR1 Global-Control
Register TCLK0
Timer-Period
ARAU0 ARAU1 Register
BK
Timer-Counter
Register
24
24
24 Auxiliary 24
Registers Timer 1
32
(AR0 – AR7)
32 Global-Control
32 Register
Timer-Period TCLK1
32 Register
Other 32 Timer-Counter
32 Register
Registers
(12)

operation
Operation of the TMS320C32 is identical to the TMS320C30 and TMS320C31 digital signal processors, with
the exception of an enhanced external memory interface and the addition of two CPU power-management
modes.
external-memory interface
The TMS320C32 has a configurable external-memory interface with a 24-bit address bus, a 32-bit data bus,
and three independent multifunction strobes. The flexibility of this unique interface enables product designers
to minimize external-memory chip count.

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

external memory interface (continued)

Up to three mutually exclusive memory areas (one program area and two data areas) can be implemented. Each
memory area configuration is independent of the physical memory width and independent of the configuration
of other memory areas. See Figure 1.

8-/16-/32-Bit Data in
’C32 8-/16-/32-Bit-Wide Memory
STRB0
32-Bit Program in 16-/32-Bit-
Wide Memory

32-Bit
PRGW Pin
CPU 8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
STRB1
32-Bit Program in 16-/32-Bit-
Wide Memory
Memory
Strobe-
Interface
Control
32-Bit Data in 32-Bit-Wide
Registers
Memory
IOSTRB
32-Bit Program in 32-Bit-
Wide Memory

Figure 1. ’C32 External Memory Interface

The TMS320C32’s external-memory configuration is controlled by a combination of hardware configuration and

memory-mapped control registers and can be reconfigured dynamically. The signals that control
external-memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows:
D The TMS320C32 is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The
external-memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit
half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high,
32 bits if the PRGW signal is low.
D STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of
external-memory addresses. When an address within one of these ranges is accessed by a read or write
instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the
TMS320C32 memory map, showing the address ranges for which the strobe signals become active.
The behavior of the STRB0 and STRB1 control signals is determined by the contents of the STRB0 and STRB1
control registers.
The STRB0 and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or
32 bits) of the external-memory address ranges they control. Another field specifies the data width (8, 16, or
32 bits) of the data contained in those addresses. The values in these fields are not required to match. For
example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four
consecutive 8-bit locations, each having its own address.
Each control-signal set has two pins (STRBx_B2/A–2 and STRBx_B3/A–1) that can act as either byte-enable
(chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and
STRBx_B1). The pin functions are determined by the physical memory width specified in the corresponding
control register.

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

external memory interface (continued)

D For 8-bit-wide physical memory, the STRBx_B2/A–2 and STRBx_B3/A–1 pins function as address pins
(least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin.
STRBx_B1 is unused. See Figure 2.

8-Bit Data Bus

8
Data
TMS320C32 A14
A13
A12 A14 Data
. .

Memory
. .
A1 A3
A0 A2
A1
STRB0_B3/ A –1 A0 CS
STRB0_B2/ A –2
STRB0_B1 NC
STRB0_B0

Figure 2. ’C32 With 8-Bit-Wide External Memory

D For 16-bit-wide physical memory, the STRBx_B3/A–1 pin functions as an address pin (least significant
address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins.
STRBx_B2/A–2 is unused. See Figure 3.

16-Bit Data Bus

16

8 8
Data
TMS320C32

A14
A13 A14 Data A14 Data
. . .
Memory
Memory

. . .
A2 A3 A3
A1 A2 A2
A0 A1 A1
A0 A0
CS CS
STRB0_B3/ A –1
STRB0_B2 / A –2 NC
STRB0_B1
STRB0_B0

Figure 3. ’C32 With 16-Bit-Wide External Memory

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

external memory interface (continued)

D For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins.
See Figure 4.

32-Bit Data Bus

32

8 8 8 8
Data
TMS320C32

A14 A14 Data A14 Data A14 Data A14 Data

A13 A13 A13 A13 A13

Memory

Memory
Memory

Memory
. . . . .
. . . . .
A2 A2 A2 A2 A2
A1 A1 A1 A1 A1
A0 A0 CS A0 CS A0 CS A0 CS

STRB0_B3/A –1
STRB0_B2/A –2
STRB0_B1
STRB0_B0

Figure 4. ’C32 With 32-Bit-Wide External Memory

For more detailed information and examples see TMS320C32 Addendum to the TMS320C3x User’s Guide
(literature number SPRU132) and Interfacing Memory to the TMS320C32 DSP Application Report (literature
number SPRA040).
D The IOSTRB control signal, like STRB0 and STRB1, also is mapped to a specific range of addresses but
it is a single signal that can access only 32-bit data from 32-bit-wide memory. Its range of addresses appears
in the TMS320C32 memory map, shown in Figure 8. The IOSTRB bus timing is different from the STRB0
and STRB1 bus timings to accommodate slower I/O peripherals.

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

external memory interface (continued)

examples
Figure 5 and Figure 6 show examples of external memory configurations that can be implemented using the
TMS320C32 external memory interface. The first example has a 32-bit-wide external memory with 8- and 16-bit
data areas and a 32-bit program area.
32-Bit-Wide Memory

8-Bit Data 8-Bit Data 8-Bit Data 8-Bit Data

320C32 32-Bit Program

16-Bit Data 16-Bit Data

8 8 8 8
32

32-Bit-Wide Data Bus

Figure 5. 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit Program
Memory

Figure 6 shows a configuration that can be implemented with 16-bit external memory. The 32-bit data and
program words can be stored and retrieved as half-words.
16-Bit-Wide Memory

8-Bit Data 8-Bit Data

320C32 32-Bit Program

16-Bit Data

8 8
16

16-Bit-Wide Data Bus

Figure 6. 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit Program
Area

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

external memory interface (continued)

Figure 7 shows one possible configuration that can be implemented with 8-bit external memory. Program words,
which are 32-bit, cannot be executed from 8-bit-wide memory.
8-Bit-Wide Memory

8-Bit Data

320C32

16-Bit Data

8
8

8-Bit-Wide Data Bus

Figure 7. 8-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

memory map
Figure 8 depicts the memory map for the TMS320C32. Refer to theTMS320C32 Addendum to the TMS320C3x
User’s Guide (literature number SPRU132) for a detailed description of this memory mapping, with shading to
indicate external memory.
0h 0h
Reserved for
Reset-Vector Location
FFFh Boot-Loader Operations
1000h Boot 1
1001h
External Memory External Memory
STRB0 Active STRB0 Active
(8.192M Words) (8.188M Words)

7FFFFFh 7FFFFFh
800000h 800000h
Reserved Reserved
(32K Words) (32K Words)
807FFFh 807FFFh
808000h Peripheral-Bus 808000h Peripheral-Bus
Memory-Mapped Registers Memory-Mapped Registers
8097FFh (6K-Word Internal) 8097FFh (6K-Word Internal)
809800h 809800h
Reserved Reserved
(26K Words) (26K Words)
80FFFFh 80FFFFh
810000h 810000h Boot 2
810001h

External Memory External Memory

IOSTRB Active IOSTRB Active
(128K Words) (128K Words)

82FFFFh 82FFFFh
830000h Reserved 830000h Reserved
87FDFFh (314.5K Words) 87FDFFh (319.5K Words)
87FE00h RAM Block 0 87FE00h
(256-Word Internal) RAM Block 0 (256-Word Internal)
87FEFFh 87FEFFh
87FF00h RAM Block 1 87FF00h
RAM Block 1 (256-Word Internal)
87FFFFh (256-Word Internal) 87FFFFh
880000h 880000h
External Memory External Memory
STRB0 Active STRB0 Active

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
(512K Words) (512K Words)
8FFFFFh 8FFFFFh

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
900000h 900000h Boot 3

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
External Memory 900001h External Memory
STRB1 Active
STRB1 Active

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
(7.168M Words)
(7.168M Words)
FFFFFFh FFFFFFh

Microprocessor Mode Microcomputer/Boot-LoaderMode

Figure 8. TMS320C32 Memory Map

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

power management
The TMS320C32 CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2
mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the
external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal
is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to
execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN
frequency divided by 16 (that is, TMS320C32 with a 32-MHz CLKIN frequency performs the same as a 2-MHz
TMS320C32 with an instruction cycle time of 1000 ns (1 MHz).
boot loader
The TMS320C32 flexible boot loader loads programs from the serial port, EPROM, or other standard
non-volatile memory device. The boot-loader functionality of the TMS320C32 is equivalent to that of the
TMS320C31, and has added modes to handle the data-type sizes and memory widths supported by the external
memory interface. The memory-boot load supports data transfers with and without handshaking. The
handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and
data-ready signals.
peripherals
The TMS320C32 peripherals are composed of one serial port, two timers, and two DMA channels. The serial
port and timers are the functional equivalent of those in the TMS320C31 peripherals. The TMS320C32
two-channel DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA.

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

peripherals (continued)

Figure 9 shows the TMS320C32’s peripheral-bus control-register mapping, with the reserved areas shaded.

808000h DMA 0 Global Control

808004h DMA 0 Source Address

808006h DMA 0 Destination Address

808008h DMA 0 Transfer Counter

808009h
808010h DMA 1 Global Control

808014h DMA 1 Source Address

808016h DMA 1 Destination Address

808018h DMA 1 Transfer Counter

808020h Timer 0 Global Control

808024h Timer 0 Counter

808028h Timer 0 Period

808030h Timer 1 Global Control

808034h Timer 1 Counter

808038h Timer 1 Period Register

808040h Serial Port Global Control

808042h FSX/DX/CLKX Port Control

808043h FSR/DR/CLKR Port Control

808044h R/X Timer Control

808045h R/X Timer Counter

808046h R/X Timer Period

808048h Data Transmit

80804Ch Data Receive

808050h
Reserved
80805Fh
808060h IOSTRB-Bus Control

808064h STRB0-Bus Control

808068h STRB1-Bus Control

808069h Reserved
Reserved
8097FFh

Figure 9. Peripheral-Bus Memory-Mapped Registers

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

interrupts
To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered.
Unlike the fixed interrupt-trap vector-table location of the TMS320C30 and TMS320C31 devices, the
TMS320C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a
256-word boundary. Figure 10 shows the interrupt and trap vector locations memory mapping with shading to
indicate reserved areas. The reset vector is fixed to address 0h as shown in Figure 8.

EA (ITTP) + 00h Reserved

EA (ITTP) + 01h INT0

EA (ITTP) + 02h INT1

EA (ITTP) + 03h INT2

EA (ITTP) + 04h INT3

EA (ITTP) + 05h XINT0

EA (ITTP) + 06h RINT0

EA (ITTP) + 07h Reserved

EA (ITTP) + 08h Reserved

EA (ITTP) + 09h TINT0

EA (ITTP) + 0Ah TINT1

EA (ITTP) + 0Bh DINT0

EA (ITTP) + 0Ch DINT1

EA (ITTP) + 0Dh
Reserved
EA (ITTP) + 1Fh

EA (ITTP) + 20h TRAP0

.
.
.
.

EA (ITTP) + 3Bh TRAP27

EA (ITTP) + 3Ch TRAP28

EA (ITTP) + 3Dh TRAP29

EA (ITTP) + 3Eh TRAP30

EA (ITTP) + 3Fh TRAP31 Reserved

Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

absolute maximum ratings over specified temperature ranges (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W
Operating case temperature, TC (PCM (commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
(PCMA (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. This value calculated for the ’C32-40. Actual operating power is less. This value was obtained under specially produced worst-case
test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of
a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD) current specification in the electrical
characteristics table and refer the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRU031).

recommended operating conditions (see Note 3)‡

MIN NOM‡ MAX UNIT
VDD Supply voltage (DVDD, VDDL) 4.75 5 5.25 V
VSS Supply voltage (CVSS, VSSL, IVSS, DVSS, VSUBS) 0 V
CLKIN 2.6 VDD + 0.3§ V
VIH High level input voltage
High-level
All other inputs 2 VDD + 0.3§ V
VIL Low-level input voltage – 0.3§ 0.8 V
IOH High-level output current – 300 µA
IOL Low-level output current 2 mA
Operating case temperature (commercial) 0 85 °C
TC
Operating case temperature (extended) – 40 125 °C
‡ All nominal values are at VDD = 5 V, TA (ambient air temperature)= 25°C.
§ These values are derived from characterization and not tested.
NOTE 3: All input and output voltage levels are TTL compatible.

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)†‡
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VOH High-level output voltage VDD = MIN, IOH = MAX 2.4 3 V
VOL Low-level output voltage VDD = MIN, IOL = MAX 0.3 0.6§ V
IOZ High-impedance state output current VDD = MAX – 20 20 µA
II Input current VI = VSS to VDD – 10 10 µA
fx = 40 MHz TA = 25
25°C,
C, 160 390
fx = 50 MHz VDD = MAX, 200 425 mA
Supply current fx = MAX‡
IDD fx = 60 MHz 225 475
(see Note 4)
IDLE2,
Standby 50 µA
CLKIN shut off
All other
CI Input capacitance 15¶ pF
inputs
Co Output capacitance 20¶ pF
† All nominal values are at VDD = 5 V, TA (ambient air temperature) = 25°C.
‡ fx is the input clock frequency.
§ VOL(max) = 0.7 V for A(0:23)
¶ Assured by design but not tested
NOTE 4: Actual operating current is less than this maximum value (reference Note 2).

PARAMETER MEASUREMENT INFORMATION

IOL

Output
Tester Pin VLoad Under
Electronics Test
CT

IOH

Where: IOL = 2 mA (all outputs)

IOH = 300 µA (all outputs)
VLoad = 2.15 V
CT = 80-pF typical load-circuit capacitance
Figure 11. Test Load Circuit

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

signal-transition levels for ’C32 (see Figure 12 and Figure 13)

TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified in the following paragraph.
For a high-to-low transition on an output signal, the level at which the output is said to be no longer high is
2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level at which the
output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V ( see Figure 12 ).
2.4 V
2V

1V
0.6 V

Figure 12. ’C32 Output Levels

Transition times for TTL-compatible inputs are specified as follows. For a high-to-low transition on an input
signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to
be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer
low is 0.8 V and the level at which the input is said to be high is 2 V ( see Figure 13 ).
2V

0.8 V

Figure 13. ’C32 Input Levels

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

timing parameter symbology

Timing parameter symbols used in this document are in accordance with JEDEC Standard 100-A. Unless
otherwise noted, in order to shorten the symbols, pin names and other related terminology have been
abbreviated as follows:

A23– A0 when the physical-memory-width-bit field of the STRBx control register is set to 32 bits
A23– A0 and STRBx_B3/A–1 when the physical-memory-width-bit field of the STRBx control register is
A set to 16 bits
A23– A0, STRBx_B3/A–1, and STRBx_B2/A–2 when the physical-memory-width-bit field of the STRBx
control register is set to 8 bits
CI CLKIN
RDY RDY
D D(31 – 0)
H H1, H3
IOS IOSTRB
P tc(H)
Q tc(CI)
RW R/ W
STRBx_B(3– 0) when the physical-memory-width-bit field of the STRBx control register is set to 32 bits
S STRBx_B(1– 0) when the physical-memory-width-bit field of the STRBx control register is set to 16 bits
STRBx_B0 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits
XF XF0 or XF1

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

operating characteristics for CLKIN, H1 and H3 [Q = tc(CI)] (see Figure 14 and Figure 15)
TEST ’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. PARAMETERS UNIT
CONDITIONS MIN MAX MIN MAX MIN MAX
1 tf(CI) Fall time, CLKIN 5‡ 5‡ 4‡ ns
2 tw(CIL) Pulse duration, CLKIN low Q = MIN 9 7 6 ns
3 tw(CIH) Pulse duration, CLKIN high Q = MIN 9† 8† 6† ns
4 tr(CI) Rise time, CLKIN 5‡ 5‡ 4‡ ns
5 tc(CI) Cycle time, CLKIN 25 303 20 303 16.67 303 ns
6 tf(H) Fall time, H1 / H3 3 3 3 ns
7 tw(HL) Pulse duration, H1 / H3 low Q–5 Q–5 Q–4 ns
8 tw(HH) Pulse duration, H1 / H3 high Q–6 Q–6 Q–5 ns
9 tr(H) Rise time, H1 / H3 3 3 3 ns
9.1 td(HL-HH) Delay time, H1 / H3 low to H1 / H3 high 0 4 0 4 0 4 ns
10 tc(H) Cycle time, H1 / H3 50 606 40 606 33.33 606 ns
† The minimum CLKIN high pulse duration at 3.3 MHz is 10 ns.
‡ Assured by design but not tested

5
4
1

CLKIN

3
2

Figure 14. CLKIN Timing

10

9 6

H1 8

7
9.1

9.1

H3
8

9
6
7
10

Figure 15. H1 / H3 Timing

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
11 td(H1L - SL) Delay time, H1 low to STRBx low 0† 11 0† 9 0† 7 ns
12 td(H1L - SH) Delay time, H1 low to STRBx high 0† 11 0† 9 0† 7 ns
13 td(H1H - RWL) Delay time, H1 high to R / W low (read) 0† 11 0† 9 0† 8 ns
14 td(H1L - A) Delay time, H1 low to A valid 0† 11 0† 9 0† 7 ns
15 tsu(D)R Setup time, D valid before H1 low (read) 13 10 10 ns
16 th(D)R Hold time, D after H1 low (read) 0 0 0 ns
17 tsu(RDY) Setup time, RDY before H1 low 21 19 17 ns
18 th(RDY) Hold time, RDY after H1 low 0 0 0 ns
19 td(H1H - RWH) Delay time, H1 high to R / W high (write) 11 9 8 ns
20 tv(D)W Valid time, D after H1 low (write) 17 14 12 ns
21 th(D)W Hold time, D after H1 high (write) 0 0 0 ns
Delay time, H1 high to A valid on back-to-back write
22 td(H1H - A) 11 9 8 ns
cycles
† Assured from characterization but not tested

H3

H1

11 12
STRBx ‡

R/W 15
14
13

16

18
17
RDY

‡ STRBx remains low during back-to-back operations.

Figure 16. Memory-Read-Cycle Timing

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
(continued)

H3

H1

11
12

STRBx

13 19

R/W

14 22

20 21

18

RDY

17

Figure 17. Memory-Write-Cycle Timing

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

memory-read-cycle timing using IOSTRB (see Figure 18)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
11.1 td(H3L-IOSL) Delay time, H3 low to IOSTRB low 0† 11 0† 9 0† 8 ns
12.1 td(H3L-IOSH) Delay time, H3 low to IOSTRB high 0† 11 0† 9 0† 8 ns
13.1 td(H1L-RWL) Delay time, H1 low to R / W high 0† 11 0† 9 0† 8 ns
14.1 td(H1L-A) Delay time, H1 low to A valid 0† 11 0† 9 0† 8 ns
15.1 tsu(D)R Setup time, D before H1 high 13 10 9 ns
16.1 th(D)R Hold time, D after H1 high 0 0 0 ns
17.1 tsu(RDY) Setup time, RDY before H1 high 9 8 7 ns
18.1 th(RDY) Hold time, RDY after H1 high 0 0 0 ns
23 td(H1L-RWH) Delay time, H1 low to R / W low 0† 11 0† 9 0† 8 ns
† Assured from characterization but not tested

H3

H1

11.1 12.1

IOSTRB

13.1 23†

R/W

14.1

15.1
16.1

17.1
18.1
RDY

† See Figure 19 and accompanying table.

Figure 18. Memory-Read-Cycle Timing Using IOSTRB

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

memory-write-cycle timing using IOSTRB (see Figure 19)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
11.1 td(H3L-IOSL) Delay time, H3 low to IOSTRB low 0† 11 0† 9 0† 8 ns
12.1 td(H3L-IOSH) Delay time, H3 low to IOSTRB high 0† 11 0† 9 0† 8 ns
13.1 td(H1L-RWL) Delay time, H1 low to R / W high 0† 11 0† 9 0† 8 ns
14.1 td(H1L-A) Delay time, H1 low to A valid 0† 11 0† 9 0† 8 ns
17.1 tsu(RDY) Setup time, RDY before H1 high 9 8 7 ns
18.1 th(RDY) Hold time, RDY after H1 high 0 0 0 ns
23 td(H1L-RWH) Delay time, H1 low to R / W low 0† 11 0† 9 0† 8 ns
24 tv(D)W Valid time, D after H1 high 17 14 12 ns
25 th(D)W Hold time, D after H1 low 0 0 0 ns
† Assured from characterization but not tested

H3

H1

11.1† 12.1†

IOSTRB

13.1†
23†

R/W

14.1†

24 25

17.1†
18.1†

RDY

† See Figure 18 and accompanying table.

Figure 19. Memory-Write-Cycle Timing Using IOSTRB

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for XF0 and XF1 when executing LDFI or LDII (see Figure 20)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
38 td(H3H-XF0L) Delay time, H3 high to XF0 low 13 12 11 ns
39 tsu(XF1) Setup time, XF1 before H1 low 9 9 8 ns
40 th(XF1) Hold time, XF1 after H1 low 0 0 0 ns

Fetch
LDFI or LDII Decode Read Execute
H3

H1

STRBx

R/W

RDY

38

XF0 39

40

XF1

Figure 20. XF0 and XF1 When Executing LDFI or LDII

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for XF0 when executing STFI or STII † (see Figure 21)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO. MIN MAX MIN MAX MIN MAX UNIT
41 td(H3H-XF0H) Delay time, H3 high to XF0 high 13 12 11 ns
† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from
executing, the address of the store is not driven until the store can execute.

Fetch
STFI or STII Decode Read Execute
H3

H1

STRBx

R/W

RDY 41

XF0

Figure 21. XF0 When Executing a STFI or STII

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for XF0 and XF1 when executing SIGI (see Figure 22)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
41.1 td(H3H-XF0L) Delay time, H3 high to XF0 low 13 12 11 ns
42 td(H3H-XF0H) Delay time, H3 high to XF0 high 13 12 11 ns
43 tsu(XF1) Setup time, XF1 before H1 low 9 9 8 ns
44 th(XF1) Hold time, XF1 after H1 low 0 0 0 ns

Fetch
SIGI Decode Read Execute

H3

H1
41.1
43 42

XF0

44

XF1

Figure 22. XF0 and XF1 When Executing SIGI

timing for loading XF register when configured as an output pin (see Figure 23)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
45 tv(H3H-XF) Valid time, H3 high to XF valid 13 12 11 ns

Fetch Load
Instruction Decode Read Execute
H3

H1

OUTXF Bit† 1 or 0

45

XFx

† OUTXFx represents either bit 2 or 6 of the IOF register.

Figure 23. Loading XF Register When Configured as an Output Pin

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing of XF changing from output to input mode (see Figure 24)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
46 th(H3H-XF01) Hold time, XF after H3 high 13† 12† 11† ns
47 tsu(XF) Setup time, XF before H1 low 9 9 8 ns
48 th(XF) Hold time, XF after H1 low 0 0 0 ns
† Assured from characterization but not tested

Buffers Go
Execute from Ouput Synchronizer Value on Pin
Load of IOF to Input Delay Seen in IOF
H3

H1

I / OXFx Bit† 47
48
46

XFx Output

INXFx Bit†
Data
Sampled
Data
Seen
† I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.

Figure 24. Change of XF From Output to Input Mode

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing of XF changing from input to output mode (see Figure 25)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
49 td(H3H-XFIO) Delay time, H3 high to XF switching from input to output 17 17 15 ns

Execution of
Load of IOF

H3

H1

I / OXFx Bit†

49

XFx

† I / OXFx represents either bit 1 or bit 5 of the IOF register.

Figure 25. Change of XF From Input to Output Mode

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 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for RESET [Q = tc(CI)] (see Figure 26)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
50 tsu(RESET) Setup time, RESET before CLKIN low 10 Q† 10 Q† 7 Q† ns
51 td(CLKINH-H1H) Delay time, CLKIN high to H1 high 2 12 2 10 2 10 ns
52 td(CLKINH-H1L) Delay time, CLKIN high to H1 low 2 12 2 10 2 10 ns
Setup time, RESET high before H1 low and
53 tsu(RESETH-H1L) 9 7 6 ns
after ten H1 clock cycles
54 td(CLKINH-H3L) Delay time, CLKIN high to H3 low 2 12 2 10 2 10 ns
55 td(CLKINH-H3H) Delay time, CLKIN high to H3 high 2 12 2 10 2 10 ns
Disable time, H1 low to D in the
56 tdis(H1H-D) 13‡ 12‡ 11‡ ns
high-impedance state
Disable time, H3 low to A in the
57 tdis(H3HL-A) 9‡ 8‡ 7‡ ns
high-impedance state
58.1 td(H3H-CONTROLH) Delay time, H3 high to control signals high 9‡ 8‡ 7‡ ns
58.2 td(H1H-RWH) Delay time, H1 low to R / W high 9‡ 8‡ 7‡ ns
59 td(H1H-IACKH) Delay time, H1 high to IACK high 9‡ 8‡ 7‡ ns
Disable time, RESET low to asynchronous
60 tdis(RESETL-ASYNCH) 21‡ 17‡ 14‡ ns
reset signals in the high-impedance state
† Assured by design but not tested
‡ Assured from characterization but not tested

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for RESET [Q = tc(CI)] (continued)

CLKIN
50
RESET†‡
51 52 53
H1
54
H3
10 H1 Clock Cycles
55 56
D§
57
A§
58.1
Control
Signals ¶
58.2
R/W
59
IACK

Asynchronous 60
Reset Signals #
† RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown
occurs; otherwise, an additional delay of one clock cycle can occur.
‡ The R / W output is placed in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 – 22 kΩ, if undesirable
spurious writes can occur when these outputs go low.
§ In microprocessor mode (MCBL / MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode
(MCBL / MP = 1), the reset vector is fetched two times, with no software wait states.
¶ Control signals include STRBx and IOSTRB.
# Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx .

Figure 26. RESET Timing

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for INT3 –INT0 interrupt response [P = tc(H)] (see Figure 27)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
61 tsu(INT) Setup time, INT3–INT0 before H1 low 13 10 8 ns
Pulse duration of interrupt to assure only one interrupt seen
62.1 tw(INT) P 2P† P 2P† P 2P† ns
for level-triggered interrupts
62.2 tw(INT) Pulse duration of interrupt for edge-triggered interrupts P† P† P† ns
† Assured from characterization but not tested.

Reset or Fetch First

Interrupt Instruction of
Vector Read Service Routine

H3

H1

61
INT3 – INT0 Pin

62.1
INT3 – INT0 Flag

62.2

A
Vector First
Address Instruction
Address

Figure 27. INT3–INT0 Interrupt-Response Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for IACK (see Notes 5 and Figure 28)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
63 td(H1H-IACKL) Delay time, H1 high to IACK low 9 7 6 ns
64 td(H1H-IACKH) Delay time, H1 high to IACK high 9 7 6 ns
NOTES: 5. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states.

Fetch IACK Decode IACK IACK Data

Instruction Instruction Read

H3

H1

63
64

IACK

Figure 28. IACK Timing

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 serial-port timing [P = tc(H)] (see Figure 29 and Figure 30)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
65 td(H1-SCK) Delay time, H1 high to internal CLKX / R high/low 13 10 8 ns
CLKX / R ext 2.6P 2.6P 2.6P
66 tc(SCK)
(SCK) Cycle time
time, CLKX / R ns
CLKX / R int 2P (232)P 2P (232)P 2P (232)P
CLKX / R ext P + 10 P + 10 P + 10
67 tw(SCK)
(SCK) Pulse duration
duration, CLKX / R high / low ns
CLKX / R int [tc(SCK) / 2] – 5 [tC(SCK) / 2] + 5 [tc(SCK) / 2] – 5 [tc(SCK) / 2] + 5 [tc(SCK) / 2] – 5 [tc(SCK) / 2] + 5
68 tr(SCK) Rise time, CLKX / R 7 6 5 ns
69 tf(SCK) Fall time, CLKX / R 7 6 5 ns
CLKX ext 30 24 20
70 td(DX) Delay time
time, CLKX to DX valid ns
CLKX int 17 16 15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CLKR ext 9 9 8
71 tsu(DR)
(DR) Setup time,
time DR before CLKR low ns
CLKR int 21 17 15
CLKR ext 9 7 6 ns
72 th(DR) Hold time,
time DR from CLKR low
CLKR int 0 0 0 ns

Delayy time,, CLKX to internal FSX CLKX ext 27 22 20

73 td(FSX) ns
high / low CLKX int 15 15 14
CLKR ext 9 7 6
74 tsu(FSR)
(FSR) Setup time,
time FSR before CLKR low ns
CLKR int 9 7 6

Hold time,, FSX / R input from CLKX / R CLKX / R ext 9 7 6

75 th(FS) ns
low CLKX / R int 0 0 0

Setup time,, external FSX before CLKX ext 8 – P† [tc(SCK) / 2]–10† 8 – P† [tc(SCK) / 2]–10† 8 – P† [tc(SCK) / 2]–10†
76 tsu(FSX)
(FSX) ns

SPRS027C – JANuARY 1995 – REVISED DECEMBER 1996

CLKX high CLKX int 21 – P† tc(SCK) / 2† 21 – P† tc(SCK) / 2† 21 – P† tc(SCK) / 2†

Delayy time,, CLKX to first DX bit,, FSX CLKX ext 30† 24† 20†

DIGITAL SIGNAL PROCESSOR

77 td(CH-DX)V
d(CH DX)V ns
precedes CLKX high CLKX int 18† 14† 12†
78 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 30† 24† 20† ns
Delay time, CLKX high to DX in the high-impedance
79 td(DXZ) 17† 14† 12† ns
state following last data bit
† Assured from characterization but not tested

TMS320C32
35
TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

serial-port timing [P = tc(H)] (see Figure 29 and Figure 30) (continued)

65 66

H1
65
67
67
CLKX / R
69
68
77 79
72 70

DX Bit n-1 Bit n-2 Bit 0

71
DR
Bit n-1 Bit n-2

FSR
74
73 73

75
FSX(INT)

FSX(EXT)
75
76

NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

Figure 29. Fixed Data-Rate-Mode Timing

CLKX / R
73

FSX(INT)
78
76

FSX(EXT) 70
79
77
DX Bit n-1 Bit n-2 Bit n-3 Bit 0
75

FSR
74

DR Bit n-1 Bit n-2 Bit n-3

71
72
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified
for the fixed data-rate mode.

Figure 30. Variable Data-Rate-Mode Timing

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for HOLD/HOLDA [P = tc(H)] (see Note 6 and Figure 31)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
80 tsu(HOLD) Setup time, HOLD before H1 low 13 10 8 ns
81 tv(HOLDA) Valid time, HOLDA after H1 low 0† 9 0† 7 0† 6 ns
82 tw(HOLD) Pulse duration, HOLD low 2P 2P 2P ns
83 tw(HOLDA) Pulse duration, HOLDA low P – 5† P – 5† P – 5† ns
84 td(H1L-SH)H Delay time, H1 low to STRBx high for a HOLD 0‡ 9 0‡ 7 0‡ 6 ns
84.1 td(H1H-IOS)H Delay time, H1 high to IOSTRB high for a HOLD 0‡ 9 0‡ 7 0‡ 6 ns
Disable time, H1 low to STRBx or IOSTRB (in the
85 tdis(H1L-S) 0‡ 9† 0‡ 8† 0‡ 7† ns
high-impedance state)
86 ten(H1L-S) Enable time, H1 low to STRBx or IOSTRB active 0‡ 9 0‡ 7 0‡ 6 ns
Disable time, H1 low to R/W in the
87 tdis(H1L-RW) 0† 9† 0† 8† 0† 7† ns
high-impedance state
88 ten(H1L-RW) Enable time, H1 low to R/W (active) 0† 9 0† 7 0† 6 ns
Disable time, H1 low to A in the high-impedance
89 tdis(H1L-A) 0‡ 10† 0‡ 8† 0‡ 7† ns
state
90 ten(H1L-A) Enable time, H1 low to A valid 0‡ 13 0‡ 12 0‡ 11 ns
Disable time, H1 high to D disabled in the
91 tdis(H1H-D) 0‡ 9† 0‡ 8† 0‡ 7† ns
high-impedance state
† Assured from characterization but not tested
‡ Not tested
NOTE 6: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The NOHOLD bit of the primary-bit-control register
overwrites the HOLD signal.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for HOLD/HOLDA [P = tc(H)] (see Note 6 and Figure 31) (continued)

H3

H1

80 80
82
HOLD
81 81
83
HOLDA
(see Note A)
84 85 86

STRBx
84.1 85 86
IOSTRB
88
87
R/W
89 90

A
91
D Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.

Figure 31. HOLD / HOLDA Timing

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing of peripheral pin configured as general-purpose I/O (see Figure 32)

’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
92 tsu(GPIOH1L) Setup time, general-purpose input before H1 low 10 9 8 ns
93 th(GPIOH1L) Hold time, general-purpose input after H1 low 0 0 0 ns
94 td(GPIOH1H) Delay time, general-purpose output after H1 high 13 10 8 ns

H3

H1
93
94
92 94
Peripheral Pin
(see Note A)

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.

Figure 32. Peripheral-Pin General-Purpose I / O Timing

timing of peripheral pin changing from general-purpose output to input mode (see Figure 33)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
95 th(H1H) Hold time, after H1 high 13 12 11 ns
96 tsu(GPI0H1L) Setup time, peripheral pin before H1 low 10 9 8 ns
97 th(GPIOH1L) Hold time, peripheral pin after H1 low 0 0 0 ns

Execute Store Value on

of Peripheral Buffers Pin Seen
Control Go From in
Output to Input Synchronizer Delay Peripheral
Register
Control Register

H3

H1

I/O 96
Control Bit 97

95
Peripheral Pin
(see Note A) Output

Data Bit

Data Sampled Data

Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.

Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input-Mode

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing of peripheral pin changing from general-purpose input to output mode (see Figure 34)
’C32 - 40 ’C32 - 50 ’C32 - 60
NO
NO. UNIT
MIN MAX MIN MAX MIN MAX
Delay time, H1 high to peripheral pin switching from input
98 td(GPIOH1H) 13 10 8 ns
to output

Execution of Store of
Peripheral Control
Register

H3

H1

I / O Control Bit

98

Peripheral Pin
(see Note A)

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.

Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input to Output Mode

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for timer pin [P = tc(H)] (see Figure 35)†

’C32 - 40
NO
NO. UNIT
MIN MAX
99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 10 ns
100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns
101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 9 ns
TCLK external 2.6P
102 tc(TCLK)
(TCLK) Cycle time
time, TCLK ns
TCLK internal 2P (232)P‡
TCLK external P + 10
103 tw(TCLK)
(TCLK) Pulse duration,
duration TCLK high / low ns
TCLK internal [tc(TCLK) / 2] – 5 [tc(TCLK) / 2]+5
† Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
‡ Assured by design but not tested
’C32 - 50
NO
NO. UNIT
MIN MAX
99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 8 ns
100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns
101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 9 ns
TCLK external 2.6P
102 tc(TCLK)
(TCLK) Cycle time
time, TCLK cycle time ns
TCLK internal 2P (232)P‡
TCLK external P + 10
103 tw(TCLK)
(TCLK) Pulse duration,
duration TCLK high / low ns
TCLK internal [tc(TCLK) / 2] – 5 [tc(TCLK) / 2]+5
† Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
‡ Assured by design but not tested

’C32 - 60
NO
NO. UNIT
MIN MAX
99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 6 ns
100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns
101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 8 ns
TCLK external 2.6P
102 tc(TCLK)
(TCLK) Cycle time
time, TCLK cycle time ns
TCLK internal 2P (232)P‡
TCLK external P + 10
103 tw(TCLK)
(TCLK) Pulse duration,
duration TCLK high / low ns
TCLK internal [tc(TCLK) / 2] – 5 [tc(TCLK) / 2]+5
† Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
‡ Assured by design but not tested

H3

H1
100 101
99 101
TCLKx
103
102

Figure 35. Timing for Timer Pin

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41

TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

timing for SHZ pin [Q = tc(CI)] (see Figure 36)

’C32 - 50† ’C32 - 60
UNIT
NO. MIN MAX MIN MAX
104 tdis(SHZ) Disable time, SHZ low to all O, I/O pins in the high-impedance state 0† 2Q† 0† 2Q† ns
† Assured by characterization but not tested

H3

H1

SHZ
(see Note A)

104

All I/O Pins

NOTE A: Enabling SHZ destroys ’C32 register and memory contents. Assert SHZ = 1 and reset the ’C32 to restore it to a known condition.

Figure 36. SHZ Pin Timing

Table 1. Thermal Resistance Characteristics for PCM package

PARAMETER MIN MAX UNIT
RΘJA Junction-to-free-air 39 °C / W
RΘJC Junction-to-case 10.0 °C / W

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

 TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

MECHANICAL DATA
PCM(S-PQFP-G***) PLASTIC QUAD FLATPACK
144 PIN SHOWN

108 73

109 72 0,38 0,13 M

0,22

0,65 TYP

NO. OF PINS*** A

144 22,75 TYP

160 25,35 TYP

144 37
0,16 NOM

1 36 3,60
A 3,20

28,20
SQ
27,80
31,45
SQ
30,95 0,25 MIN
0°– 7°

1,03
0,73

Seating Plane
0,10
4,10 MAX (see Note C)
4040015/A–10/93

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
D. The 144PCM is identical to 160PCM except that 4 leads per corner are removed.
E. Foot length is measured from lead tip to a position on backside of lead 0,25 mm above seating plane (gage plane)
F. Preliminary drawing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43

 PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TMS320C32PCM40 NRND QFP PCM 144 24 Pb-Free CU NIPDAU Level-4-245C-72HR
(RoHS)
TMS320C32PCM50 NRND QFP PCM 144 24 Pb-Free CU NIPDAU Level-4-245C-72HR
(RoHS)
TMS320C32PCM60 NRND QFP PCM 144 24 Pb-Free CU NIPDAU Level-4-245C-72HR
(RoHS)
TMS320C32PCMA40 NRND QFP PCM 144 24 Pb-Free CU NIPDAU Level-4-245C-72HR
(RoHS)
TMS320C32PCMA50 NRND QFP PCM 144 24 Pb-Free CU NIPDAU Level-4-245C-72HR
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

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Addendum-Page 1
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