Very Large Scale Integration
((VLSI
Lecture 3
Dr. Ahmed H. Madian
[email protected] Dr. Ahmed H. Madian-VLSI 1
Contents
Wiring tracks
Latch-up
Circuit characterization & performance
Resistance estimation
Capacitance estimation
Inductance estimation
Delay estimation
Simple RC model
Penfield-Rubenstein Model
Delay minimization techniques
Transistor sizing
Distributed drivers
Large driver
Wiring techniques
Dr. Ahmed H. Madian-VLSI 2
Wiring Tracks
A wiring track space required for a wire
4λ width, 4λ spacing from the neighbor=8 λ
Transistor consumes one wiring track
4λ
4λ
4λ
4λ
Dr. Ahmed H. Madian-VLSI 3
Area Estimation
Estimate Area by Counting wiring tracks
Multiply by 8 (4Width + 4Spacing) to express in λ
40λ
32λ
Dr. Ahmed H. Madian-VLSI 4
Latch up
Latch up is a condition that can occur in a circuit
fabricated in a bulk CMOS technology.
GND VDD
VDD
P
+N +N +P +P
N
N-well
P
N
Dr. Ahmed H. Madian-VLSI 5
Latch up Prevention
This could be corrected by:
Include an N-well contact every time a pFET is connected to VDD
Include an p-substrate contact every time a NFET is connected to
GND
GND GND VDD VDD
+N +N +P +P
N-well
P-substrate
Dr. Ahmed H. Madian-VLSI 6
Circuit characterization &
performance
Resistance estimation
Capacitance estimation
Inductance estimation
Delay estimation
Dr. Ahmed H. Madian-VLSI 7
Resistance estimation
Resistance of uniform slab
I
can be given as,
ρ l
R = . ohms
t w t
Where ρ = resistivity
t= thickness
l= conductor length w
l
w=conductor width
or, l
R = Rs . ohms
w
Rs is the sheet resistance Ω/
Dr. Ahmed H. Madian-VLSI 8
(.Resistance estimation (cont
Resistance of certain layers
Material Rs (Ω/ )
metal 0.03
Poly 15100
Diffusion p 80
Diffusion n 35
Silicide 24
N-well 1K 5K
Dr. Ahmed H. Madian-VLSI 9
Resistance estimation
For MOSFET channel resistance
Rchannel = RSheet (L/W)
+N L +N
where Rsheet = 1/µCOX(Vgs-Vt)
L
For P and n channels
Rsheet = 1000 ->30,000 Ω/ channel
W
Dr. Ahmed H. Madian-VLSI 10
(.Resistance estimation (cont
Resistance of non rectangular regions
W1
W2
L L L
W1
Ratio = 2L/(L+2W1) W W2
Ratio =L/W Ratio =L/W
W2 W2
W2
W1 W2
W1
W1 Ratio =W1/W2 W1
Ratio =W2/W1
Dr. Ahmed H. Madian-VLSI 11
Inverter resistance estimation
CMOS inverter (no static
VDD
current) VDD
Switching current Vin Vout
VDD VDD
I max = = Rs,p (L/W) MP
Rtotal R L L
s, p + Rs , n IL VOUT = VDS
W W Vin
for L =W =1 IDS
VDD VDD VDD Rs,n (L/W) MN
I max = = =
Rs , p + Rs , n 25 + 10 35 VGS
2
V DD
switching power loss = I max .VDD =
35
Dr. Ahmed H. Madian-VLSI 12
Circuit characterization &
performance
Resistance estimation
Capacitance estimation
Transistor capacitance
Routing capacitance
Inductance estimation
Delay estimation
Dr. Ahmed H. Madian-VLSI 13
Capacitance estimation
The dynamic response of MOS systems strongly depends on
the parasitic capacitances associated with the MOS device.
The total load capacitance on the output of a CMOS gate is
the sum of:
gate capacitance (of other inputs connected to out)
diffusion capacitance (of drain/source regions) drain
routing capacitances (output to other inputs)
CGD CDB
gate substrate
CGS CSB
source
CGB
Dr. Ahmed H. Madian-VLSI 14
(.Capacitance estimation (cont
gate
Gate capacitance Cgate insulator
Diffusion capacitance +n
substrate
Routing capacitance C.diff
Metal layer
Cdiff >Cpoly>Cm1>Cm2
gate Crouting
+n
substrate
Dr. Ahmed H. Madian-VLSI 15
Capacitance estimation
In general, capacitance could be calculated using
ε . A ε o .ε r . A
C= =
d d
ε o .ε r
C/ unit area = = Cox d
d
Dr. Ahmed H. Madian-VLSI 16
Gate Capacitance
Cg = Cgs + Cgd + Cgb
Dr. Ahmed H. Madian-VLSI 17
(.Capacitance estimation (cont
b
Diffusion capacitance (source/drain)
Source Drain
a Diffusion Diffusion
Area Area
C Ja Gate
CJP
insulator
Side wall capacitance area capacitance
C s , diff = C d , Area . A + C d , sidewalls .P
Where A = area and p = perimeters
Dr. Ahmed H. Madian-VLSI 18
Routing capacitance
single conductor capacitance
multiple conductor capacitance
Dr. Ahmed H. Madian-VLSI 19
(.Capacitance estimation (cont
Routing capacitance: a) single conductor capacitance
Fringing capacitance Half cylinders
Metal 1
w h
substrate
t
w −
2Π
Ctotal =ε 2 +
h 2h 2h 2h
1+
ln + +2
t t t
Dr. Ahmed H. Madian-VLSI 20
(.Capacitance estimation (cont
Routing capacitance: b) multiple conductor capacitance
C12
Metal 2 Metal 1 Metal 2
Vin Vout
C1
C2
C12
C2
Metal 1
C12
C1 ∆Vout = ∆Vin .
C 2 + C12
substrate
Dr. Ahmed H. Madian-VLSI 21
Multilayer capacitance calculations
Example: given the layout shown in the figure calculate the total
capacitance at source and gate given that:
Cmetal/Area = 0.025µF/µm2 100λ 4λ
CMP
Cpoly/Area = 0.045µF/µm 2
3λ CM 4λ
CGate/A = 0.7 fF/µm 2
CP1 2λ
Cd,a/A = 0.33fF/µm2
Cgate 3λ
Cd,side/L = 2.6fF/µm
λ = 5.1µm 2λ
CP1
4λ 2λ 4λ
Dr. Ahmed H. Madian-VLSI 22
100λ 4λ
CMP
Solution 3λ CM 4λ
CP1 2λ
Source capacitance Cgate 3λ
CS,diff = Cd,A . A + Cd,side walls . P 2λ
CP1
4λ 2λ 4λ
A = 4λ * 3λ = 12 λ2
S D
P = 2*(4λ + 3λ)=14 λ Cs G
CD
So, CS, diff = 0.33* 12 λ2+2.6* 14 λ=63.51fF CG
Dr. Ahmed H. Madian-VLSI 23
(.Solution (cont
100λ 4λ
Gate capacitance CMP
3λ CM 4λ
CG,total = CM + CMP+CP1+CG+CP2
CP1 2λ
CM = 0.025 * 100λ*3 λ=7.5λ2 Cgate 3λ
2λ
CMP = 0.045 * 4λ* 4 λ = 0.72λ2 4λ 2λ 4λ
CP1
CP1 = 0.045 * 2λ* 2λ = 0.18λ2
CP2 = 0.045 * 2λ* 2λ = 0.18λ2 CM CMP CP1 Cgate CP1
CG = 0.7 * 2λ* 3λ = 4.2λ2
Dr. Ahmed H. Madian-VLSI 24
