Unit-4
Delays
Sheet resistance Rs
Sheet resistance Rs
The actual values associated with the layers in a MOS circuit
depend on the thickness of the layer and the resistivity of the
material forming the layer.
For the metal and polysilicon layers, the thickness of the layer
is easily envisaged and the resistivity of the material is known.
For the diffusion layer, the depth of the diffusion regions
contributes toward the effective thickness while the impurity
concentration profile determines the resistivity.
Typical values of sheet resistance Rs
Sheet resistance concept applied to
MOS transistors and inverters
The length to width ratio, denoted Z, is 1:1 in case 1 and it is
4:1 for case 2 thus channel resistance R =ZRs=4x104 ohm.
Area capacitances of layers
Conducting layers are separated from the substrate and each
other by insulating (dielectric) layers, and thus parallel plate
capacitive effects must be present and must be allowed for.
For any layer, knowing the dielectric thickness, we can
calculate area capacitance as follows C=(εo εins A)/D farads.
A normal approach is to give layer area capacitances in pF/µm 2
Typical area capacitance values for
MOS circuits
Standard unit of capacitance Cg
The standard unit Cg is defined as the gate to channel
capacitance of a Mos transistor having W=L=feature size, that
is a standard or feature size square.
Some area capacitance calculations
The calculation of capacitance values may now be undertaken
by establishing the ratio between the area of interest and the
area of standard (feature size square) gate (2λx2 λ for λ-based
rules) and multiplying this ratio by the appropriate relative C
value from table.
The product will give the required capacitance in C g units.
Simple area for capacitance
calculation
Capacitance calculation multilayer
The delay unit
One standard (feature size square) gate area capacitance being
charged through one feature size square of n channel resistance is
called the time constant
The delay unit
• In practice, circuit wiring and parasitic capacitances must
be allowed for so that the figure taken for is often
increased by a factor of two or three so that for 5µm
circuit the delay is 0.2 to 0.3 nsec is a typical design
figure in assessing likely worst case delays.
• It is a common practice to use transit time and time
constant interchangeably.
• Stray capacitances are usually allowed for by doubling
the theoretical values calculated.
Inverter Delays
Td (1 Z p.u / Z p.d )
If we consider a pair of cascaded inverters, then the delay over
the pair will be constant irrespective of the sense of the logic
level transition of the input to the first.
CMOS inverter pair delay
Summary of CMOS rise and fall factors
r/f =n/p
r and f are proportional to 1/VDD
r and f are proportional to CL
r=2.5f for equal n and p transistor geometries
Driving large capacitive loads
The problem of driving comparatively large capacitive loads
arises when signals must be propagated from the chip to off
chip destinations.
Generally, typical off chip capacitances may be several orders
higher than on chip Cg
CL>104 Cg
Capacitances of this order must be driven through low
resistances, otherwise excessively long delays will occur.
Wiring capacitances
The significant sources of capacitance which contribute to the
overall wiring capacitance are
Fringing fields
Interlayer capacitances
Peripheral capacitance
Fan-in and fan-out characteristics.
Two additional factors that influence the operational speed of a
gate are
Fan-in (its number of inputs)
Fan-out (the number of gates and length of metal tracks
connected to its output).
Fan-in and fan-out characteristics.
Fan-in and fan-out characteristics.
Fan-in curve follows a linear behavior, indicating that as the
number of inputs to a gate increase the increase in delay
associated with that gate follows a uniform linear path.
The fan-out curve shows that the delay follows an exponential
path as the number of loads being driven by the output of the
gate is increased. Thus, the gate delay substantially increases
for a high number of fan-out.
