NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 4: STRUCTURAL MODELING

Lecturer: Ho Ngoc Diem

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Agenda
 Chapter 1: Introduction
 Chapter 2: Modules and hierarchical structure
 Chapter 3: Fundamental concepts
 Chapter 4: Structural modeling (Gate & Switch-level modeling)
 Chapter 5: Dataflow modeling (Expression)
 Chapter 6: Behavioral modeling
 Chapter 7: Tasks and Functions
 Chapter 8: State machines
 Chapter 9: Testbench and verification
 Chapter 10: VHDL introduction

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Content
Chapter 4:
A – Overview
 What is structural modeling
 Primitive gates
 Switches
 User-defined primitives
B – Examples
 Combinational Circuit
 Sequential Circuit

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 A – Overview
Primitive Gates, Switches, User-defined primitives

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 Verilog model for hardware design
Verilog design
RTL Design

Gate/Switch level modeling Dataflow modeling Behavioral modeling

- Primitive switch, gate -Continuous assignment - Procedural assignment

- User defined primitive (assign) - initial, always block
- Expression (operators) - Conditional statement…

 There are different ways of modeling a hardware design. Choose an

appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling as a separate modeling
type.

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Structural model
 When Verilog was first developed (1984) most logic simulators
operated on netlists
 Netlist: a list of gates and show how they are connected
together
 A natural representation of a digital logic circuit
 Not the most convenient approach to express the test benches

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Structural model
 Structural
- Explicit structure of the circuit
- How a module is composed as an interconnection of more primitive
modules or components
- E.g. Each logic gate initially instantiated and connected to others
 In Verilog, a structural model consists of:
- List of connected components
- Like schematics, but using text: netlist
- Boring when write, and hard to decode
- Essential without integrated design tools

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Structural model
 Structural Models are built from gate primitives,
switches, and other modules
 Describe the logic circuit using logic gates

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Primitive gates
 12 primitive logic gates predefined in the Verilog HDL

 Advantanges:
 Gates provide a much closer one-to-one mapping
between the actual circuit and the model.
There is no continuous assignment equivalent to the
bidirectional transfer gate.
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 Primitive gates
And/Or/Nand/Nor/Xor/Xnor
One scalar output
Multiple scalar inputs
The first terminal in the list of
gate terminals is an output and
the other terminals are inputs
Terminal list
Verilog automatically instantiates
wire OUT, IN1, IN2; // basic gate instantiations. the appropriate gate.
and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2); // More than two inputs; 3 input nand gate

or or1(OUT, IN1, IN2); nand na1_3inp(OUT, IN1, IN2, IN3);

nor nor1(OUT, IN1, IN2); // gate instantiation without instance name

xor x1(OUT, IN1, IN2); and (OUT, IN1, IN2); // legal gate instantiation

xnor nx1(OUT, IN1, IN2); 10

Primitive gates
Buf/Not Gates
One scalar input
One or more scalar outputs
The last terminal in the port list
is connected to the input
// basic gate instantiations.
buf b1(OUT1, IN);
not n1(OUT1, IN);
// More than two outputs
buf b1_2out(OUT1, OUT2, IN);
// gate instantiation without instance name
not (OUT1, IN); // legal gate instantiation
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 Primitive gates
Bufif/notif
Gates with an additional control signal on buf and not gates

Propagate only if control signal is asserted.

Propagate z if their control signal is de-asserted

bufif1 b1 (out, in, ctrl); bufif0 b0 (out, in, ctrl); notif1 n1 (out, in, ctrl); notif0 n0 (out, in,12ctrl);
Primitive gates
 Array of Instances
wire [7:0] OUT, IN1, IN2;
nand n_gate[7:0](OUT, IN1, IN2);
The instances differ from each other only
by the index of the vector to which they
are connected
// This is equivalent to the following 8 instantiations
nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);
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Primitive gates
 Example: Gate-level multiplexer
// Module 4-to-1 multiplexer.
// Port list is taken exactly from the I/Odiagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;

4-to-1 Multiplexer
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 Primitive gates
 Example: Gate-level multiplexer // Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
// Gate instantiations
// Create s1n and s0n signals.
not (s1n, s1);
not (s0n, s0);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated
or (out, y0, y1, y2, y3);
Logic Diagram for 4-to-1 Multiplexer endmodule
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Switches
 There are two kinds of switch:
* MOS switches :
cmos, nmos, pmos, rcmos, rnmos, rpmos
* Bidirectional pass switches:
tran, rtran, tranif1, rtranif1, tranif0, rtranif0

 Advantages:
- Gates provide a much closer one-to-one mapping between the
actual circuit and the model.
- There is no continuous assignment equivalent to the
bidirectional transfer gate.

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 Switches
MOS switches: nmos, pmos, rnoms, rpmos
Unidirectional channel for data, similar to bufif gate
nmos nmos rnmos
rnmos when “off” when “on” when “on”
R R
CONTROL

DATA

Ex: nmos n1 (out, data, control)

pmos pmos rpmos
when “off” when “on” when “on”
rpmos

CONTROL R R

DATA
Ex: pmos p1 (out, data, control) 17
Switches
MOS Switches: cmos, rcmos
cmos rcmos
n_control when on when on
cmos when “off”
R R
rcmos
in out

p_control
cmos (out, in, n_control, p_control)

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Switches
Bidirectional pass switches
 tranif0, tranif1, rtranif0, rtranif1: block signal when turn off,
pass signal when turn on
Ex: tranif0 (inout1, inout2, control)
 tran, rtran: always pass signal
Ex: tran (inout1, inout2)
 Terminals be scalar nets or bit-select of vector nets

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 Switches
Bidirectional pass switches
tran rtran
R R
inout1 inout2 tran, rtran

control tranif0 rtranif0

tranif0 , rtranif0 R R
inout1 inout2

tranif1, rtranif1 tranif1 rtranif1

control R R
inout1 inout2

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 Switches
 Ref “Verilog digital system design”, Zainalabedin Navabi for
design examples at switch level

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 Strength modeling
 Allows specification of drive strength for primitive gate outputs
and nets.
 Gate output or net signal strength values are specified in a set of
parenthesis that include a strength value for logic 0 and one for
logic 1.
 Drive strengths for logic 0 (strength0):
supply0, strong0, pull0, weak0, highz0
 Drive strengths for logic 1 (strength1):
supply1, strong1, pull1, weak1, highz1
 Charge strengths, representing the strength of a capacitive net:
large, medium, small

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Strength modeling
Drive strength values of primitive gate outputs

Ex:

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Strength modeling
Strength values of nets

Strength0

Strength1

Drive strength Charge strength 24

Strength modeling
Strength level
The stronger signal shall dominate all the
weaker drivers and determine the result.

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Gate & Net delays
• Rise, Fall, and Turn-off Delays
Rise delay

Fall delay

Turn-off delay
1, 0, x z

Note: If a value changes to x, the minimum

of the three delays is considered
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Gate & Net delays
• Rise, Fall, and Turn-off Delays
- If only one delay is specified, this value is used for all transitions.
- If two delays are specified, they refer to the rise and fall delay values.
The turn-off delay is the minimum of the two.
- If all three delays are specified, they refer to rise, fall, and turn-off
delay values.
- If no delays are specified, the default value is zero.

Example:
and #(5) a1(out, i1, i2); //Delay of 5 for all transitions
and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off = 5
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Gate & Net delays
• Min/Typ/Max values
For each type of delay three values, min/typ/max, can be specified.
Min/typ/max values: model devices whose delays vary within a [min max]
range because of the IC fabrication process variations.

min The minimum delay value that the designer expects the gate to have
typ The typical delay value that the designer expects the gate to have
max The maximum delay value that the designer expects the gate to have

Min, typ, or max values can be chosen at Verilog run time.

Method of choosing a min/typ/max value may vary for different
simulators or operating systems

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 Gate & Net delays
• Min/Typ/Max // One delay

values // mindelays, delay= 4

// typdelays, delay= 5
// maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);
// Two delays
// mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);
// Three delays
// mindelays, rise= 2 fall= 3 turn-off = 4
// typdelays, rise= 3 fall= 4 turn-off = 5
// maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2); 29
Gate & Net delays

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 Built-in Gate & Switch

A gate/switch instance declaration consists of:

Ex: nand (pull0, pull1) #(3, 5) n1 [7:0] (w, a, b, c) 31

 User-Defined Primitives
• The set of predefined gate primitives by designing and
specifying new primitive elements
• Instances of these new UDPs can be used in exactly the same
manner as the gate primitives
• Way to define combinational and sequential elements using
a truth table
• Each UDP has exactly one output, which can be in one of
three states: 0, 1, or x.
• Often simulate faster than using expressions, collections of
primitive gates, etc.
• Gives more control over behavior with X inputs
• Most often used for specifying custom gate libraries
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Example: Combinational UDPs
primitive multiplexer (mux, control, dataA, dataB);
output mux;
input control, dataA, dataB;
table
// control dataA dataB mux
010:1;
011:1; output mux;
01x:1; input control, dataA, dataB;
000:0; table
001:0; // control dataA dataB mux
00x:0; 0 1 ? : 1 ; // ? = 0 1 x
101:1; 00?:0;
111:1; 1?1:1;
1x1:1; 1?0:0;
100:0; x00:0;
110:0; x11:1;
1x0:0; endtable
x00:0; endprimitive
x11:1;
endtable
endprimitive 33
User-Defined Primitives
Example: Level-sensitive sequential UDPs
primitive latch (q, clock, data);
output q; reg q;
input clock, data;
table
// clock data q q+
0 1:?:1;
0 0:?:0;
1 ? : ? : - ; // - = no change
endtable
endprimitive

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User-Defined Primitives
Example: Edge-sensitive sequential UDPs
primitive d_edge_ff (q, clock, data);
output q; reg q;
input clock, data;
table
// obtain output on rising edge of clock
// clock data q q+
(01) 0 : ? : 0 ;
(01) 1 : ? : 1 ;
(0?) 1 : 1 : 1 ;
(0?) 0 : 0 : 0 ;
// ignore negative edge of clock
(?0) ? : ? : - ;
// ignore data changes on steady clock
? ? : ? : - ; // - = no change
endtable
endprimitive
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User-Defined Primitives
Initial statement in UDPs and instances
primitive dff1 (q, clk, d); module dff (q, qb, clk, d);
input clk, d; input clk, d;
output q; reg q; output q, qb;
initial q = 1'b1; dff1 g1 (qi, clk, d);
table buf #3 g2 (q, qi);
// clk d q q+ not #5 g3 (qb, qi);
r0:?:0; endmodule
r1:?:1;
f?:?:-;
?*:?:-;
endtable
endprimitive

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 B – Examples
Combinational Circuit & Sequential Circuit

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Combinational Circuit
 Outputs are functions of the current inputs
 Logic without state variables
 No clock involved

 Examples
o multiplexer, demultiplexers
o decoder
o encoder
o adder
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 Example: xor
xor

 The instantiated gates are always active

 xor gate already exists as a built-in (so really no need to define it)
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Example: mux 4-to-1

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Example: 2-to-4 decoder

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Example: Full adder 1-bit
t1
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
t2
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
t3 // Instantiate logic gate primitives
xor (s1, a, b);
Full adder 1-bit and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
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Example: 4-bit ripple carry full adder

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Example: 4-bit ripple carry full adder
// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);
// I/O port declarations
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
// Internal nets
wire c1, c2, c3;
// Instantiate four 1-bit full adders.
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
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 Sequential Circuit
 A feedback path
 The state of the sequential circuits
 The state transition
- synchronous circuits
- asynchronous circuits

Example: Latch, Flip-flop, Register, Counter, State machine, Processor…

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Example: SR latch
 Set-Reset (SR) Latch :

or

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Example: SR latch
 Clocked Set-Reset (SR) Latch :
(1) State can change only when clock is high
(2) Potential non-derterministic behavior if both input Sbar and Rbar
are 0

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Example: SR latch
module clockedSR_latch(Q, Qbar, Sbar, Rbar, clk);
// Port declarations
output Q, Qbar;
input Sbar, Rbar, clkbar;
wire X, Y ;
// Gate declarations
not a(clkbar, clk);
or r1(X, Sbar, clkbar);
or r2(Y, Rbar, clkbar);
nand n1(Q, X, Qbar);
nand n2(Qbar, Y, Q);
endmodule

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D flip-flop

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 Example: D flip-flop
 Negative edge-triggered D flip-flop
sbar
Clock D Qnext
Falling edge 0 0
cbar s Falling edge 1 1
clear
q
Non-falling X Q
clkbar
clk
r qbar

rbar
d

Negative edge-triggered D-flipflop implemented using 3 SR latches

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Example: D flip-flop
Negative edge-triggered D flip-flop
module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar; Gate-level D-flipflop
not (cbar, clear); (1) Negative edge-triggered
not (clkbar, clk); (2) Made from 3 SR-latches (see circuit)

// Input latches Extremely important module – it is the

nand (sbar, rbar, s); fundamental unit of computer memory!
nand (s, sbar, cbar, clkbar);
nand (r, rbar, clkbar, s);
nand (rbar, r, cbar, d);
// Output latch
nand (q, s, qbar);
nand (qbar, q, r, cbar);
endmodule
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Example: T flip-flop
 T (Toggle) flip-flop
module t_ff(q, clk, clear);
output q;
input clk, clear;

// Instantiate the edge triggered DFF

// Complement of output q is fed back.
// Notice qbar not needed. Empty port.
edge_dff ff1(q, ,~q, clk, clear);

endmodule

Negative edge-triggered T-flipflop implemented using a D-flipflop

and an inverter gate – toggles every clock cycle

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 Example: Counter
 4-bit ripple counter
q0 q1 q2 q3

q q q q
clock T_FF T_FF T_FF T_FF
tff0 tff1 tff2 tff3

clear

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Example: 4-bit ripple counter
 4-bit ripple counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
// Instantiate the T flipflops
t_ff tff0(Q[0], clock, clear);
t_ff tff1(Q[1], Q[0], clear);
t_ff tff2(Q[2], Q[1], clear);
t_ff tff3(Q[3], Q[2], clear);
endmodule

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Example: Register
 4-bit register

module register4bits( dataOut, dataIn, enable, clock, clear );

// Inputs and outputs
output [3:0] dataOut;
input [3:0] dataIn;
input enable, clock, clear;
// 4 D-flipflops
edge_dff ff0( dataOut[0], dataIn[0], enable, clock, clear );
edge_dff ff1( dataOut[1], dataIn[1], enable, clock, clear );
edge_dff ff2( dataOut[2], dataIn[2], enable, clock, clear );
edge_dff ff3( dataOut[3], dataIn[3], enable, clock, clear );
endmodule 55
Example: Register
A 4-bit register using D flip-flops

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