Design for Testability
DFT
► Density of ASICs
► Issue which comes into play at the very end
of the design cycle
► Develop a test strategy and address
testability issues concurrently with other
activities in the design
Dr. Behnam Arad 2
EEE/CSC-273
Test synthesis
► Objective: to improve observability and
controllability of the design
The ability to detect manufacturing defects in a
design
Dr. Behnam Arad 3
EEE/CSC-273
Facts
► Functional
vectors on the tester does not
give more than 50-60% fault coverage
► Runautomatic test pattern generation
(ATPG) after fault simulation to target the
remaining faults
Dr. Behnam Arad 4
EEE/CSC-273
Fault models
► Common: stuck_at_fault
1. Stuck @0
2. Stuck @1
Every node/pin has two faults associated with
it
Dr. Behnam Arad 5
EEE/CSC-273
Scan technique
► The most widely used design for testability (DFT)
technique
► Supported by most synthesis tools
► Involves replacing the sequential non_scan cells
by scan cells of the desired scan style.
► Enables sequential scan cells to be connected as a
shift register in the scan mode
► For ATPG, each of scan cells behave as pseudo
primary input as well as pseudo primary output
Dr. Behnam Arad 6
EEE/CSC-273
Basic Issues
1. Scan methodology
2. Scan style
3. Scan insertion
4. ASIC vender issues
Dr. Behnam Arad 7
EEE/CSC-273
Scan methodology
► Full scan
Replace all the sequential cells in the net-list
with scan cells
► Partial scan
Only some cells are replaced
The choice of which cells to be replaced is made
based on area and timing constraints
User can specify if fault coverage, timing, or
area is of highest priority
Dr. Behnam Arad 8
EEE/CSC-273
Scan styles
► Type of scan cells used
1. Multiplexed filpflop
2. Level sensitive scan design
3. Clocked scan cell
4. AUX LSSD cell
Dr. Behnam Arad 9
EEE/CSC-273
Scan Insertion
► Scan cell operations:
Normal
► Same as that of sequential non-scan cell
Scan
► Scan cells are linked in the form of a shift register
scanin
D Q
Normal input
__
Q
Scan select
clock
Dr. Behnam Arad 10
EEE/CSC-273
Scan insertion (continue…)
► Allscan cells are controllable and observable
► Shifting of data into the scan chain is done serially
► N-cycle for an N-cell design
► Overhead:
Use of extra scan ports
Increase in area due to scan flops
Grater timing delays due to insertion of scan cells
Can be reduced by sharing scan ports with functional
ports
► After insertion, use ATPG to generate test patterns
Dr. Behnam Arad 11
EEE/CSC-273
ASIC vendor issues
► Test strategy highly dependent on the
requirements of the ASIC vendor
► Issues:
1. Style supported?
2. How many clocks supported by the test?
3. Limit on the # of waveforms
4. Limit on the scan chain
5. Limit on the length of scan chain
6. Test vector format
7. Parallel or serial vectors
Dr. Behnam Arad 12
EEE/CSC-273
Test synthesis flow using SC
1. Read design
2. Set current design to the top level and specify test
methodology and style
3. Synthesize after timing/area requirement
4. Set timing related test attributes
5. Analyze the testability of the design before scan insertion
6. Save design in .db
7. Scan insertion
8. Analyzer testability after insertion
9. Execute ATPG on a sample default list
10. JTAG synthesis pattern generation
Dr. Behnam Arad 13
EEE/CSC-273
Dr. Behnam Arad 14
EEE/CSC-273
