ARM7 Processor Architecture
ARM7 - Introduction
Advanced (Acron) RISC Machines Processor Cores
ARM is a British semiconductor and software design company based
in Cambridge, England,
Originally known as Acorn RISC machine
Now its Advanced RISC Machines is a family of reduced instruction set
The primary business ARM is to design of 32 bit and 64 bit ARM High Performance
RISC architecture processors (CPUs).
ARM is the industry's leading provider of 32/64-bit embedded RISC microprocessor
solutions
Arm Ltd. develops the architecture and licenses it to other companies,
who wants design their own Microcontrollers or systems-on-chips (SoC)
and systems-on-modules (SoM)
Ex; ATMEL, Cirrus Logic, Freescale Semiconductor, NXP(Founded By Philips), OKI,
Samsung, Sharp, STMicroelectronics, Texas Instruments
Due to their low costs, minimal power consumption, and lower heat
generation
ARM processors are desirable for light, portable, battery-powered devices
Including smart phones, laptops and tablet computers, as well as
other embedded systems.
ARM processors are also used for desktops and servers, including the
world's fastest supercomputer.
Features of ARM7
32-bit Advanced RISC(Adv.) Processor 32-bit ALU architecture (ARM v4T)
Operates upto 60 to 100Mhz
32-bit ARM instruction set for maximum performance and flexibility
16-bit Thumb instruction set for increased code density
Unified bus interface, 32-bit data bus carries both instructions and data
Three-stage pipeline
1. Fetch 2. Decode 3. Execute
JTAG interface debug unit
32-Bit Memory Addressing Range
USER mode, FIQ mode, IRQ mode, SVC mode
UNDEFINED mode, ABORT mode, System Mode
ARM7 Processor Architecture
32 Bit ALU
32 Bit PC- Program Counter
32 bit MAC Unit
32 Bit Barrel Shifter
32 Bit Address Bus
32 Bit Data Bus
Signed Extension
Instruction Decoder
ARM Processor Architecture
ARM Processor Architecture
The Current Program Status Registers-(CPSR)
ARM Processor Architecture
Inline barrel shifter
The ARM arithmetic logic unit has a 32-bit barrel
shifter that is capable of shift and rotate
operations.
The second operand of the instruction specifies
the no. of bits of shift or rotation
Ex: LSR R5,4
ARM Processor Architecture
Ex: LSL R5,4
AMBA Bus Protocol
(Advanced Microcontroller Bus Architecture)
Adv.High
Performance Bus
(AHB)
Adv. Peripheral
Bus (APB)
If AHB=60 Mhz
Then APB=(1/4)AHB
=15MHz
AMBA Bus Architecture
The Advanced Micro controller Bus
Architecture (AMBA) bus protocols
is a set of interconnect specifications
from ARM that standardizes on chip
communication mechanisms between
various functional blocks like USB,
UART,I2Cetc for building high
performance SOC designs
Thumb Instruction Set
The ARM7TDMI processor has two instruction sets:
the 32-bit ARM instruction set
the 16-bit Thumb instruction set.
Thumb Instruction Set
The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions.
Thumb instructions are 16 bits long,
They have a corresponding 32-bit ARM instruction
Thumb instructions operate with the standard ARM register configuration
Interoperability between ARM and Thumb states.
On execution, 16-bit Thumb instructions are transparently decompressed to full
32-bit ARM instructions in real time, without performance loss.
Advantages of Thumb Mode
Thumb code is typically 65% of the size of ARM code,
Provides 160% of the performance of ARM code when running from a 16-bit
memory system.
The ARM7TDMI core ideally suited to embedded applications with restricted
memory bandwidth.
Thumb has all the advantages of a 32-bit core:
32-bit address space
32-bit registers
32-bit shifter, and Arithmetic Logic Unit (ALU)
32-bit memory transfer.
ARM Thumb
(CPSR T=0) (CPSR T=1)
Instruction size 32 bit 16 bit
Core Instructions 58 30
Conditional Only branch
Most
Execution instructions
Program Status R/W in privileged
No direct access
Register mode
15 General Purpose
registers 8 GP Registers
Register Usage (R0 –R15) (R0-R7)
+CPSR + SP+LR PC
ARM 7 – Operating Modes 1. User : unprivileged mode under which
most tasks run
The ARM has seven basic operating modes 2. System : privileged mode using the
same registers as user mode
3. Undef : used to handle undefined
instructions
4. Abort : used to handle memory access
violations
5. IRQ : entered when a low priority
(normal) interrupt is raised
6. FIQ : entered when a high priority
(fast) interrupt is raised
7. Supervisor : entered on reset and
when a Software Interrupt instruction
is executed
ARM 7 Register Set
37 registers
31 general 32 bit registers
6 status registers
16 general registers and one
or two status registers are
visible at any time
The visible registers depend
on the processor mode
IRQ Mode
Mode Switch LR,SP,SPSR
Go to ISR
User Mode PC Vector
R0-R15 Address
PC
Main Pgm To LR
Instruction 1 And CPSR to
Instruction 2 SPSR
INT x
Instruction 3
Instruction 4
Instruction 5
Instruction 6
ISR
Get original PC
Instruction 1
Restore CPSR from from LR
Instruction 2
SPSR SPSR to CPSR
Instruction 3
Restore PC from LR Clr int flag
ARM Nomenclature
LPC2129 Microcontroller
Internal Architecture
(ARM7 Based Controller)
LPC2129 Microcontroller Internal
Architecture
LQFP 64 A Low-profile Quad Flat
Package
No of pins - 64
ARM7TDMI @60 MHz maximum CPU
clock
CPU Clock can be programmable using
on-chip PLL
On chip SRAM - 16Kbytes
On chip flash –256 Kb
10 bit ADC channels – 4
Two 32-bit timers/external
LPC2129 Microcontroller Internal
Architecture
PWM unit (6 outputs),
Real Time Clock (RTC),
Watchdog Timer
Vectored Interrupt Controller with
configurable priorities.
Two UARTs
I2C-bus
Two SPI interfaces.
TWO interconnected CAN
interfaces
Memory Map of
LPC2129 Microcontroller
General Purpose Input & Output (GPIO)
LPC2129
Two 32 bit general purpose IO ports
PORT 0 (32 pins)
P0.0 to P0.31
PORT 1 (32 pins)
16 pins available for GPIO
P1.16 to P1.31
Pins controlled using GPIO registers
GPIO register set
IODIRx
Def 0 0 input port
1 output port
IOSET: 1 set the port pin
IOCLR: 1 clear the port pin
IOPIN : to check the status of the port pin
toggle the port pin P0.1
P0.1 ip or op
IODIR0
P0.1=1
DELAY
P0.1=0
DELAY
Set a bit (OR with 1in the bit pos)
Clear a bit (AND with 0 in the bit pos)
~(set flag)
Toggle a bit (XOR with set flag)
Buzzer
P0.11
While(1)
{
lLPC2129
Buzzer(P0.11)=1
Delay
Bezzer (P0.11)=0
delay
}
IOPIN
Buzzer
P0.11
Switch
P1.25 lLPC2129
While(1)
If switch (P1.25) ==1
Buzzer(P0.11)=1
Delay
Bezzer (P0.11)==0
LED
LED
LED
LED
LED
Switch
P1.25 lLPC2129
LED
LED
While(1)
If switch (P1.25) ==1
LED= turn on
Delay
LED= turn off
