ARM7 Peripheral
Programming
Shashidhara H S
Agenda
• Features of LPC214x Series
• Processor Organisation LPC214x
• Memory Map
• System Control Block and Functions
• Peripherals and Programming
• GPIO
• Timers
• PWM
• UART
LPC241x
• 16/32 bit ARM7TDMI-S core
• 8 - 40 kb on chip static RAM & 32 - 512 kb on chip flash
memory
• One or two 10-bit ADCs with 6 to 14 analog input pins
• 10 bit DAC
• 2 32-bit timer/counters
• PWM unit with 6 output pins and Watch Dog Timer
LPC214x features
• RTC with independent power and 32 kHz clock input
• Serial Communication - 2 UARTs, 2 SPI and SSP and 2 I2C
• External crystal can have frequencies from 1 MHz to 25
MHz
• Low power modes for power saving
• Power on Reset and Brown out Reset Circuits
• 2 PLLs
Processor Organisation
Processor Organisation
Memory Map
Memory Map
Memory Map
• Core has 32 address lines, hence 4GB addressing capability
• Memory mapped IO and hence…..?
• Addressing peripheral means addressing registers
• Each peripheral may have many registers and thus has many
addresses (all within 4GB block)
• Flash memory - LPC2141/2/4/6/8 : 32/64/128/256/512Kb & starts
from 0x00000000
• On-chip static RAM - LPC2141/2/4/6/8 : 8/16/32 kb & starts from
0x40000000
System Control Block
Functions not peripheral specific but common to whole chip
• Crystal Oscillator and PLL
• System clock(CCLK) - can be obtained by external oscillator/on-
board oscillator/PLL
• One PLL is used to generate CCLK. Accepts an input frq in the range
10-25MHz and multiplies to get 10-60MHz required by core
• VPB divider
• Peripherals do not work with same high frq as core
• CCLK is usually /2 or /4 (default being 1/4th)
SCB…VPB
• VPB divider decides the relationship between CCLK and PCLK
• It also reduces power consumption
• PLL has to remain active during Idle mode to continuously supply
inout to VPB divider
Low power modes
• IDLE mode
• Instruction execution is suspended
• Peripherals continue to operate to interrupt processor
• Eliminates power used by processor, memory system, related controllers and
internal buses
• Power-down mode
• Oscillator shuts down, chip receives no internal clocks
• Processor states, registers, SRAM values and chip pin signals are preserved
• Processor operation resumed upon Reset and power consump. is nearly 0
RESET
2 sources - RESET/ WDT
• Use glitch filter and Wake-up timer
Internal Bus
• Fastest - ARM Local bus: connects core to memory as
well as high-speed GPIO
• System functions are on AHB and peripherals use low
speed VPB
Bus Structure
Peripherals
• GPIO
• LPC214x has two 32 bit ports viz. Port 0 and Port 1
• Each pin can be configured to work as input/output,
But….
• P0.31 is output only, P0.24, P0.26 and P0.27 not available.
• P1.0 - P1.15: Not available & P1.16 - P1.25 reserved.
• Each pin can have more than one function.
Pin Select Block
• Has configuration registers which supply select input to
multiplexers connecting peripherals to GPIO pin
• Called Pin Select Registers - PINSEL0, PINSEL1 and PINSEL2
• Each one handles 16 pins
• Example:
Example 2
• Write pin select register configuration to select P0.0 as GPIO,
P0.1 as RxD, P0.2 as Timer) capture input and P0.14 as
SDA(I2C)
Using Port pins as GPIO
• Each pin has 4 functions, but default function is GPIO.
• If used as GPIO, it has attributes:
• input/output
• If input, reads values from outside chip
• If output, it may be set or cleared
• Need some registers to configure these attributes
Registers associated with GPIO
• IODIR - decides mode:input/output (0/1)
• IOSET - in output mode, used to set pin
• IOCLR - in output mode, used to clear pin
• IOPIN - in input mode reads the status of pin
Example
Solution
Program
• Write a program to toggle the lowest pin of port 0 with
some delay.
What do you think it does?
Answer
Timers
• LPC214x has 2 timer/counter units - Timer 0 and Timer 1
• Timer vs Counters
• We discuss only from delay creation purpose
• Has 8 registers viz. TCR, TC, PR, MCR and MR0-MR3
Operation of Timer
Timer registers
• TC - incremented by 1 for every PCLK or prescaled PCLK
• TCR - Enables/Disables and reset counter
• MR0-3 - one of them can be used to declare count. TC is incremented till it matches with MR
• MCR - Decides action upon match (STOP/RESET/Interrupt)
Program to generate square wave
Frequency Calculation
• Assume reference Clock(CCLK) of 50MHz
• By default PCLK is 1/4th of CCLK = 12.5MHz
• So, T(PCLK) = 0.08micro seconds
• Count loaded in MR = 34FF = 13567.
• TC register starts from 0 and counts unto 13567 = 13568
• Delay produced = 13568 * .08 = 1.085mS
• So, 1.085 * 2 = 2.17 mS is the time period of square wave and
hence, F = 1/T = .460 KHz/460Hz
Vectored Interrupt Controller
• Observe the previous program: while (TOTC!=TOMR1);
• This line keeps the processor in loop.
• Even though, processor has 2 timers, we cannot use
them simultaneously. (Polling, wastes memo cycles)
• Solution is to make the timer work in interrupt mode
• Peripherals can work simultaneously using this technique
• LPC214x uses VIC to process multiple interrupt requests
Vectored Interrupt Controller
• VIC can take 32 interrupt request and categorise them as
• FIQ - highest priority
• Vectored IRQ - second priority
• Non-vectored IRQ - last priority
• ISR is started by reading a register in VIC
• If Vectored IRQ - VIC provides address else address of
default ISR
VIC Registers
• VICIntEnable Register - used to enable a specific
peripheral/s out of 32 possibilities
• Timer0 has bit 4 allocated and has to be set to be
enabled ie. 0x00000010. (see other peripherals also…)
VIC Registers
• VIC Vector Control Register - for timer0, it is designated as
VICVectCntl4
• Only LS 6 bits are used and for Timer) bit combination is
100100
• So, VICVectCntl4 = 0x00000024
• Vector Address Register - should contain address of ISR
• Timer0 Interrupt Register - when match occurs in interrupt
mode, corresponding bit is set. Clear it to further enable
Interrupts
Example Program
Pulse Width Modulator
• Fundamentally a timer made to generate pulses of
different time ie. to vary duty cycle of square wave.
• Has 6 outputs. (P0.0, P0.7, P0.1, P0.8, P0.21 and P0.9)
• So, PINSEL0 = 0x000A0000 and PINSEL1 = 0x00000400
• There are 7 Match registers - PWMMR0 to PWMMR6
• PWMMR0 is used to store T (Time period of waveform)
• PWMMR1 - PWMMR6 store “on” time for each out put
PWM…
• Two modes of operation - single edge and double edge controlled
• Single edge controlled - only falling edge of pulse is controlled
• Double edge controlled - rising edge and falling edge can be
separately controlled
How to calculate Duty Cycle?
• Let PWMMR0 = 0x4556, PWMMR1 = 0x2341 and PWMMR2 = 0x0E40. Find the duty
cycle of PWM1 and PWM2.
Solution:
Assume CCLK = 50 MHz, So, PCLK = 12.5MHz and 0.08 micro secs
MR0 determines T -> so, 17751 * 0.08 = 1.42mS
MR1 = .722 mS and MR2 = .292 mS
Duty cycle:
PWM1 = .722/1.42 = 50.8%
PWM2 = .292/1.42 = 20.56%
Registers of PWM
• PWM Control Register - used to enable and select the
mode (Single edge(0)/Double edge(1)) of PWM channels.
Only bits of 2 to 6 are used. (bit 2 - PWM2 to bit 6 -
PWM6)
• PWM Timer Control Register - controls the opn of PWM
(1001)
• MR0 should be set before PWM being enabled
Registers of PWM
• PWM Latch Enable Register - 8 bit register.
• Sometimes we may want to update MRs on the go. To
enable the procession of dynamic change, bit 0 - 6 are
made 1 (0x7F)
• PWM Match Registers - contain on time and
continuously checked against PWMTC.
• Once matched, actions are taken as per PWMMCR
settings.
Program to generate PWM waves
UART
• Mandatory Unit in every MCU used for serial communication
• Two in number - UART0 and UART1
• Inside MCU, data communication is done in parallel mode.
• For serial operation, serial to parallel and parallel to serial
conversion is required.
• For transmission, buffered data is converted to serial form, framed
with start, stop and parity bit ands sent on TxD
• For reception, received data is deformed, parallelised and moved as
byte into CPU
Working of UART
BAUD Rate Generator
• Transmission and reception rates are referred to as TCLK
and RCLK
• These are generated by the BRG and can be set using a
formula:
• DLL and DLM hold divisor value (DLM - Upper 8 bits, DLL
- lower 8 bits, so DLL has 0x01 as starting value)
Registers of UART
• Transmit Holding Register (U0THR and U1THR) - contains character to be
transmitted one byte at a time
• FIFO Control Register (U0FCR and U1FCR)
• Line Control Register (U0LCR and U1LCR) - used to set format of data to
be transmitted
• Bit 0,1:11(8 bit data), bit 2: 0 for stop bit, bit 7:Divisor Latch Access Bit
(DLAB) should be set to enable latch. (0x83)
• Line Status Register(U0LSR and U1LSR) - status of TxD and RxD blocks
