Analysis and Design of Analog Integrated Circuits
Lecture 3
Large Signal Modeling of CMOS Transistors
Michael H. Perrott
January 29, 2012
Copyright © 2012 by Michael H. Perrott
All rights reserved.
M.H. Perrott
Introducing CMOS Devices
NMOS PMOS
(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)
p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk)
p-
(Drain) (Source)
D S
(Gate) G B (Bulk) (Gate) G B (Bulk)
S D
(Source) (Drain)
CMOS: Complementary Metal Oxide Semiconductor
- Current flow through channel between Drain and Source
is controlled by Gate
- Complementary: both PMOS and NMOS are available
M.H. Perrott 2
Simplified MOS Symbol for Typical Bulk Connections
NMOS PMOS
(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)
Gnd Vdd
p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk)
p-
(Drain) (Source)
D S
(Gate) G (Gate) G
S D
(Source) (Drain)
Bulk silicon below the channel under the gate also has an
impact on the channel current
- We often tie the Bulk to Gnd/Vdd for NMOS/PMOS devices
In such case, the symbol does not include the bulk terminal 3
M.H. Perrott
Symbol Notation Often Includes Size
W
M1
W
L
L
The designer is generally free to choose the width (W)
and length (L) of the device
- Wider width is often chosen to achieve higher channel
current for a given gate bias voltage
- Longer length is often avoided since it lowers the channel
current and decreases the operating speed of the device
The minimum length for the gate is often used to define the
process name (i.e., 0.18u CMOS or 0.13u CMOS)
Longer length is used in cases where better matching or
high resistance is desired
M.H. Perrott 4
Channel Current as a Function of Gate Voltage
Id Vds > ΔV
d
Id
Note that we designate
g
M1 V as the overdrive voltage
Vgs s Id_op and that V = Vdsat
in strong inversion
Vgs
NMOS VTH Vgs_op
ΔV
If Vgs < VTH, then current density Id/W is small
- The device is in the subthreshold operating region
For Vgs > VTH, then Id/W is much larger
- The device is in strong inversion
- If V > V, then I is relatively independent of V
ds d ds
The device is in the saturation operating region
- If V < V, then I is strongly dependent on V
ds d ds
The device is in the triode operating region
M.H. Perrott 5
PMOS Devices are Complementary to NMOS Devices
Id Vsd > ΔV
Vsg s
M2
g
d Id Id_op
Vsg
PMOS -VTH Vsg_op
ΔV
Same observations and definitions apply to PMOS
- However, voltage and current signs are flipped
Note that Vsg = -Vgs, Vsd = -Vds
Note that Id as defined above for PMOS is in the
opposite direction as for NMOS
Note that VTH becomes negative
M.H. Perrott 6
Examine MOS Behavior As Vds is Increased
Triode ID
VGS
G Overall I-V Characteristic
VDS=0
S D
Cchannel = Cox(VGS-VTH)
ID
Pinch-off ID Saturation
Pinch-off
VGS
G
VD=ΔV
S D Triode
VDS
Saturation ΔV
ID
VGS
G
VD>ΔV
S D
How does VGS influence Id in the above curve ? 7
M.H. Perrott
MOS Behavior Is A Function of Vgs and Vds
Overall I-V Characteristic
ID
Saturation
Pinch-off
See page 15-23 of Razavi…
Triode
ΔV Increasing Vgs
VDS
M.H. Perrott 8
MOS Current Equations in Triode and Saturation Regions
Triode ID
ID = μnCox W (VGS - VTH - VDS/2)VDS
VGS L
G
VDS=0 for VDS << VGS - VTH
S D
ID μnCox W (VGS - VTH)VDS
L
Cchannel = Cox(VGS-VTH)
Pinch-off ID
VGS ΔV = VGS-VTH
G
VD=ΔV 2IDL
S D ΔV =
μnCoxW
Saturation ID
VGS 1 μ C W 2
G ID = n ox (VGS-VTH) (1+λVDS)
VD>ΔV 2 L
S D (where λ corresponds to
channel length modulation)
M.H. Perrott 9
The Issue of Velocity Saturation
When in saturation, the MOS current is calculated as
Which is really
- Here V dsat,l is the saturation voltage at a given length
It may be shown that
- If V gs-VTH
approaches LEsat in value, then
We say that the device is in velocity saturation
The current becomes linearly related to Vgs-VTH
M.H. Perrott 10
Example: Current Versus Voltage for 0.18 Device
Id
Vgs
M1 W 1.8μ
= Id versus Vgs
L 0.18μ 1.4
1.2
Id (milliAmps) 1
0.8
0.6
0.4
0.2
0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V (Volts)
gs
M.H. Perrott 11
The Tricky Issue of Modeling MOS Devices
The device characteristics of modern CMOS devices
lead to complicated analytical models
- This creates challenges for achieving accurate hand
calculations with reasonable effort
Hand calculations are essential in achieving deeper
understanding and intuition of circuit and device
behavior
- Simple hand calculations lack accuracy
- Detailed hand calculations often do not yield the desired
insight and understanding to make them worthwhile
A typical compromise
- Assume simple models for hand calculations
- Use SPICE to get a more accurate picture of the actual
circuit and device characteristics and performance
M.H. Perrott 12
What is the Key Role of Large Signal Calculations?
In analog circuits, we are often focused on amplifiers in
which the small signal behavior is of high importance
- Large signal calculations lead to the operating point
information of the circuit which is used to determine the
small signal model of the device
Example amplifier circuit:
Small Signal Analysis Steps
ID RD
1) Solve for bias current Id
RG 2) Calculate small signal
vout parameters (such as gm, ro)
vin
3) Solve for small signal response
Vbias RS
using transistor hybrid-π small
signal model
M.H. Perrott 13
A Key Small Signal Parameter: Transconductance
Id Vds > ΔV
d
Id
g
M1
ΔId
Vgs s Id_op gm =
ΔVgs
Vgs_op
Vgs
NMOS VTH Vgs_op
ΔV
Transconductance from input gate voltage, Vgs, to
channel current, Id, is very important for amplifier circuits
- Assuming device is in saturation:
M.H. Perrott 14
A Key Small-Signal Nonideality: Output Resistance
ID
Saturation
Pinch-off
ΔId
gds =
ΔVds
Triode Vds_op
Vds
ΔV Vds_op
Ideally, Id would not change with Vds when the device is
in saturation
- Practical CMOS transistors exhibit I dependence on V
d ds
due to channel length modulation
- The parameter is often used to characterize this effect
M.H. Perrott 15
Another Non-Ideality: Back-Gate Effect
NMOS PMOS
(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)
Gnd Vdd
p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk) p-
The threshold voltage of the device, VTH, is dependent on
the potential between the source and bulk
- This implies that changes in the source node voltage, V , s
lead to changes in the channel current, Id
We model this effect as backgate transconductance, gmb
- MIC503 will provide details (also see pages 34-36 of Razavi)
M.H. Perrott 16
MOS DC Small Signal Model
Assuming transistor is in saturation:
- Note that designers often determine g mb impact from SPICE
RD RD
ID
RG
RG
vgs gmvgs -gmbvs ro
RS
gm = μnCox(W/L)(VGS - VTH)(1 + λVDS)
vs RS
= 2μnCox(W/L)ID (assuming λVDS << 1)
γ gm 2qεsNA
gmb = where γ =
See Chapter 2 of Razavi 2 2|ΦF| + VSB Cox
for more discussion of In practice: gmb = gm/5 to gm/3
these formulas
1
ro =
λID 17
M.H. Perrott
MOS DC Small Signal Model
Assuming transistor is in triode region:
- The channel of the device can be approximated as a
resistor whose value depends on the DC operating point
of Vgs
RD RD
ID
RG
RG
vgs rds
RS
1
vs RS rds =
μnCox(W/L)(VGS - VTH)
M.H. Perrott 18
Example: Determine V and Operating Region (NMOS)
Assume VTHn = 0.5V
1V 0.2V 1V
0.2V 1V 0.7V
ΔV = ΔV = ΔV =
Region = Region = Region =
1V 0.2V 1V
0.2V 1V 0.7V
0.4V 0.4V 0.4V
ΔV = ΔV = ΔV =
Region = Region = Region =
M.H. Perrott 19
Example: Determine V and Operating Region (PMOS)
Assume VTHp = -0.5V
1.3V 1.3V 1.3V
0.5V 0.9V 0.5V
0.7V 0.7V 1.1V
ΔV = ΔV = ΔV =
Region = Region = Region =
1.2V 0.8V 1.3V
0.5V 0.9V
1.3V 0.7V 1.1V
ΔV = ΔV = ΔV =
Region = Region = Region =
M.H. Perrott 20
Example: Determine Operating Region of M1 and M2
Assume VTHn = 0.5V, VTHp = -0.5V, nCox = 50A/V2,
pCox = 20A/V2, = 0, and M1 and M2 have the same
value of W and L 1.3V
M2
vout
Vbias
M1
Determine operating region for M1 and M2 assuming:
-V bias = 1.2
-V bias = 0.2
-V bias = 0.65
M.H. Perrott 21
Example: Determine V and Operating Region
Assume Vbiasp = 0.7V, VTHn = 0.5V, VTHp = -0.5V,
nCox = 50A/V2, pCox = 20A/V2, = 0
1.3V
3.25u
0.13u
Vbiasp M2
vout
1.3u
0.13u
Vbiasn M1
Determine Vbiasn such that Vout = 0.5V
- Note that with = 0, a variety of V solutions will exist for
out
the same Vbiasn – I’m just trying to keep calculations simple
Determine the resulting operating region of M1 and M2
M.H. Perrott 22
