} weds vt uve uueese SC eC CK CHO OK I I ve vivid duua MUTHOOT INSTITUTE OF TECHNOLOGY AND SCIENCE, VARIKOLI, PUTHENCRUZ, ERNAKULAM DEPARTMENT OF ECE LAB MANUAL EC 232 ANALOG INTEGRATED CIRCUITS LAB STAFF COPYGENERAL INSTRUCTIONS SAFETY; 1. When students are doing experiment they have to be very care full 2. Students should have the prior knowledge about the lab they are doing, 3. Ifany kind of wrong thing happened while doing the experiment, Students have to immediately switch off power supply on the work table. 4. Wearing loose garments inside the lab is strictly prohibited. ATTENDANCE: 1. Students have to come to the laboratory with proper dress code and ID Cards 2 Students have to bring Observation note book , Record note book and calculators ete.. to the Laboratory, 3. Students have to sign in the log register after entering into the lab and before leaving the laboratory, 4. Students have to show their observations with results after completion of their experiments and they have to get is signed. DOING EXPERIMENTS: 1. Start the experiment as per the procedure. Enter all readings in the tabulation Do not make any interconnections on the bread board when power is switched ON 4. Ifany of the things are wrong, then switch off and modify the connections. Inform to the staff and then START CALCULATION: Calculate all required quantities and enter in the tabulation, Units are very, very important, Draw the necessary graphs. Write the result. Show it to the staff for g etting ature.s € . ~ ~ “ Se ddd « e¢ / eee ved sb d dd ddd ddd dd EC 232 ANALOG INTEGRATED CIRCUITS LAB SYLLABUS Course objectives: To acquire skills in designing and testing analog integrated circuits To expose the students to a variety of practical circuits using various analog ICs Course Outcome (Statements) CO.1 Will be able to Design and demonstrate functioning of various analog circuits. CO.2 Will get the knowledge of various feedback configurations in opamp and its application, CO.3 Will be able to design circuits using operational amplifiers for waveform generators and active filters. CO.4 Will be able to design DC regulated power supply for various applications. CO.S Will be able to design and implement data converters. CO-PO/PSO Mapping Course 7 Outcome (Statements) | PO1 | PO2 | PO3 | PO4 | POY | POLO | PO12 | PSOI PSO2 PSO3 Ol 2{2 {2 73 2 2 2 2 2 | co2 2/3 {2 azalpe2 2 2 2 | co3 Pepe pore e 2 2 3 3 cos 2 [3 2 5) 2) 2 2 2 “| | 608 373 2 2 3 2 | 2 2 | ob. av Abts Av cow Hap ECE “p e to be done) List of Experiments: (Minimum 12 experiments ar '-Familiarization of Operational amplifiers - Inverting and Non inverting amplifiers, frequency response, Adder, Integrator, comparators, 2.Measurement of Op-Amp parameters. 3. Difference Amplifier and Instrumentation amplifier. 4-Schmitt trigger circuit using Op —Amps. 5-Astable and Monostable multivibrator using Op -Amps. 6. Timer IC NESSS 7. Triangular and Square wave generators using Op- Amps. 8. Wien bridge oscillator using Op-Amp - without & with amplitude stabilization, 9.RC Phase shift Oscillator. 10.Precision rectifiers using Op-Amp. |1-Active second order filters using Op-Amp (LPF, HPF, BPF and BSF). 12.Notch filters to eliminate the SOHz power line frequency, 13.1C voltage regulators, 14-A/D converters- counter ramp and flash type, 15.D/A Converters- ladder circuit. 16.Study of PLL IC: free running frequency lock range capture rangeCON SINo. Name of the Experiment Page No. 1 Introduction 2 Familiarization of Operational Amplifiers 3 Measurements of Op Amp parameters 4 Schmitt Trigger 5 Difference Amplifier 6 Astable Multivibrator Using Op Amp 7 Monostable Multivibrator Using Op Amp 8 ‘Square Wave and Triangular Wave Generator 9 RC Phase Shif Oscillator Using Op Amp 10 Wein Bridge Oscillator Using Op Amp uw Precision Rectifier Using Op Amp R Astable Multivibrator Using 555 13 Voltage Regulator Using IC 723 14 | Active second order filters using Op-Amp (LPF, HPF. BPF and BSF). 15 Notch filters to eliminate the SOHz power line frequency 7 16 IC voltage regulators. vf Study OF PLL IC 565 18 A/D Converters-Counter and Flash Type 19 D/A Converters-Ladder TypeLINTRODUCTION Operational Amp! ifier(op-amp) tional amplifier which The best known, and most common, linear IC is the opera consists of resistors, ional analog diodes, and transistors in a convention: operational . i i amplifier is a direct-coupled, high gain amplifier con: differential amplifi i operations it can be used to perform a variety of mathematical op ‘operational’ amplifier is Such as addition substraction, multiplication ete. Hence the name op. abbreviated as op-amp, Block Diagram Representation N inverting |= -——__ -— ~“ Input Intermediate |_| level Shifting Output Ourpur Invert tage Stage stage ‘Stage | | sae inpuc | Daal inpur Duat-inoput Eminer = Balanced Unbalanced Follower Using one Date Dine a Push-pull Differential Ditferantat Current =e Amplifier Amolifer Source Plifier and also establishes the input ‘sistance of the op-amp.The intermediate stage 's usually another differential amplifier.which 's used the D.C voltage at the output of the inetrmediate stage is well above the ground potential Therefore, generally, the level shifting stage is used after the intermediate stage to shift the D. level at the output of the intermediate Stage downward to ze, TO Volts with respect to ground.The final stage usually a push Pull complementory amplifier output age swing ‘age. The output stage increases the output vol and raises the current oe capability of the op-amp.Schematic Symbol of an op-amp: Nee Equivalent Circuit: we Pin diagram IC pA 741Parameters of Op-amp: Input offset voltage Itis the voltage that must be applied between the two input terminals of op-amp to null the output, Input offset current ‘The difference between the bias currents at the input terminals of the op-amp is called as input offset current. Common Mode Rejection Ratio(CMRR) The relative sensitivity of an op mp to a difference signal as compared to a common ~mode signal is called the common ~mode rejection ratio. It is expressed in decibels. CMRR= AWA: Slew Rate ‘The slew rate is defined as the maximum rate of change of output voltage caused by a step input voltage.An ideal slew rate is infinite which means that op-amp’s output voltage should change instantaneously in response to input step voltage. Applications of ope: tional Amplifier: * Summing Amplifier * Integrating and Differentiating Amplifier * Filtering etc. The ideal op-amp Th leal behaviour of an op-amp implies that 1. The output resistance is zero 2. The input resistance is infinity. 3. Op-amp has a zero voltage offsetie., for Vi = V2 = 0, output voltage Vo = 0. 4. Common Mode Rejection Ratio (CMRR) is infinity, 5. Bandwidth is infinite i.e., Asis real and constant, 6. Slew rate is infinite. Practical op-amp 1. Supply voltage a. HA T41A, WA 741, WA 741E b. pA 741C 2. Differential input voltagesei vwid EOE Nee SO 3. Input offset voltage 4. Input Bias current 5. Input resistance 6. CMMR 7. Output resistance 8. Bandwidth 9. Slew ratexp. No.1 tion of Operational amplifiers (Inverting and Non inverting amplifiers: frequency response, Adder, Integrator. comparators) 1. a, Inverting Amplifier AIM: To design an Inverting Amplifier for the given specifications us APPARATUS REQUIRED: Op-Amp IC 741 ‘S.No ‘Name of the Apparatus Range Quantity 1. | Function Generator 3 MHz, 1 2. | CRO 30 MHz, 1 3. [Dual RPS 030V T 4. [Op-Amp IC 741 1 3. | Bread Board T 6. _| Resistors ‘As required 7. | Connecting wires and probes ‘As required THEORY: The input signal Vs is applied to the inverting input terminal through Ri and the none inverting input terminal of the op-amp is grounded, The output voltage Vo is fed back to the inverting input terminal through the Rr - Ri network, where Rr is the feedback resistor. The input terminals of the opamp draws no current because of the large differential input impedance. The potential difference across the input termin, opamp is zero becuse of the large open loop gain. Due to these two conditions the at virtual ground potential So the eurent flowing through Ri and RF als of an inverting terminal is, are the same. .c, Vl Ry VoIRs ‘Therefore VelVin = As == RW Ri,amplified wave with 1800 phase Here the —Ve sign indicates that the output will be a averted output). By varying the Ror Ri, the gain of the amplifier can be varied to any desired value. CIRCUIT DIAGRAM OBSERVATIONS: Frequency [Input Voltage Output Voltage Gain (vo/vo |, Gain in dB eee ae ae eta) ey Cain e!V0 | Sige Wor) [100 Hz, 1kHz 5 kHz 30 kHz 25 kHz [50 kHz 100 kHz 200 kHz 400 kHz 300 kHz 700 kHz ‘S00 kHz ~ 1MHz | MODEL GRAPH: Gain in aB “raaang Frequency > TePROCEDURE: 1. Check the components. Connections are given as per the ‘uit diagram. + Vee and - Vic supply is ‘en to the power supply terminal of the Op-Amp IC. 4. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op- Amp. 5. The output voltage is obtained in the CRO and the input and outpu: voltage waveforms are plotted in a graph sheet. DESIGN: Gain of an inverting amplifier Av = Vo/Vi = RE/Ri The required gain = 10. That is Av = - Rf Ri= 10 Let Ri= 1KQ, Then Rf= 10KQ. RESULT: ‘The design and testing of the inverting amplifier is done and the input and output waveforms were drawn. ee eww eeeaeagaeansAIM: 1. b. Non - Inverting Amplifier To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741 APPARATUS REQUIRED: ‘S.No Name of the Apparatus Range Quai 1] Function Generator 3 MHz, T 2. CRO 30 MHz I 3. | Dual RPS 0-30V i 4. [Op-Amp IC 741 T 3. | Bread Board 1 6. _| Resistors ‘As required 7. | Connecting wires and probes As required THEORY: The input signal Vs is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is alsu called negative feedback system since the output is feedback to the inverting input terminals. The Rf and Ri are the feedback and input resistance of tae circuit respectively, Av= Vol Vin= 1+ Ri Ri Here the +Ve sign indicates that the output will be an amplified wave in phase with the input. By varying the Rf or Ri, the gain of the amplifier can be varied to any desired value, PROCEDURE: 1 Check the components. Connections are given as per the circuit diagram. + Vecand - Vee supply is given to the power supply terminal of the Op-Amp IC. By adjusting the amplitude and frequency knobs of the function generator. appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheetCIRCUIT DIAGRAM OBSERVATIONS; RK Ry 0K. | Frequency Input Voltage Output V Wi) Wo) Fr 1 oltage Gain (ve/Vip 2522 2 3B [100 Hz 1kHz 5S kHz 10 kHz 25 kHz 50 kHz 100 kHz 200 kHz 500 kHz 700 kHz 400kHz | S800 kHz 1 MHz MODEL GRAPH: Gain in dB Increasing Frequency —> tqDESIC Gain of an inverting amplifier Ay=Vo/Vw = 1+Rd Ri, Let the required gain be 11, Therefore Av = 1+Ri R= 11 R/Ri= 10 Take Ri= 1KQ, Then Rf= 10KQ RESULT: ‘The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn.I. ¢, Integrator AIM: 1 To design an Integrator circuit for the given specifications using Op-Amp APPARATUS REQUIRED: S.No Name of the Apparatus Range Quantity T._| Function Generator Mila ! 2 {CRO 30 Miz ! 3._| Dual RPS 0-300 ! 4._|Op-Amp ICM ! 3. [Bread Board i 6.) Resistors 7. | Capacitors 8. | Connecting wires and probes As required THEORY: “ cireuit in which the output voltage waveform is the integral of the input voltage ‘savelorm is the integrator. Such a cireuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rr is replaced by a capacitor Cr. This circuit also ‘works as low pass filter. The expression for the output voltage is given as, Vo=~ (IRF Ci) J Vi dt Here the negative sign indicates that the output voltage is 180 ° out of phase with the ‘nput signal. The input signal will be integrated properly ifthe Time period T of the signal is larger than or equal to Rr Ci; That is, TE RrCr The integrator is most commonly used in analog computers and ADC and gnal-wave shaping cireuits. PROCEDURE: 1. Check the components, 2. Connections are given as per the circuit diagram, + + Vecand - Ve supply is given to the power supply terminal of the Op-Amp IcCIRCUIT DIAGRAM : 130K comme | mys iN ok OBSERVATIONS: Output Voltage, Vo = MODEL GRAPH: Vv Ven os: ' Vet 4, By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage (Vi= 2Vpp, IKHz square wave) is applied to the inverting input terminal of the Op-Amp, 5. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.DESIG) Given f=1 Ki, SoT = 1/T= ms Design equation is T = 22RiC Let C = wut waveforms were ‘The design of the Integrator circuit was done and the input and outp! obtained-_—*.s & «© J a a « v ’ J I ’ y 2 ’ 4 2 e 2 3 > . 3 9 2 ? ; 2 1d, COMPARATOR AIM: To design and setup a zero crossing detector circuit with OP AMP 741C and plot the waveforms. APPARATUS REQUIRED: S.No Name of the Apparatus Range Quantity 1 Function Generator 3 MHz 1 2 [CRO 30 MHz 1 3. [Dual RPS 0-300 1 4. | Op-Amp IC 741 I 5. [Bread Board 1 6_| Resistors 7. | Capacitors 8. | Connecting wires and probes As required THEORY: Comparator Voltage Comparator: A comparator is a circuit which compares a signal voltage applied at one input of an op-amp with output +Vsat = (Vcc). If the signal is applied to the inverting terminal of the op-amp it is called inverting comparator and if the signal is applied to non-inverting terminal of the op-amp it is called non-inverting comparator. In an inverting comparator if input signal is less than reference voltage, output will be +Vsat. When input signal voltage is greater than reference voltage output will be —Vsat. The vice-versa takes place in non-inverting comparator. Zero Crossing Detector Zero crossing comparator (ZCD) is an application of voltage comparator. The reference voltage is set as zero volts. When the polarity of the input signal changes, output square wave changes polarity. Here the signal is given the non-inverting terminal, So the output signal is in phase with the input signal. Such a circuit is called non-inverting zero crossing detector. In open loop configuration, the gain of the opamp is very high, so when the input voltage is above zero voltage, output of the circuit goes to + Vsat which isON rl v Ww Zero voltage, thy Si then the input voltage is belo Similarly when the -1BV. “PProximately +13, BES 10 ~ Vsat which is approxim: CIRCULT DIAGRAM OBSERVATIONS Output Voltage, Vo = MODEL GRapy;PROCEDURE: Check the components. 2. Connections are given as per the circuit diagram, + Voc and - Vee supply is given to the power supply terminal of the Op-Amp IC. 4. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage (Vi= 2Vpp, IKHz square wave) is applied to the non inverting input terminal of the Op-Amp. 5. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet, RESULT: ‘The zero crossing detector circuit was done and the input and output waveforms were obtained,peeeeeeeeneeeeeeeeeeee™ ol Ny 1.e, SUMMING AMPLIFIER ~“~, on ~~ AIM: To design and setup a summing amplifier circuit with OP AMP 741C for a gain o- uv of 2 and verify the output, “uv APPARATUS REQUIRED: ~~ S.No Namie of the Apparatus Range Quantity ~ T.__ | Function Generator 3 MHz, 7 ~~ 2. [CRO 30 MHz 1 3._| Dual RPS 0-30V T ee + Op-Amp 1c 741 1 ea 5. Bread Board 1 — 6._| Resistors a or 7. _| Capacitors % 8. _ | Connecting wires and probes As required | ~ ~ THEORY: ~, be Op-amp can be used to design a circuit whose output is the sum of several input signals. ~ Such a cireuit is called a summing amplifier or an adder. Summing amplifier can be pay classified as inverting & non-inverting summer depending on the input applied to wv ’ inverting & non-inverting terminals respectively. Circuit Diagram shows an inverting ~ adder (summing amplifier) with 2 inputs. Here the output will be amplified version of the ~ sum of the two input voltages with 180° phase reversal. es : Vo =-( Rd Ri (VitV2) ~ PROCEDURE: ~ D 1. Check the components T 2. Connections are given as per the circuit diagram. Oo ( 3. + Vec and - Vee supply is given to the power supply terminal of the Op-Amp IC, Mis T 4. Give Vi =2Vpp/1 KHz sine wave and V2 = +1Vde as shown in fig. Lo) R 5, Make sure that the CRO seleetor is in the D.C. coupling position. em» 1 6. Observe input and output on two channels of the oscilloscope simultaneously. ny ° 7. Note down and draw the input and output waveforms on the graph Lond p 2 = * L- é ddd ddddd oGetuse c $—_F—_F & ce u oF va vedud = ves re CIRCUIT DIAGRAM Ry 10K 2Vpp OBSERVATIONS: Output Voltage, Vo = MODEL GRAPH: Time,t ——> Input signal Output Waveform DESIGN: The output voltage of an inverting summing amplifier is given by V. (Vi+V2) Let R= Re= 10 KQ for unity gain, Then Vo= - (Vi#V2) RESULT: -(Rr/ Ri) The design of the adder circuit was done and the input and output waveforms were obtained.What is a comparator? A comparator is reuit which compares a signal voltage applied at one input of an op-amp with known reference voltage at other input. It is basically an Op-amp with output Vsa: (»Vee) What is the difference between a basic comparator and ZCD? Comparator has only one reference voltage whereas ZCD has zero reference voltage. Give the gain expression for inverting and non inverting amplifier. Inverting Amplifier RORi Non inverting Amplifie 1+( RORI) State some linear and non linear applications of Op- amp. Linear: a) Adder b) Subtractor ©) Instrumentation amplifier Non linear: a) Rectifier b) Peak detector ©) Clippers and Clampers.Exp. No.2 Measurement Of Op-Amp Parameters AIM To measure various op amp parameters. APPARATUS REQUIRED: S.No ‘Name of the Apparatus | Range Quantity | 1. _| Funetion Generator 3 MHz I 2. | CRO 30 MHz 1 | rz Dual RPS cy, ~ ] it [4] Op-Amp IC741 1 3. _| Bread Board H 6. _| Resistors ‘As required 7, | Capacitors As required | 8. | Connecting wires and probes ‘As required | THEORY ‘An ideal op-amp draws no current from the source and its response is also independent of temperature. However, a real op-amp does not work this way. Current is taken from the source into op-amp inputs. Also the two inputs respond differently to current and voltage due to mismatch in transistors. Input bias current The op-amp’s input is a differential amplifier, which may be made of BJT or FET. In either ease the input transistors must be biased into this linear region by supplying currents into the bases, In an ideal op-amp, no current is drawn from the input terminals. However, practically. input terminals conduct a small value of de current to bias the input transistors when base currents flow through external resistances, they produce a small differential input vortage or unbalance; this represents a false input signal. When amplified, this small input unbalance produces an offset in the output voltage. The input bias current shown on data sheets is the average value of base currents entering into the terminals of an op-amp. Tn= (In' + by 2CIRCUIT DIAGRAMS To Measure Input Offset Voltage To Measure Input Bias Current To Measure CMRR Ry 100K 000 AW ky 1000‘ < Geoaceeeeece « Cee UBuUeL ev Ve VevrteeuUeUvUsse To Measure Slew Rate For 741, the bias current is S00nA or less. The smaller the input bias current, the smaller will be the offset at the output voltage. Input offset current The input offset current is the difference between the two input currents driven from a common source Ittells you how much larger one current is than the other. Bias current compensation will work if both bias currents In” and Is’ are equal. So, the smaller the input offset current the better the OP amp. The 741 op-amps have input offset current of 20nA. Input offset voltage Ideally, the output voltage should be zero when the voltage between the inverting and non-inverting inputs is zero. In reality, the outpu: voltage may not be zero with zero input ismatches, tolerances, and so on inside voltage. This is due to un-avoidable imbalances. the op-amp. In order to make the output voltage zero, we have to apply a smalll voltage at the input terminals to make output voltage zero. This voltage is called input offset voltage Lie.. input offset voltage is the voltage required to be applied at the input for making output voltage to zero volts. The 741 op-amp has input offset voltage of SmV under no signal conditions. Therefore, we may have to apply a differential input of SmV, to produce an output voltage of exactly zero. Slew rate Among all specifications affecting the ac operation of the op-amp, slew rate is the most important because it places a severe limit on a large signals operation. Slew rateisdefined as themaximum rate at which the output voltage can change. The 741 op-amp has @ typical slew rate of. volts per microsecond (Vis). This is the ultimate speed of a typical 741 its output voltage can change no faster than 0.5V/qs. If we drive a 741 with large step input, it takes 20ps (0.5 V/jis*10V) for the output voltage to change from 0 to 10V. CMRR In an ideal ferent amplifier, differential gain Aq is infinite while common mode gain ‘Ac must be zero. However, in a practical differential amplifier; Aa is very large and Ac is, very small. .» the differential amplifier provides very large amplification for difference signals and very small amplification for common mode signals. Many disturbance signals/noise signals appear as a common input signal to both the input terminals of the differential amplifier. Such a common signal should be rejected by the differential amplifier. “The ability of a differential amplifier to reject a common-mode signal is expressed by a ration called Common Mode Rejection Ratio, denoted as CMRR™. CMRR is defined as the ratio of the differential voltage gain Aa to common mode voltage gain ‘Ac. CMRR = Au/Ac Ideally Ac is zero. Hence, the ideal value of CMRR is co. PROCEDURE a) Input Bias Current 1. Connect the circuit as shown in Fig. 2. Measure the output voltage from which the inverting input bias current can be calculated as In” = Vo/RE. 3. Connect the circuit as shown in Fig. 4. Measure the output voltage from which the non-inverting input bias current ean be calculated as In * = Vo/RE. 5 Input bias current Iy = (Ip" + Ip)/2 b) Input Offset Current Input offset current, [los] = OS|=Iy" = ly" ©) Input Offset Voltage 1. Connect te circuit as shown in Fig, Measure the output voltage using multimeter 3. Calculate offset voltage as Vos = Vo / (1+ RE/R1) d) d) Slew Rate 1. Connect the circuit as shown in Fig.é IF y eeveteveueeeetcere rp vdeusee ol e 2. Give square wave input (2Vp-p) from the signal generator so that the output is a square wave at 1kHz. 3. Increase the frequency slowly until the output is just barely a triangular wave. 4, Calculate slew rate as SR = (AV /.A 0. ©) CMRR 1. Connect the cireuit as shown in Fig 2. Give sine wave input (2Vp-p) from the signal generator and measure Vo. Calculate CMRR using expression CMRR= Ad/Ac Express CMRR in dB using the expression : 20 log (Vo/Vi) RESULT The input bias current, input offet current, input offet voltage and slew rate of the op- amp were determined. Viva Questions 1. State the ideal characteristics of Op-amp. i) Open loop gain, Aol = Input impedance, Ri = «0 Output Impedance, Ro = 0 Zero Offset, Vo = 0 v) Bandwidth, BW =o 2. Why differential amplifier is used as an input stage of IC op-amp? The differential amplifier eliminates the need for an emitter bye-pass capacitor. So, differential amplifier is used as an input stage in op-amp ICs 3. What does operational amplifier refers to? Operational amplifier refers to an amplifier that performs a mathematical operation. A typi 1 op-amp is a DC amplifier with a very high voltage gain, very high input impedance and very low output impedance. 4, What causes slew rate? The rate at which internal or external capacitance of Op-amp changes causes slew rate, Also slew rate is caused by current limiting and saturation of ermal stages of op-amp where a high frequency, large — amplitude signal is applied, 5. State some applications of integrator. i) Analog computers ii) ADCiii) Signal wave shaping circuits. 6, What are the characteristics of Comparator? i) Speed of oper ii) Accuracy iii) Compatibility of the output. 7. List some applications of comparator. i) Window detector ii) Time marker generator iii) Phase meter iv) Zero crossing detector 8. What are the modes in which op-amp is operated with finite gain and infinite gain? i) Open loop mode with infinite gain: Comparator ii) Closed loop mode with finite gain: Amplifier 9. Why is 1C741 op-amp not used for high frequency applications? i) Op-amp IC741 has very low slew rate (0.5V/uS) and therefore cannot be used for high frequency applications. 10. What is unity gain circuit? i) Voltage follower is called unity gain cireut, The circuit does not amplify and provides constant gain of unity. eee a, ~ ~, ~ ~ ~ ~~ ~ ~~, ~, =~ ~~ ~ ~ Xs ~, ™,ot Exp. No.3 SCHMITT TRIGGER AIM: To design and setup a Schmitt trigger. plot the input output waveforms and measure WUT and VL APPARATUS REQUIRED: S.No ‘Name of the Apparatus Range Quantity 1, _ | Function Generator 3 Miz 1 2 [CRO 30 Miz 7 3. [Dual RPS 0-30V 4. [Op-Amp IC 741 1 3. | Bread Board T 6. _ | Resistors ‘As required ‘Connecting wires and probes 8 THEORY: It is a regenerative comparator or it is 8 comparator with hysteresis. This cireuit uses positive feedback and the op-amp is operated in saturation. The output can take two values +Vsat and —Vsat, When output = +Vsat, the voltage appearing at the non-inverting terminal is Ver or UTP = +Vsat( Ri/Ri+R2) called the upper threshold point. Similarly When output = - Vsat, the voltage appearing at the non-inverting terminal is Vir or LTP is greater than UTP. the = -Vsat( Ri/Ri+R2) called the Jower threshold point. When V ilarly When Vin is less than LTP: the output output will switch from +Vsat to —Vsat. will switch from -Vsat 10 +Vsat which is shown in the graph. The difference between UTP-LTP is called hysteresis. Hysteresis avoids false triggering of the circuit by noise circuit is used to convert Hysteresis curve is the plot of Vo versus Vin . Schmitt tigg any inregular wave into square wave, PROCEDURE: 1, Check the components, re given as per the circuit diagram. 2. ConnectionsLccecerporepecerrereaceeiidisten Vio CIRCUIT DIAGRAM OBSERVATIONS: MODEL GRAPH:3. + Vecand = Vee supply is given to the power supply terminal of the Op-Amp IC 4. Give Vi =10Vpp /1 KHz sine wave. 5. Observe input and output on two channels of the oscilloscope simultaneously. 6. Note down and draw the input and output waveforms on the graph DESIGN: UTP = +Vsat( R1/R1+R2) Let UTP = +3V and LTP = -3V. Vsat=+13V UTP, +3 = +13( RUR1+R2) LetR1=1KQ Then R2 = 3.3KQ RESULT: The Schmitt trigger is done, plotted the input output waveforms and measured Vor and Vit Viva Questions 1. What is the basic ifference between comparator and Schmitt trigger? ‘A comparator compares the input signal with reference voltage and gives the ‘output whereas Schmitt trigger operates between two reference points LTP and UTP. How can you obtain triangular wave using schmitt trigger? The output of Schmitt trigger when connected to integrator yields triangular output Why Schmitt trigger is called regenerative comparator? The reference voltages LTP andUTP are regenerated depending on the output voltages +Vsat and —Vsat. What is hysteresis voltage in Schmitt trigger? The difference in voltage between lower and upper threshold voltage is called hysteresis voltage.Exp No.4 Difference Amplifier AIM: To design and setup a difference amplifier circuit with OPAMP IC 741C fora gain of 2 and verify the output. APPARATUS REQUIRED: S.No ‘Name of the Apparatus Range Quantity I | Funetion Generator 3 MHz, | 2. [CRO 30 MHz 1 3. [Dual RPS 0-30V y 4. | Op-Amp IC 741 1 5. | Bread Board 1 6. | Resistors 7. | Capacitors 8.__| Connecting wires and probes As required THEORY: A difference amplifier is a circuit that gi ves the amplified version of the cifference of the two inputs, Vo =A(V1-V2), Where Vi and Ve are the inputs and A is the voltage gain. Here input voltage Vi is connected to non-inverting terminal and V2 to the inverting terminal. This is also called as differential amplifier. Output of a differential amplifier can be determined using super position theorem. When Vi=0, the circuit becomes an inverting amplifier with input V2 and the resulting RE/Ri (V2). When V2=0, the circuit become a non-inverting amplifier with input V1 and the resulting output is Vo output is Vo= RERI(V1). Therefore the resulting output according to super position theorei: is Vo= Vort Voo = RIR(V1-V2) PROCEDURE: 1. Check the components. 2. Connections are given as per the circuit diagram. d art PPS, f tes r? yr ve, A f POLIT SPPPPIIPPPE3. + Veo and - Vc supply is given to the power supply terminal of the Op-Amp IC e wave and V2 = +1Vde as shown in fig 4, Give Vi =2Vpp/1 KHz 5. Make sure that the CRO selector is in the D.C. coupling position. CIRCUIT DIAGRAM 7 ND ND » ~~ ~ ” wv = oe » oy a) OBSERVATIONS: ~? : Output Voltage. Vo = . 9 MODEL GRAPH: 2 =) - 2 ov e 3 Ua —Time,t — Input signal Output Waveform 6. Observe input and output on two channels of the oscilloscope simultaneously 7. Note down and draw the input and output waveforms on the graph. oboe.DESIGN: Given the gain = 1 Vo = Vor+ Voa = RYR(V1-V2) That is Rr/ R Let i= 10KQ Then Re= 10KQ. RESULT: The design of the difference amplifier circuit was done and the input and output waveforms were obtained,LL2¢ 7 AF 77 FF 7 y- 7 7 Tanah £ fF ¢ ¢ # | euvuecuvececceccrcicddddcd STL S Seo a e Exp. No.5 Astable and Monostable Multivibrators using Op amp 5.a. Symmetrical And Asymme' Amp rical Astable Multivibrators Using Op AIM: To design and setup symmetrical and asymmetrical astable multivibrators using Opamp 741. plot the waveforms and measure the frequency of oscillation. APPARATUS REQUIRED: S.No ‘Name of the Apparatus Range Quantity 1. | Funetion Generator 3 MHz 1 2. [CRO 30 Miz 1 3. | Dual RPS 0-30V 1 4. [Op-Amp ICT 1 5. | Bread Board 1 6. [Resistors As required 7. | Connecting wires and probes As required THEORY: In this circuit, the opamp is operated in saturation mode and the output swings between +Vsat and —Vsat giving square wave output. This circuit is also called free running oscillator or square wave generator . A positive feedback with feedback factor B = Ri (Ri+R2) is provided to the non-inverting terminal, When Vo= +Vsat, the capacitor C starts to charge to + Vsat through R. when the capacitor voltage crosses +BVsat, output switches from +Vsat to ~Vsat, Now the voltage appearing at the non-inverting terminal is —BVsat and capacitor discharges through R towards -Vsat. When the capacitor voltage crosses ~BVsat, the output switches from —\ sat to + Vsat and this process continues to generate square wave output with time period T= ow + Tor 2RC Inf(L+Y(1-B)]. In asymmetrical astable multivibrators, the charging and discharging time of capacitor is made unequal to get ymmetrical square wave with different Ton and Toft.CIRCUIT DIAGRAM : a) SYMMETRCAL ASTABLE MULTIVIBRATOR Rak nisv Ve, 2 ir m >t vo CORE 3hy a DI Rn s6k DD tt ve ae SE come iv a | = Re 10K 7 D2 “ ° 3 / 14 ce LIIDIIIIII IS/ - 99 oe e FEEEREPPEATINEFLYIIIINIIIIIII) OBSERVATIONS: Output Voltage, Vo = Time Period.T = Voltage Across Capacitor,Vc = DESIGN a). SYMMETRICAL ASTABLE MULTIVIBRATOR Given f= 1 KHz So T= 1/f= ms And B= Ri / (Ri#Ro) Let Ri = 10KQ,, and R2 =10KQ Then = 0.5 Therefore T= 2.2RC =Ims Let C= 0.1pF Then R= 4.7KQ b) SYMMETRICAL ASTABLE MULTIVIBRATOR Given f= 1 KHz So T = Too + Tor=1/f= Ims Also Duty cycle = Ton/(Ton+Tarr) = 0.66 or 66% Solving above two equations, To = 0.66ms Tor= 0.33ms For B=0.5, Tor= 1.1RnC = 0.66ms Let C= 0.1F Then Ra = 6.2KQ = 5.6KQ (Sid) Similarly Tor = 1.1RnC = 0.33ms Then Rr = 3KQ=3.3 KQ (Sid PROCEDURE: 1, Check the components. 2. Connections are given as per the cireuit diagram. 3, + Vecand - Vec supply is given to the power supply terminal of the Op-Amp IC.citor voltage 4 The output voltage is obtained in the CRO. Observe output and capacitor voltag on two channels of the oscilloscope simultaneously. MODEL GRAPH: 2) SYMMETRICAL ASTABLE MULTIVIBRATOR b) ASYMMETRICAL ASTABLE MULTIVIBRATOR com SE | pes though Ry, Votage Ourput Vette RESULT: ‘The design and testing of the astable mu brator is done and the input and output waveforms were drawn, ™~ % es re © © es CS) - ~- r=] es ef Pd a —_What is multivibrator? A multivibrator is an electronic circuit used to implement a variety of simple two- ers and flip-flops. It is characterized by two state systems such as oscillators, amplifying devices (transistors, electron tubes or other devices) cross-coupled by resistors or capacitors What is quasi stable state? Change from one state to another without any external trigger is termed as quasi stable state. What are the various modes of operation of multivibrator? Explain Astable mode - 2 quasi stable state Monostable ~ 1 quasi and on stable state. Bistable ~ 2 stable states. What is one-shot multivibrator? The monostable is also called as one-shot multivibrator as it produces a single pulse of specified duration in response to each extemal trigger signal. Only one stable state exists. When an external trigger signal is applied the output changes its state.Exp. No. 6. Monostable Multivibrator Using Op Amp AIM: “To design and setup a monostable multivibrator usin Op-amp 741 and {i Plot the waveforms (ii) Measure the time delay APPARATUS REQUIRED: _ Name of the Apparatus Range iE Cisam es 7. | Function Generator 3 MHz foot 2, [CRO 30 MHz p | 3, | Dual RPS 0-300 ao 4. | Op-Amp IC 741 1 3, | Bread Board 1 6. _ | Resistors Fs required 7,_| Capacitors ‘As required 8._| Diode ‘As required 9, _] Connecting wires and probes ‘As required | THEORY: The circuit ‘The monostable multivibrator is also called as one shot multivibrator. produces a single pulse of specified duration in response to each extemal trigger pulse. It allways has one stable state (+Vsat), When an external tigger is applied. the output site able state (-Vsat). The circuit remains in this changes and the new state is called quasi st terval 1 original state after thi state for a fixed interval of time and then it returns to thi 0.7V to -BVsat.The This time interval is determined discharging of the capacitor from time period of quasi stable state or the delay is given by .69RC PROCEDURE: 1. Check the components. 2. Connections are given as per the circuit diagram. 3, + Vecand - Vec supply is given to the power supply terminal of the Op-Amp IC.4. Put the function generator output to square wave mode, Adjust the amplitude to SV. CIRCUIT DIAGRAM : MODEL GRAPH: Frigpering Pulse Vos eve LE, LCoscilloscope simultaneously. Draw the waveforms on the graph, 7. Measure the time delay. DESIGN: Time Period T= 0.69RC Let T= Ims: and C= 0.1 uF. Then R= 15KQ Feedback factor B = R2(RI+R2) Let B= 0.5 or 1/2 R2(RI+R2) = 1/2 IfRI=10KQ ; R2=10KQ For triggering circuit RdCd= 0.0016 Let t= 3ms and Cd = 0.01 iF; then Rd = 470 D1 & D2 are diodes IN 4001 OBSERVATIONS: Output Voltage, Vo = Time Period, Voltage Across Capacitor, Ve = RESULT: The design and testing of the monostable multivibrator is done and the input and output waveforms were drawn, Observe trigger input . output and capacitor voltage on different channels of the Jd | PPPOE ECLLIIIILIIIIIIIILI NII IIIA ?Exp.No.7 Square Wave and Triangular Wave Generators n and setup a square wave and triangular wave generators using Op-Amp 741 and plot the output waveforms APPARATUS REQUIRED: Name of the S.No Range Quantity, Apparatus 3 CRO | 30MHez 1 2 Dual RPS. 0-30V = 3 Op-Amp | C741 2 4, | Bread Board = A 5. Resistors [As required 6 Capacitors As required Connecting wires 7. and probes As required THEORY about a triangular wave generator using opamp IC. Triangular wave is This experiment 1 periodic, nonsinusoidal waveform with a tiangular shape. The most important feature of a triangular wave is that it has equal rise and fall times . The applications of triangular wave include sampling circuits, frequency generator circuits, tone generator circuits ete, There are many methods for generating tr s but here we focus on method ngular wa using opamps. This circuit is based on the fact that a square wave on integration gives a triangular wave. The cireuit uses an opamp based square vave generator for producing the square wave and an opamp based integrator for integrating the square wave PROCEI 1. Check the component DURE: BR Connecti re given as per the circuit diagram. + Veo and ~ Vee supply given to the power supply terminal of the Op-Amp ICs,, d 4. The square wave form obtained from the output of astable multivibrator is applic’ to the inverting input terminal of the integrator circuit. 5. The output voltage is obtained in the CRO and the square and triangular waveforms are plotted in a graph sheet. CIRCUIT DIAGRAM MODEL GRAPHee oleic © ST Pf i ee ee tceeove a a ee ee @. DESIGN: Square Wave Generator Given f= 1 KHz So T= I/f'= Ims And B= Ri /(Ri+R2) Let Ri = 10KQ., and R2 =10KQ Then B = 0.5 Therefore T= 2.2RC =Ims Let C = 0.1pF Then R = 4.7KQ Triangular Wave Generator Given f=1 KHz So T= 1/f= Ims Design equation is T = 2nRiC Let C= 0.01pF Then Ri= 15SKQ Take Rf= 10Ri = 150KQ RESULT Designed and setup the circuit of a square wave generator and triangular wave generator.Plotted the wave forms.Exp. No.8 RC PHASE SHIFT OSCILLATOR USING OP AMP All To Design and setup a RC phase shift oscillator using Op-Amp 741 and (i) Plot the output waveform (ii) Measure the frequency of oscillation: APPARATUS REQUIRED: S.No Name of the Apparatus Range Quantity 1. ] Function Generator 3 MHz 1 2. [CRO 30 MHz 1 3. [Dual RPS 0-30V 1 4. | Op-Amp 1C 741 1 5. | Bread Board 1 6. Resistors As required 7._| Capacitors As required 7. | Connecting wires and probes As required THEORY: RC phase shift oscillator uses op-amp, inverting amplifier mode and the circuit generates its own output signal. It consists of an op-amp as an amplifier and 3 RC cascaded network as the feedback circuit, Since the op-amp is used in the inverting mode. any signal that appears at the inverting terminal is shifted by 180° at the output. An additional 180° phase shift required for oscillation is provided by the cascaded RC network. Thus the total phase shift around the circuit is 360° or 0°. At some specific frequency, the phase shift of the cascaded RC network is exactly 180° and feedback factor is 1/29. If the gain of the amplifier is 29, the toist loop gain of the circuit becomes 1. The circuit will oscillate at this specific frequency arid is given by 1 2nVORC "| LECCLELLIIILIIIISII DIL I INIA M rfPROCEDURE: 1. Check the components. 2. Connections are given as per the circuit diagram, ind ~ Vex supply is given to the power supply terminal of the Op-Amp IC CIRCUIT DIAGRAM : 100K 3aKa ‘« SY looiF 0.01 0.010 Ny c c ¢ OBSERVATIONS: Output Voltage, Vo = Time Period, = Frequency. MODEL GRAPH: Tame (=k s obtained in the CRO and output voltage waveform is plotted 4, The output volta; ina graph sheet, DESIGN: Let f= | KHz, and C= 0.01,FR=68KQ Gain = 29 RURi = 29 TERI = 3.3KQ:: RE= 95.7KQ Use 100KQ pot RESULT: The design and testing of RC pha hift oscillator is done and the output waveform is drawn. Viva Questions 1, What is meant by oscillator? An oscillator is a circuit which produces an output signal without providing any input signal 2. What is Barkhausen criterion? An amplifier with positive feedback results in oscillations if the following conditions are satisfied: © The loop gain ( product of the gain of the amplifier and the gain of the feedback network) is unity. © The total phase shift in the loop is 0°. This is known as the Barkhausen criterion for oscillation 3. What are the essential parts of an Oscillator? Tank circuit (or) Oscillatory circuit. b) Amplifier (Transistor amplifier) c) Feedback Circuit. 4. List the advantages of Re phase shift Oscillator. + Ih is best suited for generating fixed frequency signals in the audio frequency range. + Simple Circuit + Pure sine wave output is possible. Why RC phase shift is needed in a RC phase shift Oscillat The amplifier used causes a phase shift of 180° than the feedback network should create phase shift of 180°. to satisfy the Barkhaus n Criterion. Hence ina phase shift oscillators, three sections of RC circuit are connected in cascade, each introducing a shift of 60° , thus introducing a total phase shift of 180° , due to feedback network. PP PPPPP ARP TEP PP FFF PP HTHEB FH HE EDExp. No.9 Wien Bridge Oscillator Using Op-Amp AIM: To design and construct a Wien bridge oscillator using Op-Amp 741 and (j) Plot the output waveform ({i) Measure the frequency of oscillation APPARATUS REQUIRED: S.No Name of the Apparatus Range Quantity T,_ | Function Generator 3 MHz H az CRO 30 MHz 1 3. | Dual RPS 0-30V | 4. [Op-Amp IC 741 T 5. | Bread Board 1 6. _ | Resistors As required 7. | Capacitors As required 8.__| Connecting wires and probes As required | THEORY: It is the commonly used audio frequency oscillator which employs both positive and negative feedback. The feedback signal is connected in the non-inverting input terminal so that the amplifier is working in non-inverting mode. The Wien bridge circuit is connected between amplifier input terminal and outgut terminal. The bridge has a series RC network in one arm and a parallel RC network in the adjoining arm. In the remaining two arms of the bridge, resistor RI and Rf are connected, The phase angle criterion for oscillation is that the total phase shift around the circuit must be zero. This condition ‘occurs when bridge is balanced. At resonance, the frequency of oscillation is exaetly the resonance frequency of balanced Wien bridge and is given by fo = 1/ (2aRC). At this frequency. the gain required for sustained oscillation is 3.lt is provided by the non- + (RORI inverting amplifier with GaiCIRCUIT DIAGRAM : OBSERVATIONS: Output Voltage, Vo = Time Period,T = Frequency,F = MODEL GRAPH: ot2 T= Me Te Ime f= 1KH:cceeceecee BFevVdedves OU eee eOCCoCCEE Ms PROCEDURE: 1, Check the compon . 2. Connections are given as per the circuit diagram. + Vec and - Vec supply is given to the power supply terminal of the Op-Amp IC. 4. The output voltage is obtained in the CRO and outpu: voltage waveform is plotted ina graph sheet. DESIGN : fose = 1/2nRC Let f= IKHz., and C= 0.1pF R=15KQ 1+ (RuRy) =3 IfRi = 10KQ Rr=20KQ Use 47K2 pot RESULT: The design and testing of wein bridge oscillator is done and the output waveform is drawn. Viva Ques 1. Wein bridge oscillator uses positive and negative feedback. Why? ns, Negative feedback is used for stability gain positive feedback is used for oscillation What is the function of lead-lag network in Wein bridge oscillator? The function of lag lead network is to obtain the zero degree phase shift.xp. No. 10 PRECISION RECTI AIM: To set up a precision rectifier (half wave rectifier) using IC 741 APPARATUS REQUIRED: S.No Name of the Apparatus, Range Quantity 1 Function Generator 3 MHz, 1 ‘CRO 30 MHz, a 3. | Dual RPS 0-30V e + | Op-Amp IC741 1 3. | Bread Board 1 6. _| Resistors ‘As required 7. | Diode ‘As required 8. _ | Connecting wires and probes Asrequired THEORY: The precision rectifier, wi is also known as a super diode. is a configuration obtained with an operational amplifier in order to have a circuit behaving like an ideal diode and rectifier. It can be useful for high-precision signal processing. ‘There are two types of half wave rectifiers. One is inverting half wave rectifier and second one is non-inverting half wave recti ier. The below circuit show the non- inverting half wave rectifier with diode (0A79) in the feedback loop of an op-amp. PROCEDURI 1, Check the components 2. Connections are given as per the circuit diagram, 3. + Vee and - Vee supply is given to the power supply terminal of the Op-Amp IC 4. The output voltage is obtained in the CRO and output voltage waveform is plotted in a graph sheet. ‘eo “e on ~ on o~ ~~ oe” ~”* eo” ea” = .~ wu ae aw w = oO wm ~ ~ a> s er) S +? CIRPree CGCeEeg Py SER aeecece PRIPP. FFE FEELS. A CIRCUIT DIAGRAM: ase aN. - A vo a | \ sv p; 2\pp = ikke OBSERVATIONS: Output Voltage, Vo = MODEL GRAPH: RESULT: The circuit of precision rectifier is done and the output waveform is drawn.Exp. No. 11 ASTABLE MULTIVIBRATOR USING IC 555 AIM: To design and setup symmetrical and asymmetrical astable multivibrators using IC and (i) Plot the output waveform (ii) Measure the frequency of oscillation. APPARATUS REQUIRED: S.No Name of the Apparatus Range Quantity 1, ] Function Generator 3 MHz 1 2. [CRO 30 MHz. 1 3. | Dual RPS 0-30 1 4 [IC 355 1 3. | Bread Board 1 6. _ | Resistors ‘AS required 7. _| Capacitors As required 8. | Connecting wires and probes As required THEORY: The 555 timer is a highly stable device for generating accurate time delay For f= Gai mMPIP PED Ty) eed sede tf Ceesesccid eee TIPPPP PPP PTT R, Apa 4oe Pelt For high pass filter at lower cut-off frequency. 1 f= Fae Gain is given by, a y aeniett pate MODEL GRAPH: ont h “ ~ Frequency (a) pe” aa Je pcan Sede) ‘ | Phase RESULT: i. The lower cut-off frequency = kHz ii, The upper cut-off frequency = kHz. iii, The pass band gain of the filter =14d. BAND STOP FILTER CIRCUIT DIAGRAM: PROCEDURE: 1. Construct the circuit as shown in circuit diagram. 2. Apply ai frequencies, 3. Calculate the gain in dB. 4, Plot the frequency response. input sine wave and measure the amplitude of output waveform for different values of input OBSERVATIONS: SINo. | Input frequency | Output voltage | Gain 20 log 20 log VolVi i 100 = 2. 200 - | Ey 500 4 IK 7 | 3 15K oo - = 2K — an SK ~ — |DESIGN: For high pass filter at lower cut-off frequency MODEL GRAPH: Stop Bare (Pas Bae sande ip cy Rospens Output Frequerey(t) (LegatnmeSeae) Prose Shit FraguencyRESULT: i. The lower cut-off frequeney = kHz {i, The upper cut-off frequency = kHz Uli, The pass band gain of the filter = DIMAIP Plo Ses" ° weeee Po SeSSCITeTerrrese ees AIM: To de APPA 1.CR 2. Sig 3. Bre 4. Dui Note Tenet resist the n The f carExp.No.: 14 Notch Filter To Eliminate The 50hz Power Line Frequency AIM: To design a notch filter which eliminate the 50 Hz power line frequency. APPARATUS REQUIRED: 1. CRO (Dual channel) - 1 No 2. Signal Generator - 1 No 3. Bread Board - 1 No 4, Dual channel power supply ~ 1 No ‘THEORY: Notch filter is narrow band reject filter. Ths isa passive filter composed of two T-shaped networks, One network is made up of two resistors and a capacitor, while the other is made of two capacitors and a resistor. One drawback of above notch filter is that it has relatively low figure of merit Q. However. Q of the network can be increased significantly ifit is used with the voltage follower. ‘The frequency at which the signal needs to be rejected is given as 1 eRe CIRCUIT DIAGRAM: rR Rk resins PROCEDURE: 1. Construct the circuit as shown in circuit diagram. 2. Apply an input sine wave and measure the amplitude of output waveform for different values of input frequencies 3, Caleulave the gain in dB. 4, Plot the frequency response. OBSERVATIONS: “SINo. | Input freq TT EL =] 10 | Output voltage Gain in dB0. ~ 7 TT 1 4 100 20 a=—ale tn fe fe FREQUENCY! —————+ Frequency Response RESULT: The noteh filter is designed to eliminate 50 Hz frequency and also implemented. ee PIII I LECIILILIIIITL IIIT IIIS sens AIM: To set up a posit APPARATUS J |. CRO (Dual et 2. Bread Board - 3. Dual channel 4, Rheosta. res 5. Voltmeter, an 6, Connecting ‘THEORY: 7803 isa three wide r asacomplete you need are DC and then i transformer, b circurr pI >? oe. PROCEDU 1. Check all 2. Setup ci 3. Switeh o 4. Vary theExp. No. 16 IC VOLTAGE REGULATORS (78XX and 79XX) I. POSITIVE VOLTAGE REGULATOR USING IC 7805 AIM: To set up a positive voltage regulator using IC7805 and plot the regulation characteristics: APPARATUS REQUIRED: 1. CRO (Dual channel) - 1 No 2. Bread Board - | No 3. Dual channel power supply ~ 1 No 4, Rheostat, resistor, capacitor, IC723 5. Voltmeter, ammeter 6. Connecting wires THEORY: 7805 is a three terminal linear voltage regulator IC with a fixed output voltage of SV which is useful in a of applications. As per the datasheets of 7805 IC, the basic circuit required for 7805 t0 work then all wide range asa complete regulator is very simple. In fact, if the input supply is an unregulated DC Volt ‘you need are two capacitors. The AC power supply from mains first gets converted into and unregulated DC and then into a constant regulated DC with the help of this circuit, The circuit is made up of transformer, bridge rectifier made up from diodes, linear voltage regulator 7805 and capacitors. CIRCUIT DIAGRAM: + ag . OT PROCEDURE: 1. Check all the components 2, Set up circuit on the breadboard and check the connections 3. Switch on the power supply J. Vary the input de voltage and measure the input and output voltages using voltmeter5. Vary the toad resistance potentiometer and measure output voltage and current 6. Plot line regulation and load regulation characteristics on the graph 7. Calculate percentage load regulation OBSERVATIONS: INPUT(V) +) REGULATED OUTPUT | | RESULT: Positive voltage regulator was implemented, verified and studied. I. NEGATIVE VOLTAGE REGULATOR USING IC 7912 AIM: To set up a negative voltage regulator using IC7912 and plot the regulation APPARATUS REQUIRED: 1. CRO (Dual channel) - 1 No 2. Signal Generator - 1 No 3. Bread Board - 1 No 4, Dual channel power supply — 1 No 5. Rheostat, resistor, capacitor, 1723 6. Voltmeter, ammeter 7. Connecting wires PELIILLIII IIIA AAAI reereeee TH 791 reg con safTYVIFIIAP Cobdddded. é , papopal gay ee TPP ee LELICEEE ©eeveeeoee ee o ree e THEORY: 7912 is a negative 12V Voltage Regulator that restricts the voltage output to -12V and draws -12V regulated power supply. The 7912 is the most common, as its regulated -12-volt supply provides a convenient power source for most TTL components. These regulators employ internal current limiting safe area protection and thermal shutdown for protection against virtually all overload conditions. Low eround pin current of the LM7912 allows output voltage to be easily boosted above the preset value with a resistor divider. The low quiescent current drain of these devices with a specified maximum change with line and load ensures good regulation in the voltage boosted mode. CIRCUIT DIAGRAM PROCEDURE: 1. Check all the components 2. Set up circuit on the breadboard and check the connections 3. Switch on the power supply 4. Vary the input de voltage and measure the input and output voltages using voltmeter 5. Vary the load resistance potentiometer and measure output voltage and current 6, Plot line regulation and load regulation characteristics on the graph 7. Caleulate percentage load regulation OBSERVATIONS: UT(V) REGULATED OUTPUT +RESULT: Negative voltage regulator was implemented, verified and studied. pec recr er siqstiddd LIP IIIS MMIII,pe? eee FIVIVIN?P eeedccce roy ees 26 rep oo Exp. No.16 Study of PLL IC AIM: To study phase lock loop and its capture range, lock range and free running VCO. APPARATUS REQUIRED: [SNo] Name of the Apparatus Range Quantity T. | Regulated Power Supply 0-30V 1 2, [PLLIC NE 565 I 3. | Bread Board p 4, | Resistors ‘As required 3. | Capacitors As required 6. | Connecting wires and probes As required THEORY: PLL has emerged as one of the fundamental building block in electronic technology It is used for the frequency multiplication, FM stereo detector , FM demodulator . frequency shift keying decoders, local oscillator in TV and FM tuner. It consists of a phase detector, a LPF and a voltage controlled oscillator (VCO) connected together in the form of a feedback system. The VCO is a sinusoidal generator whose frequency is determined by a voltage applied to it from an external source. In effect, any frequency modulator may serve as a VCO The phase detector or comparator compares the input frequency, fin , with feedback frequency fot ,( output frequency). The output of the phase deteetor is proportional to the phase difference between fin and fow . The output voltage of the phase detector is a DC voltage and therefore m is often refers to as error voltage . The output of the phase detector is then applied to the LPF , which removes the high frequency noise and produces a DC lend. The DC level, in term is the input to the VCO. The output frequency of the VCO is directly proportional to the input DC level, The VCO frequency is compared with the input frequencies and adjusted until it is equal to the input frequency.PIN DIAGRAM: v ul-nc Input T top —]>— |v veooupj4 |3] 6 5 Input to phase det. from VCO—| 5 Reference Outpur—|6 External C for VCO Demodulation Output —External R for VCO CIRCUIT DIAGRAM: Demodulation Output Reference Output VCO Output MODEL GRAPH: LockRange In short, PLL keeps its output frequency constant at the input frequeney. Thus, the PLL goes through 3 states. 1, Free running state. 2. Capture range / mode 3. Phase lock state. =Before input is applied. the PLL is in the free running state. Once the input frequency is applied, the VCO frequency starts to change and the PLL is said to be the capture range/mode. The VCO frequency cantinues to change (output frequency ) until it equals the input frequency and the PLL is then in the phase locked state, When phase is locked, the loop tracks any change in the input frequeney through its repetitive action, Lock Range or Tracking Range: It is the range of frequencies in the which the VCO, once locked to the input signal, will remain locked ity of *f O" over which the nity of f O over Capture Range (f C) : Is the range of frequencies in the vi loop will acquire lock with an input signal initially starting out of lock . a Phase {irene veo Loe Detector Filter PROCEDURE : 1, The connections are given as per the circuit diagram. 2, Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal to zero. Compare it with the calculated value = 0.25 / (Rr C1). 3. Now apply the input signal of 1 Vee square wave at a | KHz to pin 2. Connect one channel of the scope to pin 2 and display this signal on the scope. 4, Gradually increase the input frequency till the PLL is locked to the input frequency. This frequency f1 gives the lower end of the capture range. Go on increasing the input frequency, till PLL tracks the input signal, say ,to a frequency f2.This frequency {2 gives the upper end of the lock range. If input frequency is increased further, the loop will get unlocked. 5, Now gradually decrease the input frequency till the PLL is again locked. This is the the input frequency frequency f3, the upper end of the capture range. Keep on decreas until the loop is unlocked. This frequency f4 gives the lower end of the lock range. {2 — £4).Compare it with the calculated value of + 7.8fo/12. 6. The lock range A Also the capture range is Afe = (13 ~f1).Compare it with the calculated value of capture range. RESULT: ‘Thus the PLL circuit is constructed and its Characteristics were determined.Viva Questions 1. What is phase locked loop? tis a circuit which provides frequercy selective tuning and filtering without coils ot inductors. 2. List the components of the block diagram of PLL. a) Phase detector b) Low pass filter ¢) Emor amplifier 4) Voltage controlled Oscillator 3. What is voltage controlled oscillator? 4. Oscillator circuit in which the frequency of oscillations can be controlled by an externally applied voltage 5. Define Lock-in range. a) The range of frequencies over which PLL can maintain lock with the incoming signal, 6. Define capture range. )_ The range of frequencies over which PLL can acquire lock with the input signal, 7. What are the applications of PLL? a) FM b) Signal generation ©) Frequency shift keying 4) Frequency multipliers 8. What are the 3 stages of PLL characteris a) Free running b) Capture ©) LockingExp no. 17 Analog to digital converters (COUNTER RAMP TYPE AND FLASH TYPE) 1. COUNTER RAMP TYPE ADC AIM: To study and verify counter ramp type analog to digital converter. APPARATUS REQUIRED: 1, DC voltage source 2. Signal generator 3. Breadboard 4.CRO 5. Connecting wires 6. IC's and resistors THEORY: The process of converting an analog signal into its equivalent digital signals is called analog to digital conversion. Circuit diagram of the counter ramp Analog to Digital converter is shown below. Basically, a comparator opens a gate for period of time and a counter counts the number of pulses flowing through the gate, comparator keeps the gate open until the analogue equivalent of the digital output of the counter ized. equals the input voltage that to be d For every sampling interval the DAC output follows a ramp so that itis called as digital ramp type ADC This ramp wave form looks like a staircase for every sampling time. Therefore, itis also called Staircase Approximation Type ADC A 4—bit binary counter using IC 7493 is used to count the pulses. An op-amp with R-2R ladder network Vj > Va, where V; is the input to be is used as DAC. Comparator output provides high output as long digitized and V, is the analogue equivalent of the instantaneous digital output. When V; < Vj, gate closes and binary counter does not receive pulses. CIRCUIT DIAGRAM:PROCEDURE: 1. Set up partial circuit including 1C 7493, R-2R network and op-amp only. Apply 1 KHz elock pulse at pin number 14 of IC 7493 and observe the output of op-amp. 2. Ifstaircase waveform is obtained complete the circuit and apply SV de at V; and observe the output 3. Vary V; from 0 to SV and note the corresponding digital read cut at Q3(2Qs Qo 4, Apply a 100H2 sine wave in place of SV at V; and observe the waveform. Take care that the sine wave is clamped up by turing the offset knob of the function generator. OBSERVATIONS: ‘Analog input Digital input L V; (volts) Qs @2 Q1 Qo DESIGN: Use a 1KQ resistor to tie up the output of 311 to +SV, being an open collector IC. Use R= 10KQ and 2R = 22KO for R-2R ladder network. MODEL GRAPH: “a os Af ¥, fi |, 1 Hnpas and output wavetorms she 1) Input ane output waveforms when input isa de voltage input isa sinusoidal voltae | Figure 1.105. Input and output waveforms of counter ramp ADC. RESULT: | The counter ramp type analog to digital converter was studied, implemented and verified s u ooa > Ti A oo 4 3 , 3 eG oof ‘ F 1 % te ts ts ry r) °° 7 eo *” 2ehb22 : q J f i i d dQilel? SE EIIE OOo Tes HL. FLASH TYPE ADC AIM: To study and verify fash type analog to digital converter APPARATUS REQUIRED: 1. DC voltage source 2. Signal generator 3. Breadboard 4. CRO 5. Connecting wires 6.1C’s and resistors, THEORY: Flash Type ADC is based on the principle of comparing analog input voltage with a set of reference voltages. To convert the analog input voltage into a digital signal of n-bit output, (2n~ 1) comparators are required. The three op-amps are used as comparators. The non-inverting inputs of all the three comparators are connected to the analog input voltage. The inverting terminals are connected to a set of reference voltages (V), 2V) and (3V) respectively which are obtained using a resistive divider network and power supply +V (10 V) The output of the comparator is in positive saturation(j.e. logic 1), when voltage at non-inverting terminal is greater than voltage at inverting terminal and is in negative saturation otherwise For a 3 comparator flash type ADC: Analoginput | Comparator Outputs Digital output | Conditions |G | Gz | GB | Bs v | eats te OH LO o 0] 0 [osm ea] vow eZ] 1} 0 o 0 1 a 7 | [2 Nlifa]o a] o a 3 | | i via] rata 7 Consider first condition, where analog input voltage VA is less than (V/4). In this case, the voltage at the non-inverting terminals of all the three comparators is less than the respective voltages at inverting terminals and hence the comparator outputs are C1C2C3 = 000. This comparator outputs are applied to the further coding circuit to get the digital outputs as B1B0 = 00 Similarly the digital outputs are calculated for other three conditions also.CIRCUIT DIAGRAM: | — I Dieiatounnu Flash ADC Analog iP b> Resistor Encoder Ladder 4 Comparators — PROCEDURE: 1. Construct the cir ‘cuit as shown in circuit diagram. 2. Verify the Digital O/P for different analog voltages. RESULT: ‘The flash type analog to digital converter was studied, implemented and verified EEEBBEVISILIIET LL ILL LISI IIMAExp. No. 18 D/A Converter AIM: To study the operation of i) R-2R DAC ii) Weighted Resistor DAC THEORY: In weighted resistor type DAC, op-amp is used to produce a weighted sum of digital inputs Where weights are produced to weights of bit positions of inputs. Each input is amplified by a factor equal to ratio of feed back resistance to input resistance to which it is connected. Voor = -Re IR (Ds +1/2 Dot % Di+1/8Do) ‘The R-2R ladder type DAC uses resistor of only two values R and2R.The inputs to resistor network may be applied through digitally connected switches or from output pins of a RoR counter. The analogue output will be maximum, when all inputs are of logic high. (1/2. Ds+1/4D2+1/8D1+1/16Do) In a3 input ADC, if the analog signal exceeds the reference signal, comparator turns on, [fall comparators are off, analog input will be between 0 and V/4.1f C1 is high and C2 is ow input will be between V/4 andV/2.If C1 andC2 are high and C3 is low input will be between 3V/4 and V. CIRCUIT DIAGRAM (R-2R ladder type): Vecombinations Si i. | 3. Plot the digital input versus the analog output voltage using AD kit centage resolution, 4 Calculate the maximum Fneaity err and accuracy. Syecify the pe OBSERVATIONS: ee Ven Vorac MODEL GRAPH: Deans aminViva Questions 1. List all the types of DAC. a) Weighted resistor b) R-2R ladder ¢) Inverted R-2R ladder. What is the advantage of R-2R ladder over weighted resistor? In weighted resistor, for higher order conversion the values of resistors become very high which is overcome in R-2R ladder which has only R and 2R values of resistors, 3. List the various types of ADC. Direct type a) Flash type b) Counter ©) Successive Approximation Register 4) Tracking 4. Define resolution. Smallest change in voltage which may be produced at output of the converter. 5. List the specifications of DAC and ADC. a) Resolution b) Linearity c) Accuracy 4) Monotonicity ©) Settling time 1) Stability 6. State the applications of DAC and ADC. a) Digital signal processing b) Communication circuits