IMPORTANT TYPES OF COMBINATIONAL LOGIC CIRCUITS

Decoder 1. Defined as a circuit which translates an n-bit input codeword into a larger m bit output word, where m 2 n . 2. Useful for making selections. For simple decoders, the m bit output word consists of one active (selected) bit, and m-1 inactive bits. n select lines determine which output is selected. 3. Architecture consists of an array of m ANDing elements (active-high outputs use AND gates; active-low outputs use NAND gates) 4. For simple decoders, the outputs are minterms of the input select line variables. 5. The enable signal E must be in the active state to enable the decoder. 6. Simple decoders may also be employed as a SOP Boolean function generator of the n select lines. Sum desired minterms by attaching an ORing element to the corresponding decoder outputs (each output line contributes one minterm.) Multiplexer (MUX) 1. Defined as a circuit which connects one of 2 n input data lines to one output line. 2. The data source selected for connection is determined by a set of n input select lines. 3. Architecture consists of a decoder plus an ORing element. 4. Data lines Di are ANDed with decoder minterms to provide selection of data sources. 5. The enable signal E (an active-low input) is provided for activation. 6. Demonstration of multiplexing action as provided by a mechanical switch. 7. May also be employed as a SOP Boolean function generator of the input select lines (the data inputs specify the truth table values.)

Notes:

Active-high outputs are 1 when active; active-low outputs are 0 when active.

Encoder 1. Defined as a circuit which translates an n bit dataword into a smaller m-bit codeword, where n 2m. 2. Used to do bit compression. 3. Architecture consists of a linear array of m ORing elements. Demultiplexer (DeMUX) 1. Defined as a circuit which connects one input data line to one of 2 n output lines. 2. The output line selected for connection is determined by a set of n output select lines. 3. Demonstration of demultiplexing action as provided by a mechanical switch. 4. A DeMUX circuit can be realized from a decoder circuit by utilizing the decoder enable input line E as the DeMUX data input line. Read-Only Memory (ROM) 1. Programmable truth table 2. n-bit address input (selects a row) 3. m-bit data output (typically m = 8, for one row) 4. Capacity: C 2 n x m (bit contents of truth table) ROM Organization and Type 1. Decoder (selects a word) 2. Encoder array (encodes or stores the word) a. Diode-fuse array computer.howstuffworks.com/rom3.htm b. MOS transistor-fuse array c. Double gate MOS transistor array 3. Historically 5 kinds of ROM implementations. a. ROM (mask) b. PROM (programmable ROM): c. EPROM (erasable-programmable ROM): d. EEPROM (electrically-erasable PROM): e. Flash (fast block-based EEPROM) ROM Transistor Implementations Three examples: 1. PROM a. Decoder built from NMOS array. b. Encoder uses transistor-fuse array. Fuses are altered when ROM is programmed i. A intact fuse represents a 0 ii. A blown fuse represents a 1.

Notice that decoder circuit is used in every important CLC except the encoder.

2. EPROM a. PROM transistor structure b. Double-gate implementation computer.howstuffworks.com/rom4.htm 3. Flash memories: from wikipedia.com a. Double-gate implementation b. NOR flash (like EPROM, can access individual bytes) c. NAND flash (physically smaller, but can access only blocks of bytes). Current technology used by portable music players and cameras d. Secure Digital (SD) Cards en.wikipedia.org/wiki/Secure_digital i. SD (up to 2 GB) ii. SDHC (4GB to 32 GB) iii. SDXC (>32 GB) Programmable Logic Devices (PLDs) 1. Consists an AND-array having n input variables. There are p AND gates (product terms) in each AND array. A PLD will have m AND arrays. 2. Each product term in the AND-array can connect to 2*n input lines. The array then has size p x 2*n. 3. The connections between the inputs and the AND array are represented by dots (or xs). No dot (or x) implies no connection. The dots are placed during the process of downloading a data bit stream into the PLD using special hardware. 4. Xilinx XCR3064XL complex XPA3 PLD (CPLD) structure. Consists of a number of interconnected PLDs (also called function blocks), each having 20 inputs (n = 20) and 8 macrocells (m = 8 outputs). There are 5 product terms (p = 5), per macrocell. 5. The XCR3064XL has 6 PLDs, each PLD having 8 macrocells. Each PLD AND array has 5 x 8 = 40 product terms.

SEQUENTIAL LOGIC CIRCUITS Notes:

SLC defined: logic circuits whose outputs depend upon state. Random Access Memory (RAM) 1. Rewritable truth table of cells a. Read data (read 1 word of state from table) b. Write data (write 1 word of state to table) 2. n-bit address input (selects a word) 3. m-bit data input/output determines word length: a. m = 8 bits (1 byte) b. m = 16 bits (2 bytes) c. m = 32 bits (4 bytes) d. m = 64 bits (8 bytes) e. m = 128 bits (16 bytes) RAM Organization and Type 1. Addressing (selecting a word). a. Straight n-bit decoding. n physical address bits with array that has width m and decoder selects m-bit word. Address size = n. b. Row decoders and column MUX. nr bits for row selection of large array, and reuse nc nr bits for column decoding (via MUX) to select a word from that row. Address size: n = nr + nc c. Bank organization. Address includes 1 or more bank lines for switching between memory banks in chip. Address size: n = nr + nc + nb 2. Storage cell array technology a. Static (no refresh; constructed from gates) b. Dynamic (requires refreshing by CPU) computer.howstuffworks.com/ram.htm c. Synchronous Dynamic (SD) (self-refreshing) d. Double Data Rate (DDR) SD (faster) 3. Refreshing cycle. Uses row and column decoders to select cells for refresh computer.howstuffworks.com/ram1.htm 4. Depending upon cell type, we have a. SRAM (Used for registers, and caches) b. DRAM (older memories) c. SDRAM (current memories) d. DDR SDRAM (latest memories) 5. Memory modules: computer.howstuffworks.com/ram4.htm a. SIMM (single in-line) b. DIMM (dual in-line) c. SODIMM (small outline dual in-line)

Memory capacities can be expressed in bits C 2n x m (b) or, if m = 8, in Bytes C 2n (B)

Putting it all Together: Apple iPhone 1. Mobile Communication Device a. Cell phone (voice/texting) b. iPod (music/video) c. Internet Browser (web/email/facebook/twitter) 2. iPhone Block Diagram www.iphonekiller.com/iphone-4-block-diagram/ a. Samsung A4 Processor b. USB & Audio Ports c. 2x256 MB DDR SDRAM d. NOR Pseudo SRAM e. 16/32/64 GB NAND Flash f. Cell phone Transceiver & Power Amps g. GPS h. Accelerometer/Magnetometer i. 3-axis Gyroscope j. WiFi and Bluetooth Transceiver k. Camera l. Touch Screen 3. Samsung A4 System on a Chip (SoC) S5PC100 a. Processor ARM Cortex A8 (800 MHz) b. GPU PowerVR SGX 535 Shader Engine c. 512 MB DDR SDRAM 4. Processor Details www.arm.com/products/CPUs/ a. Dual instruction issue, in order. b. 13 stage pipeline architecture, major steps are i. iFetch ii. iDecode iii. iExecute iv. Load/Store c. L1 cache 32KB instructions/32KB data d. L2 cache (640 KB) e. Neon Unit (128 bit SIMD for multimedia) 5. Software Applications (Apps) Writing an app tutorial: servin.com/iphone Look at one bit now: Simple Latch Circuit 1. The latch performs the simplest kind of binary information storage. It is employed in some form in virtually all memory element circuits. 2. Circuitry consists of two cross-coupled NAND (or NOR) gates, with outputs (Q),fed back to inputs (S, R). Inputs are active-low. 3. Latch state is specified by the latch outputs; (Q (Q

Computing Comparison: iPhone 3GS (2009) A3 = ARM Cortex A8 (600 MHz) PowerVR SGX 520 GPU 256 MB RAM iPhone 4 & iPad1 (2010) A4 = ARM Cortex A8 (800MHz/1GHz iPad) PowerVR SGX 535 GPU 512 MB RAM HTC Droid (2010) Qualcomm Scorpion (1 GHz) (with ARMv7 instruction set) Adrino 200 GPU 512 MB RAM iPad2 (2011) A5 = ARM Cortex A9 (1 GHz) (dual core) PowerVR SGX 543 (dual core) 512 MB RAM

1, Q 0 Q
,

0 ) indicates the latch is Set, 1 ) indicates the latch is Reset.

4. Latch mode of operation is specified by the latch inputs. Allowable modes include the No Change, Set and Reset modes. 5. Latch operation shall be demonstrated by use of truth table and timing diagrams. Data Latch with Enable (Used in SRAM) 1. Circuitry consists of a simple latch plus additional logic which is under the control of an enable signal E and input D. The D input is active-high. 2. Mode of operation is specified by the input D, and the enable as follows: when E = LOW, mode = No Change (this puts the latch to sleep); when E = HIGH, mode = Set or Reset, as determined by D. 3. The enable input forms the basis of a rudimentary clock signal, which shall be examined more closely in the next section

FLIP-FLOPS AND CLOCKS

Flip-Flop defined: A synchronous SLC which stores one bit of binary information under the control of a set of data input signals and a clock.

Notes:

Properties of Clocks (A general clock waveform will be presented and the following points should be noted.) 1. Clock outputs yield uniform rectangular waveforms when plotted against time. 2. T = clock period = time between consecutive clock waveform rising (or falling) edges, expressed in units of seconds.

3. f c = clock frequency = number of complete clock oscillations (cycles) per second of time, expressed in Hertz or cycles per second (Hz=cycles/sec), where

1 T

Importance of Clocks 1. Up part defines day time, when flip-flops are active, and respond to inputs. 2. Down part defines night time, when flipflops are sleeping, and are not responsive (put in the no change mode). 3. Flip-flop input signals (i.e. bread for breakfast) must come at night to be responded to. Flip-Flop Notation and Characteristics (A general flip-flop circuit will be presented and the following points should be noted.) 1. Q n Q is the stable PS Q value when the CLOCK is LOW before the nth+1 clock pulse. Occurs during night time. 2. Qn 1 Q is the stable NS value when the CLOCK is LOW after the nth+1 clock pulse, i.e. the Q value tommorrow night. Qn 1 is the PS to NS Q change when 3. Qn the CLOCK is HIGH during the nth+1 clock pulse. This occurs during the daytime. 4. F/F data inputs (which control state Qn 1 must arrive before the changes) Qn nth+1 clock pulse and remain stable all day while the CLOCK is HIGH. Edge-Triggered D Flip-Flop (D F/F) 1. Allows a flip-flop to load its next D input only coincident with a clock-pulse edge; subsequent input changes are locked out (and do not effect the output) until the next corresponding clock edge. 2. Circuitry consists of two latches (a master and a slave latch), using 8 gates. With some optimization, circuitry can be reduced to 6 gates, used by the commercial version. 3. F/F state is specified by the latch outputs; Qn 1 ) are initiated on state changes ( Qn the rising edge of the clock. 4. Both positive (rising) and negative-edge (falling) triggering may be implemented. 5. F/F mode of operation is similar to that of the D-Latch: when CLOCK = LOW, mode = No Change; when CLOCK = HIGH, mode = Set or Reset, as determined by D. For positive edge triggered case, when CLOCK

= HIGH, the D input is enabled; the master latch is either set, reset, toggled, or not changed. When CLOCK = LOW, the D input is disabled and the output of the master latch is gated into the slave latch. 6. D F/F architecture described above is often augmented by an asynchronous S (or PRE) and R (or CLR) input overrides on the slave latch. Edge-Triggered Jack/Kill Flip-Flop (JK F/F) 1. Like D F/F, except with 2 inputs J and K. 2. There are four modes of operation: No Change, Set, Reset, or Toggle, as specified by the J and K inputs.

SYNCHRONOUS SEQUENTIAL CIRCUIT ANALYSIS AND DESIGN

General SLC Block Diagram 1. The Present State (PS) of the SLC is defined to be the output bit pattern of the MEMORY ELEMENTS (a register) at the prescribed observation time. 2. The Next State (NS) of the SLC is the future state of the MEMORY ELEMENTS, and is formed by the INPUT LOGIC BLOCK, which utilizes the SLC INPUTS as well as the SLC Present State. 3. The OUTPUTS of the SLC are determined by the OUTPUT LOGIC BLOCK, and are dependent upon the SLC Present State and INPUTS. SLC Classes 1. Class A (MEALY) circuit: OUTPUTS are a function of the PS and INPUTS, e.g.,

Notes:

f( X, Y) .

2. Class B (MOORE) circuit: OUTPUTS are a function of only the PS, e.g., Z f( Y) . 3. Class C circuit: OUTPUTS are equal to the PS, e.g., Z Y.

SLC Variable Notation 1. X = single input variable or vector of input variables (X1, X2, X3, ...) . 2. Y = single state variable (representing flipflop output Q Y ) or vector of state variables (Y1, Y2, Y3, ...) . 1. Z = single output variable or vector of output variables (Z1, Z2, Z3, ...) . 2. Yn = PS, Yn 1 = NS The State Diagram (SD) Shows the state to state transitions of a SLC 1. Components: a. Bubbles: represent the SLC states labeled with alphabetic letters (a, b, c, etc.) or with state codes (000, 001, 010,...) b. Arrows indicate allowable state transitions (present to next.) Arrows specify the transition input conditions and resulting outputs. 2. Types: a. Mealy: arrows are labeled with code X/Z b. Moore: arrows are labeled with X only; bubbles are labeled with code Y/Z. Flip-Flop State Diagrams 1. D flip-flops 2. JK flip-flops The State Table (ST) A tabulation of NS and outputs verses PS and inputs of a SD in truth table fashion. 1. State Table format: PS In | NS Out Yn X | Yn+1 Z 2. Construction: Examine SD: for every Yn bubble, record Yn+1 and output Z indicated by arrow X. 3. There is a ST row for every SD state bubble.

State Trace A timing diagram which lists states and outputs for a given sequence of input values: 1. Trace format Similar to timing diagram, where X is given and Y and Z need to be filled in: X: X1 X2 X3 (sequence of inputs Xn) Y: Y1 Y2 Y3.... (sequence of states Yn) Z: Z1 Z2 Z3.... (sequence of outputs Zn) 2. Construction: Start with n = 1 (X1 and Y1 are given): a. Examine PS Yn and input Xn b. Look up NS Yn+1 and Zn in SD c. Write Yn+1 and Zn in trace d. n = n + 1, Go to step a Synchronous SLC Design Procedure (This procedure is useful for designing SLCs, such as required in the ECE 250 Laboratory. 1. Given a set of specifications for a SLC, identify the inputs and outputs and draw a block diagram. (You may at this point be able to observe if the specifications stipulate a Class A, B, or C SLC design.) Also, formulate a state diagram that describes the functionality of the SLC according to the set of design specifications. 2. Construct a state table based on the information obtained in the state diagram of step (1), showing PS variables Y Yn and inputs X verses NS variables Yn 1 and outputs Z f( X, Y) . 3. Draw the next state maps (one for each and OUTPUT K-maps (one for each Z ) based upon the state table of step (2). 4. If JK F/Fs are to be employed, transform the next state maps into JK maps for each state variable Y . If D F/Fs are to be used, the D maps are the same as the next state maps. 5. Read the maps of steps (3, 4) to obtain SOP expressions for the J, K, or D F/F input variables as well as Z. Translate these equations into appropriate circuits

Yn

1)

Synchronous SLC Analysis Steps (This procedure is useful for creating a state diagram for an already existing SLC, whose behavior needs to be analyzed.) 1. Examine the given SLC and determine the logic equation for each F/F input (J, K, or D) and circuit output Z. 2. Complete a K-map for the J, K, D, and Z variables. If JK F/Fs are used, consolidate the J and K maps into next state maps. If D F/Fs are used, the D maps are the next state maps. The Z variables generate the OUTPUT maps. 3. Transfer the contents of the next state maps and OUTPUT maps of step (2) into a single state table. 4. Construct a state diagram from the state table of step (3). 5. If an input sequence X is given, complete a timing diagram for X, Y, Z and CLOCK.

SOME IMPORTANT TYPES OF SEQUENTIAL LOGIC CIRCUITS

Register circuits defined: those logic circuits which deal with the storage and transfer of multi-bit data. Data Transfer Modes 1. 2. 3. 4. PARALLEL-IN/PARALLEL-OUT (PIPO) SERIAL-IN/SERIAL-OUT (SISO) PARALLEL-IN/SERIAL-OUT (PISO) SERIAL-IN/PARALLEL-OUT (SIPO)

Notes:

The most significant bit (MSB) of a register is usually reserved for the sign bit..

Data Latch Register 1. Defined as a register circuit capable of performing only PIPO data transfers. 2. Typical architecture consists of a linear array of D flip-flops driven by a common clock line. Shift Register 1. Defined as any register circuit capable of performing SISO data transfers. 2. Typical architecture consists of a linear array of D or JK flip-flop with inputs and outputs of adjacent flip-flops tied together, driven by a common clock line. 3. Multi-mode shift registers are augmented by additional logic circuitry to support SIPO, PISO, or even PIPO data transfers. 4. Bidirectional shift registers contain additional logic circuitry to support left or right data shifts. 5. A bidirectional shift register capable of supporting additional modesof operation is known as a multifunction register.

Counter circuit defined: those logic circuits which deal with the generation and storage of multi-bit sequential codes. Counter Circuit Characteristics 1. Single or multi-mode operation (up-down, for example) 2. Synchronous or asynchronous operation 3. Outputs provide frequency division of input clock signal 4. Zero reset for termination of count sequence Single-Mode Synchronous Counter 1. Defined as a synchronous counter circuit which counts in one direction. 2. Typical architecture (for binary code sequence generator) consists of a linear array of JK or D flip-flops, driven by a common clock line, configured either in the toggle or no change modes as determined by additional decoding circuitry attached to the Q outputs. 3. Count outputs are guaranteed stable for a very short time following application of each clock pulse. Ripple Counter 1. Defined as an asynchronous counter circuit because only the LSB flip-flop gets the clock signal. 2. Typical architecture consists of a linear array of JK flip-flops, configured in toggle mode, with the clock inputs and outputs of adjacent flip-flops tied together. 3. Ripple effect: count outputs are not guaranteed stable until the most significant F/F receives its clock signal.