EECS 150 - Components and Design Techniques for Digital Systems

Lec 15 Storage: Regs, SRAM, ROM

David Culler
Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150
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Review: Timing
All gates have delays
RC delay in driving the output

Wires are distributed RCs

Delays goes with the square of the length

Source circuits determines strength

Serial vs parallel

Delays in combinational logic determine by

Input delay Path length Delay of each gate along the path Worst case over all possible input-output paths

Setup and CLK-Q determined by the two latches in flipflop Clock cycle : Tcycle TCL+Tsetup+TclkQ + worst case skew

Delays can introduce glitches in combinational logic

Outline
Memory concepts Register Files SRAM SRAM Access Multiported Memories
FIFOS

ROM, EPROM, FLASH Relationship to Comb. Logic

Memory Basics
Uses:
Whenever a large collection of state elements is required. data & program storage general purpose registers buffering table lookups CL implementation

Example RAM: Register file from microprocessor

clk

Types:
RAM - random access memory ROM - read only memory EPROM, FLASH - electrically programmable read only memory

regid = register identifier (address of word in memory) sizeof(regid) = log2(# of reg) WE = write enable

Definitions
Memory Interfaces for Accessing Data

Asynchronous (unclocked):
A change in the address results in data appearing

Synchronous (clocked):
A change in address, followed by an edge on CLK results in data appearing or write operation occurring.

A common arrangement is to have synchronous write operations and asynchronous read operations.

Volatile:
Looses its state when the power goes off.

Nonvolatile:
Retains it state when power goes off.

Register File Internals

For read operations, functionally the regfile is equivalent to a 2-D array of flip-flops with tristate outputs on each
MUX, but distributed Unary control

Cell with added write logic:

These circuits are just functional abstractions of the actual circuits used.

How do we go from "regid" to "SEL"?

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Regid (address) Decoding

The function of the address decoder is to generate a one-hot code word from the address. Binary -> unary Simplied DEMUX The output is use for row selection. Many different circuits exist for this function. A simple one is shown. Where have you seen this before?

Accessing Register Files

Read: output is a combinational function of the address input
Change address, see data from a different word on the output Regardless of clock

Write is synchronous
If enabled, input data is written to selected word on the clock edge

Often multi-ported (more on that later)

clk addr dout din addr X R[X] addr Y R[Y] val
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val

WE

Basic Memory Subsystem Block Diagram

Word Line Address Decoder Memory cell
2n word lines

n Address Bits

m Bit Lines

what happens if n and/or m is very large?

RAM/ROM naming convention:

32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words
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Memory Components Types:

Volatile:
Random Access Memory (RAM): SRAM "static" DRAM "dynamic"

Non-volatile:
Read Only Memory (ROM): Mask ROM "mask programmable" EPROM "electrically programmable" EEPROM "erasable electrically programmable" FLASH memory - similar to EEPROM with programmer integrated on chip

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Read Only Memory (ROM)

Simplified form of memory. No write operation needed. Functional Equivalence:
Connections to Vdd used to store a logic 1, connections to GND for storing logic 0.

address decoder

bit-cell array

Full tri-state buffers are not needed at each cell point. In practice, single transistors are used to implement zero cells. Logic ones are derived through precharging or bit-line pullup transistor.

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Static RAM Cell

6-Transistor SRAM Cell
0 1

word (row select)

Read:

bit

bit

1. Select row 2. Cell pulls one line low and one high 3. Sense output on bit and bit

Write:
1. Drive bit lines (e.g, bit=1, bit=0) 2. Select row

Why does this work? When one bit-line is low, it will force output high; that will set new state 12

Typical SRAM Organization: 16-word x 4-bit

Din 3 Wr Driver Din 2 Wr Driver Din 1 Wr Driver Din 0 Wr Driver WrEn

+
Word 0

SRAM Cell

SRAM Cell

SRAM Cell

SRAM Cell

A0 A1

Address Decoder

SRAM Cell

SRAM Cell

SRAM Cell

SRAM Cell

Word 1

A2
A3

:
SRAM Cell - Sense Amp +

:
SRAM Cell - Sense Amp +

:
SRAM Cell - Sense Amp +

:
SRAM Cell - Sense Amp +
Word 15

Dout 3

Dout 2

Dout 1

Dout 0

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Simplified SRAM timing diagram

Read: Valid address, then Chip Select Access Time: address good to data valid
even if not visible on out

Cycle Time: min between subsequent mem operations Write: Valid address and data with WE_l, then CS
Address must be stable a setup time before WE and CS go low And hold time after one goes high

When do you drive, sample, or Z the data bus?

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What happens when # bits gets large

Big slow decoder Bit lines very log
Large distributed RC load

Treat output as differential signal, rather than rail-to-rail logic

Sense amps on puts Can precharge both bit lines high, so cell only has to pull one low

Log n bit address

n bits

==> Make it shorter and wider

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Inside a Tall-Thin RAM is a short-fat RAM

n = k x m bits Log k bit address

Sense amps

mux Log m bit

address 1 data bit

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Column MUX
Controls physical aspect ratio
Important for physical layout and to control delay on wires.

In DRAM, allows time-multiplexing of chip address pins (later)

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Administration and Announcements

Reading 10.4.1, Xilinx Block RAM datasheet HW 6 (two problems) due Friday Midterm Results
Max: 97, Mean: 67, Median 69 about 10 pt low due to length will weight later one a little more You will see the later problems again make sure you know it
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Midterm1 Grade Distribution

Project adjustments
Number of Students

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20

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0 <=40% <=50% <=60% <=70% Percantage <=80% <=90% >90%

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Revised: Schedule of checkpoints

CP1: N64 interface (this week) extend a week CP2: Digital video encoder (week 8) CP3: SDRAM controller (two parts, week 9-10) CP4: IEEE 802.15.4 (cc2420) interface (wk 11-12)
unless we bail out to ethernet Overlaps with midterm II
Make optional

Project CP: game engine (wk 13-14) Endgame

11/29 early checkoff 12/6 final checkoff 12/10 project report due 12/15 midterm III
Check out the web page

Start earlier and have a week before final

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Logic Diagram of a Typical SRAM

A
N

WE_L

OE_L

2 N words x M bit SRAM

M

Write Enable is usually active low (WE_L) Din and Dout are combined to save pins: A new control signal, Output Enable (OE_L)
WE_L is asserted (Low), OE_L is unasserted (High) D serves as the data input pin WE_L is unasserted (High), OE_L is asserted (Low) D is the data output pin Neither WE_L and OE_L are asserted? or chipSelect (CS) + WE Chip is disconneted Never both asserted! 20

Cascading Memory Modules (or chips)

Example: assemble of 256 x 8 ROM using 256 x 4 modules:

example: 1K x * ROM using 256 x 4 modules:

each module has tri-state outputs:

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Typical SRAM Timing

A
N

WE_L OE_L

2 N words x M bit SRAM

M

OE determines direction Hi = Write, Lo = Read Writes are dangerous! Be careful! Double signaling: OE Hi, WE Lo
D

Write Timing:
D A OE_L WE_L Write Hold Time Write Setup Time Data In Write Address

Read Timing:
High Z
Junk Read Address Read Address Data Out Data Out

Read Access Time

Read Access Time

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Memory Blocks in FPGAs

LUTs can double as small RAM blocks:
4-LUT is really a 16x1 memory. Normally we think of the contents being written from the configuration bit stream, but Virtex architecture (and others) allow bits of LUT to be written and read from the general interconnect structure. achieves 16x density advantage over using CLB flip-flops. Furthermore, the two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16x1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register of adjustable length.

Newer FPGA families include larger onchip RAM blocks (usually dual ported):
Called block selectRAMs in Xilinx Virtex series 4k bits each 23

Synchronous SRAM

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Verilog for Virtex LUT RAM

module ram16x1(q, a, d, we, clk); output q; input d; input [3:0] a; input clk, we; reg mem [15:0]; always @(posedge clk) begin if(we) mem[a] <= d; end assign q = mem[a]; endmodule

Note: synchronous write and asynchronous read.

Deeper and/or wider RAMs can be specified and the synthesis tool will do the job of wiring together multiple LUTs. How does the synthesis tool choose to implement your RAM as a collection of LUTs or as block RAMs?
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Virtex Block RAMs

Each block SelectRAM (block RAM) is a fully synchronous (synchronous write and read) dualported (true dual port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. CLKA and CLKB can be independent, providing an easy way to cross clock boundaries. Around 160 of these on the 2000E. Multiples can be combined to implement, wider or deeper memories.
See chapter 8 of Synplify reference manual on how to write Verilog for implied Block RAMs. Or instead, explicitly instantiate as primitive (project checkpoint will use this method).
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WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] DOA[#:0]

WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]

DOB[#:0]

Multi-ported Memory
Motivation:
Consider CPU core register file: 1 read or write per cycle limits processor performance. Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile. Common arrangement in pipelined CPUs is 2 read ports and 1 write port.

dataa sela selb selc

Regfile

datab

datac

What do we need in the project?

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Dual-ported Memory Internals

Add decoder, another set of read/write logic, bits lines, word lines:
Example cell: SRAM
WL2 WL1 deca decb

cell array
b2
r/w logic r/w logic

b1

b1

b2

address ports

data ports

Repeat everything but crosscoupled inverters. This scheme extends up to a couple more ports, then need to add additional transistors.

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First-in-first-out (FIFO) Memory

Used to implement queues.
These find common use in computers and communication circuits. Generally, used for rate matching data producer and consumer:
stating state

Producer can perform many writes without consumer performing any reads (or vice versa). However, because of finite buffer size, on average, need equal number of reads and writes. Typical uses:
interfacing I/O devices. Example network interface. Data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized. Example: Audio output. Processor produces output samples in bursts (during process swap-in time). Audio DAC clocks it out at constant sample rate.
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after write

after read

FIFO Interfaces
DIN
WE RST CLK

Address pointers are used internally to keep next write position and next read position into a dual-port memory.
write ptr read ptr

FULL
HALF FULL EMPTY RE

FIFO

DOUT

If pointers equal after write FULL:

After write or read operation, FULL and EMPTY indicate status of buffer. Used by external logic to control own reading from or writing to the buffer. FIFO resets to EMPTY state. HALF FULL (or other indicator of partial fullness) is optional.

write ptr

read ptr

If pointers equal after read EMPTY:

write ptr read ptr

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Non-volatile Memory
Used to hold fixed code (ex. BIOS), tables of data (ex. FSM next state/output logic), slowly changing values that persist over power off (date/time)

Mask ROM
Used with logic circuits for tables etc. Contents fixed at IC fab time (truly write once!)

EPROM (erasable programmable) & FLASH

requires special IC process (floating gate technology)

writing is slower than RAM. EPROM uses special programming system to provide special voltages and timing. reading can be made fairly fast. rewriting is very slow. erasure is first required , EPROM - UV light exposure, EEPROM electrically erasable
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FLASH Memory
Electrically erasable In system programmability and erasability (no special system or voltages needed) On-chip circuitry (FSM) and voltage generators to control erasure and programming (writing) Erasure happens in variable sized "sectors" in a flash (16K - 64K Bytes)

See: http://developer.intel.com/design/flash/ for product descriptions, etc.

Compact flash cards are based on this type of memory.
NAND flash Configuration memory, microcontrollers usually NOR flash

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Relationship between Memory and CL

Memory blocks can be (and often are) used to implement combinational logic functions: Examples:
LUTs in FPGAs 1Mbit x 8 EPROM can implement 8 independent functions each of log2(1M)=20 inputs.

The decoder part of a memory block can be considered a minterm generator. The cell array part of a memory block can be considered an OR function over a subset of rows.

The combination gives us a way to implement logic functions directly in sum of products form. Several variations on this theme exist in a set of devices called Programmable logic devices (PLDs)
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A ROM as AND/OR Logic Device

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PLD Summary

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PLA Example

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PAL Example

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Summary
Basic RAM structure
Address decoder to select row of cell array bit, ~bit lines to read & write Sense difference in each bit Column mux

Read/write protocols
Synchronous (reg files, fpga block ram) Asynchronous read, synchronous writes Asynchronous

Multiported RAMs
reg files and fifos

Non-volatile memory
ROM, EPROM, EEPROM, FLASH

Memory as combinational logic Relationship to programmable logic

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