Fractional Capacitor Based SIMO Biquad Filter using CDTA

Ashish Kumar, Debu Patra, Himanshu Singh and Rajeshwari Pandey

Abstract - In this paper, a fractional capacitor it corresponds to the impedance of a

based single input multiple output (SIMO) fractional-order capacitor. The passive
biquadratic filter is designed using Current realization methods for higher-order FOEs
Differencing Transconductance Amplifier require a FOC of order -1 < α < 0.
(CDTA). The realized filter has one input and
three outputs, low-pass (LP), high-pass (HP), Although there has been much progress
and band-pass (BP) responses. It can be utilized towards realizing fractional order capacitors
as current mode (CM), voltage mode (VM),
transadmittance mode (TAM), and
[Approximated Fractional Order Chebyshev
transimpedance mode (TIM) using appropriate Lowpass Filters (hindawi.com)], there are
input choices. The performance of the filter is currently no commercial devices using these
demonstrated through the LTSPICE software processes available to implement these
simulation with the 0.35μm CMOS technology circuits, though their increasing progress
parameters. towards commercialization highlights the need
to research their use in electronic circuits to
Index Terms — Fractional Capacitor, CDTA, take advantage of their unique characteristics
SIMO Biquad Filter, LTSPICE when they do become available. Until
commercial devices with the desired
characteristics become available integer order
I. INTRODUCTION approximations must be used to realize
fractional circuits. Research on hardware
Historically, fractional order calculus has been realization of FOE is still in nascent stage and
largely unexplored in the engineering domain variety of approximations such as Oustaloup
due to its Recursive approximation, Carlson
complex realization. Only with in the last approximation, Matsuda approximation,
twenty years, engineers had been capable of Chareff approximation, Continued Fraction
designing and subsequently taking advantage Expansion (CFE), Modified Oustaloup and El-
of fractional-order calculus potentialities, so Khazali reduced order approximations are
that, nowadays, it's far implemented in lots of available in literature to emulate the behavior
studies areas; from computerized and scientific of FOE specially FC with a through a semi-
applications, to electrical networks [1], to civil infinite RC tree in or by other combinations of
engineering applications [2]. Fractional order RC ladder networks such as cross RC ladder
network, domino ladder etc.
systems allow us to realize real-world systems
and it can be utilized to get more consistent
solutions for various engineering problems.
Fractional order elements (FOE) are gaining
popularity in many areas as they allow us to
Foster-I
investigate design flexibility, which is not
possible in the narrow finite subset of
realization is
conventional integer-order circuits. The
impedance of a FOE can be represented as
Z(s) = Fsα, Where the coefficient F is called
used to
practice and α denotes the exponent of FOE
and is known as the order of the FOE. Here, α
is a fractional number, and it lies in -n to n, n
is an integer. When the value of α is negative,
transform the order
fractional approximations
capacitor (Oustaloup,
obtained from Matsuda and
these integer- CFE) into an RC
order parallel–series
approximations circuit topolog
(Oustaloup, Foster-I
Matsuda and realization is
CFE) into an RC used to
parallel–series transform the
circuit topolog fractional
Foster-I capacitor
realization is obtained from
used to these integer-
transform the order
fractional approximations
capacitor (Oustaloup,
obtained from Matsuda and
these integer-
CFE) into an RC
process the analog signal whereas the digital
filters are also used to process analog signals
after discretization. Since the filters have a

parallel–series wide area of application, and are often used in

signal modulation, demodulation,
amplification, etc. researchers are eager to
circuit topolog improve the performance of filters. Filters
have three key specifications; passband ripple,

Foster-I stopband attenuation, and passband roll-off.

For an optimum design, filters should have
minimum passband ripple as-well-as
realization is maximum roll-off. As the order increases, the
roll-off increases and the passband ripples

used to intensify. It is essential to have a justified

trade-off between the pass-band ripple and
roll-off. However, it is not so easy to control
transform the both of them simultaneously. Therefore, the
concept of fractional calculus is being applied

fractional in filter designing; such filters are known as

fractional-order filters. In the fractional-order
filters, fractance devices (FDs) are used in
capacitor place of conventional capacitors and inductors.
These filters provide an extra degree of

obtained from freedom in system designing, and provide

precise control on pass band ripple, roll-off
and stop band attenuation. It should also be

these integer- noticed that the responses of fractional-order

filters can be altered by varying the order of

order
FDs only; therefore, there is no need to vary
the numerical values of capacitances and
inductances of the fractional-order filters.

approximations The remaining paper proceeds as follows:

Section II discusses the CDTA circuit

(Oustaloup, description. Section III describes Fractional

order capacitor and its realization and Section

Matsuda and
IV moves on to present the non-ideal analysis
of the above FOC. Finally, the results and
simulations of the circuit thus obtained are

CFE) into an RC presented in Section V. The last section VI

gives the conclusion of the paper

parallel–series II. CDTA DESCRIPTION

circuit topology. The current differencing transconductance

amplifier (CDTA) is one of the most versatile
devices of the current mode family and is used
Electronic filters are one of the most popular in analog signal processing in the electronics
and commonly used devices in the area of industry. CDTA was first introduced in the
signal processing. Filters are digital as-well-as year 2003, and since then it has been
analog in nature. Analog filters are used to acknowledged as a versatile current-mode
active building block in designing analog and -gm at X+ and X- terminals respectively,
circuits. It exhibits the ability of electronic which can be changed by external bias current
tuning with the help of its transconductance electronically.
gain (gm). With its current-mode operation
nature, all these advantages make the CDTA a III. FRACTIONAL ORDER CAPACITOR
good choice for realizing the current-mode
filters[3]. The CDTA is free from parasitic From the variety of approximations, the CFE
input capacitances and it can operate in a wide method was selected to model the fractional
frequency range due to its current-mode order capacitors for SPICE simulations.
operation. Approximation using continued fraction
The symbolic representation of CDTA is as expansion (CFE) is a method for evaluation of
depicted in Fig. 1 where the input terminal functions, that frequently converges much
currents are denoted as Ip and In, and the output more rapidly than power series expansions,
terminal currents are denoted as Iz, Ix+ and Ix-. and converges in a much larger domain in the
The terminal relationships can be defined complex plane.
through the subsequent matrix: Collecting eight terms of the CFE yields
an order approximation of the fractional
capacitor that can be physically realized using
Vp 0 0 0 0 Ip the RC ladder network.
Vn = 0 0 0 0 In
Iz 1 -1 0 0 Vx The method is based upon expanding
Ix 0 0 0 ±gm Vz expression (1+x)α , for 0    1 into
continued fraction:

Vp = Vn = 0
Iz = Ip – In
Ix+ = gmVz
Ix- = - gmVz

Using notation proposed in [Khovanskii A.N.:

The application of continued fractions and
their generalizations to problems in
approximation theory, Noordhoff, The
Netherlands, 1963.] , above Eq. may be
written as:

Substituting x = s–1 and considering successive

terms, we obtain approximation with accuracy
The CDTA consists of two stages that are for the 4th order:
current differencing unit (CDU) and dual
output transconductance stage. CDU gives the
difference of applied input currents at p and n
terminals and this difference (Ip - In) is
transmitted to z intermediate terminal. With
the help of an external impedance Z, this (4 + 103 + 352 + 50 + 24) s4
current is converted into voltage. In the second + (- 44 - 203 + 402 + 320 + 384)
stage, the voltage which is generated at s 3
(64 - 1503 + 864) s2 + (- 44
intermediate z terminal is transformed into + 203 + 402 -320+ 384) s + (4 - 103 +
output currents by transconductance gain gm 352 - 50 + 24)
s = (4 - 103 + 352 - 50 + 24) s4
+ (-44 + 203 + 402 - 320 + 384) s3
(64 - 1503 + 864) s2 + (-44 - 203 +
40 2
+320+ 384) s + (4 +103 + 352
+50 + 24)

In general, any nth-order CFE approximation

function represents an impedance function and
may be physically implemented with an RC
ladder network using a partial fraction method.
Thus, a CFE-approximated FOC can be obtained
by using the reciprocal of respective nth-order
function. The realization of a fourth-order Foster-I realization of fractional-order
approximation form for FOC is explained below. capacitor
The impedance function of FOC is obtained by
the reciprocal of (14.3d) as given by 0.5 0.6 0.7 0.8
Order ()
(4 - 103 + 352 - 50 + 24) s4 R1(Ω)
+ (-44 + 203 + 402 - 320 + 384) s3
R2(Ω)
(64 - 1503 + 864) s2 + (-44 - 203 +
40 2
+320+ 384) s + (4 +103 + 352 R3(Ω)
+50 + 24) R4(Ω)
1 = (4 + 103 + 352 + 50 + 24) s4
 R5(Ω)
s + (- 44 - 203 + 402 + 320 + 384)
s3 (64 - 1503 + 864) s2 + (- 44 C2(μF)
+ 20 + 40 -320+ 384) s + (4 - 103 +
3 2
C3(μF)
352 - 50 + 24)
C4(μF)
This impedance function may be realized by C5(μF)
the partial fraction method outlined in [M.V.
Valkenburg, Network Analysis, 3rd edition, FOC realization for  = 0.5, 0.6, 0.7,
Prentice Hall College Div, ISBN 978- 0.8
0136110958, 1974.]. The domino RC ladder
network of Fig. 14.1 is one of the realizations
used widely by researchers to verify the
 FOC Simulation Results:
proposals. The impedance function of Fig. is
given by:

Foster-I realization is used to transform the

fractional capacitor obtained from these
integer-order approximations (CFE) into an
RC parallel–series circuit topology.
 IV. PROPOSED FRACTIONAL
CAPACITOR BASED
MULTIMODE SIMO FILTER
Fig. Fractional Capacitor based Multimode
SIMO ……Biquad Filter
Design Equations of FOF and Critical
Frequencies
A. CM configuration:
The generic FOF transfer function using two
FCs of different orders, represented by α and
β, respectively, can be expressed as

N (s) b2 s + β + b1 s + b0
T (s) = =
D (s) s + β + a1 s + a0

where coefficients b0, b1, b2, a0, a1 are the

constant terms. Various FO responses may be
obtained if coefficients are selected according
to scheme given in Table 2. Considering α = β,
(1) modifies to

N (s) b2 s2 + b1 s + b0
T (s) = =
D (s) s2 + a1 s + a0

The CMOS CDTA based fractional Multimode

SIMO filter has been depicted in Fig. 2. It is
made up of three CDTAs, a grounded resistor,
two grounded fractional capacitors, and a
virtually grounded resistor. The
implementation area of ICs can be B. VM configuration:
reduced by using grounded capacitors. It can
be arranged as CM, VM, TAM, and TIM When Vin is active (Iin = 0), the given topology
configuration by appropriate input signal yields VM configuration. Following VM
selection. transfer functions are obtained after analysing
the given circuit:

V1 = _ (R2/R1) s2

Vin HP Δ

V2 = _ (gm1R2/R1C1) s
 Vin BP Δ Iin LP Δ
V1 = _ gm1gm2R2/R1C1C2

Vin LP Δ E. Critical Frequency

C. TAM configuration:
 
Removing the input current source (I in = 0) in D(s) = [ ω4 + 2a1 ω3 cos π /2
Fig. 2 will result in TAM mode configuration.
Evaluation of this configuration results in the + (a12 + 2a0 cos π) ω2 +
 1/2
following transfer functions: 2a1a0 ω cosπ /2 + a02]
 In general, three critical frequencies [21] are
I1 = _ (gm1R2/R1) s2
used to characterize FOF which are defined
Vin HP Δ below:

I2 = _ (gm1R2/R1) s

ωm: the maximum/minimum frequency point
at which |T (jω)| is maximum/minimum
Vin BP Δ
ωh: the half power frequency point
I3 = _ gm1gm2gm3R2/R1C1C2
ωrp: the right-phase frequency corresponding
Vin LP Δ
to angle = ±π/2
D. TIM configuration:
The proposed topology works in TIM mode [Verma Paper]
when Iin is active (Vin = 0) in Fig. 2. Routine
[Freeborn, T.J.; Elwakil, A.S.; Maundy, B.:
calculations yield the following TIM mode
Approximated fractional-order inverse
transfer functions:
Chebyshev lowpass filters. Circuits Syst. Signal
 Process. 35(6), 1973–1982 (2016)]
V1 = R 2 s2
CCII based KHN fractional order filter |
Iin HP Δ
Request PDF (researchgate.net)

V2 = (gm1R2/C1) s

Iin BP Δ
V3 = gm1gm2R2/C1C2

Filter Passive Theoretical f0 (MHz) Simulated f0 (MHz)

Configuration Components
C1 & C2(μF)  LPF HPF BPF LPF HPF BPF

VM 1 0.5
CM 1 0.5
TIM 1 0.5
TAM 1 0.5
VM 1 0.6
CM 1 0.6
TIM 1 0.6
TAM 1 0.6
VM 1 0.7
CM 1 0.7
TIM 1 0.7
TAM 1 0.7
VM 1 0.8
CM 1 0.8
TIM 1 0.8
TAM 1 0.8

V. Conclusions

Foster-I realization is used to

transform the fractional
capacitor obtained from these
integer-order approximations
(Oustaloup, Matsuda and
CFE) into an RC parallel–series
circuit topology.

REFERENCES

[1] S. V. Puscasu and S. M. Bibic, “Aspects of Fractional Calculus in RLC Circuits,” 2018 International
 Symposium on Fundamentals of Electrical Engineering (ISFEE), 2018.

[2] A. M. Muhittin Evren Aydin, "Applications of fractional calculus in equiaffine geometry:," 2021.

[3] Biolek D., "CDTA-building block for current-mode analog," Krakow, Poland, 2003.

[4]