Why Use Virtual Memory?

Address Translation Page Table Size TLB & Virtual Cache

Virtual Memory

Muhammad Tahir

Lecture 22-23

Electrical Engineering Department

University of Engineering and Technology Lahore
Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Contents

1 Why Use Virtual Memory?

2 Address Translation

3 Page Table Size

4 TLB & Virtual Cache

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Virtual Memory and Its Importance

• Virtual Memory allows to execute a program that may not

reside completely in the main memory (RAM)
• Allows efficient utilization of the available main memory
resources
• Simplifies memory management
• Relieves the programmer from the burden of memory resource
management

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Working of Virtual Memory

• Types of memory space

• Virtual memory space: What the program “sees”
• Physical memory space: Where the program “resides” and
executes from (size of RAM)
• On program startup
• OS copies the program into RAM
• If RAM is not enough, OS stops copying and starts execution
(with partly loaded program in RAM)
• When the program accesses a part not in the RAM, OS gets a
page fault, and OS copies the missing part from disk to RAM

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Working of Virtual Memory Cont’d

• On program startup cont’d

• To copy the missing program page(s) from disk to RAM, OS
may evict parts of the program already in the RAM
• OS copies the evicted parts of the program back to disk

Virtual Address (VA) Address Translation Physical Address (PA)

space Memory
space

PA Page
VA MMU Tables
CPU
Trap Cache
         Data

Data

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Virtual Memory: Logical View

• Virtual vs Physical memory view
Virtual Physical 
Address Address
0 A 0
4K B 4K C
8K C 8K Physical
12K D 12K main Memory
16K A
Virtual Memory 20K
24K B
28K

D Disk

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Address Translation

• The mapping between virtual addresses and physical addresses

is stored in page table
31 12 11 0 Virtual Address
Virtual page number Page offset
(from Processor)
20 12

Address
Translation Translation

11 0 Physical
Physical page number Page offset Address
Physical Address

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Address Translation Cont’d

Page table register

31 12 11 0 Virtual Address
Virtual page number Page offset (from Processor)
20 12

V Physical page number

Page Table

If 0 then page is not

present in memory
11 0
Physical
Physical page number Page offset Address

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Address Translation Cont’d

• Page table is stored in main memory
• It is maintained by the operating system
• Page table entry example

Figure 1: Source: Privileged architecture manual.

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Address Translation Cont’d

31 10
0

Physical Page Number

RSW
D
A
G
U
X
W
R
V

Valid
Readable
Writeable
Executeable
User Mode
Global
Accessed
Dirty
Reserved by Software

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Page Table Size: The Problem

• For every virtual page number there is an entry in the page

table
• One entry per page for the entire virtual address space, even
for pages the program never uses!
• Entry contains: physical page number and page attribute bits,
e.g. presence, protection bits etc.
• Overall size:
Virtual memory size
× size of page table entry
page size

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Page Table Size: The Problem cont’d

• Example
• Virtual memory = 4GB, Page size = 4KB, Size of entry is 4B.
4MB Page table/process
• Some processes may actually be smaller than 4MB but their
page table is 4MB!
• How big would the page table be for a 64-bit machine?

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Page Table Size: The Problem cont’d

• The problem with flat page tables is:

• The page table size is determined by the size of the virtual
memory and not by the actual amount of memory a program
uses
• For 32bit virtual address space, several MBs which in most
cases is larger than the actual application
• For 64bit virtual address space, its too big

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Multi Level Page Table: The Solution

• One way to solve this is via multi-level page tables which

solves these problems
• The overall page table size is ≈ to size of program
• Provides a solution for large virtual addresses

• The reason it works is because of the way large virtual address

spaces actually get partitioned & used by processes

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Multi Level Page Table: The Solution cont’d

• The VA is partitioned into two parts: Page offset & virtual

page number
• Virtual page number is further divided into two parts:
• Outer virtual page number (page table number) : which
part of the large page table will be used – first level page table
• Entry indicates which of the second level page tables to use
• Inner virtual page number (page table offset) : which
specific entry in that portion of the page table will be used –
second level page table
• Entry gives us physical frame number

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

2 Level Page Table: The Solution cont’d

• The VA is partitioned into two parts: Page offset & virtual
page number
Page Table Page Table Page
Number Offset Offset
Virtual
0X0 3FE FB0
Address
8 12 12

V Physical Page Number

1 0x23F1
1 0x23F1 0
0011 0x23F1
0x23F1
1 0x23F1 1
1 00 0x7FFE
11 0 0x7FFE
0x7FFE 2
V Page Table Addreess 0 1 0x7FFE
0 1 0x7FFE
0 0x1003 0000 .
0 0 .
1 0x40000 00 0 .. .
0 0 . ...
0 . . ..
0
. 0x0073. . . .
00 0x0073
1100 0x0073. .
. First- 0 0x0073..
1
0 1 0x0073
. Level 0 1 0x0073
PTBR + 0x0073
0
Page 0 00 0x72FC
0 0x72FC
0
0 Table 0
11 0 0x72FC
0 0x72FC
1 0x2375000 0011 0x72FC
0x72FC
1 0x72FC Second-
0 00
00 0 Level
00 00x00C1
0x00C1 Page
0
255 1 00 0x00C1 Table 4094
11 0 0x00C1
0x00C1
11 0x00C1
0x00C1 4095
10
15

Physical
0x23F1 FB0
Address

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

N Level Page Table: The Solution cont’d

• In multilevel paging all the page tables will be stored in main
memory
• One access for each level needed
• Each page table entry except the last level page table entry
contains base address of the next level page table
Page Table Page Table
Offset Offset Virtual Address

Level 1 Level 2 Level 3 . . . . . . . . . . .  . . .  Level n offset

PTBR +

PTE +

PTE + . . . . . . . . . . .  . . .  +
Physical Page Number offset

PTE
Physical Address

n Level paging system

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Making Address Translation Fast: The TLB

• The memory management unit maintains a buffer (cache
memory) of recently used page table mappings
• This cache is called Translation look-aside buffer (TLB)

Virtual Address 31 12 0
(from Processor) Virtual page number Page offset
12

TLB VD Tag Physical page number

=
=
TLB =
=
Hit =
=
=
=
20
Physical
Address Physical page number Page offset
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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Real Life Example

Virtual Address
(from Processor)
32
31 12 0
Virtual page number Page offset Physical page number Page offset
12 Physical Address
Tag Index
TLB VD Tag Physical page number 31 14 4 20
18 10 2 (word offset)
=
=
TLB =
= Line V D Tag Data (16 byte block)
Hit No.
= 0
= 1
=

. . .

. . .
. . .
=
1022
1023

32 Data

Hit

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Handling Page Faults

Virtual address

TLB access

TLB miss
exception No Yes
TLB hit?

Protection
Page Table
Access Check Access
"Walk"
Denied Permitted
Physical
Page not Page in Address
in Mem Mem Protection Fault No Yes
Page Fault Write?
Update TLB
(OS loads page)
SIGSEGV
Write  Yes
No
Find in Disk Find in mem Try to read access bit
data from on?
cache Write protection
exception Try to write
data to cache

Cache miss No Yes

stall while read Cache hit? Cache miss stall No Cache Yes
block while read block hit?

Deliver data
to the CPU write data into cache, update
the dirty bit, and put the data
and the address into the write
buffer
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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Caches with Virtual Addressing

Virtual Address (VA) Address Translation Physical Address

space (PA) space Memory

MMU TLB Entries

Page
VA VA
Tables
CPU Cache Table PA
TLB Walk
Data Unit

Data
Trap

• One-step process in case of a hit (+)

• Cache needs to be flushed on a context switch unless address
space identifiers (ASIDs) included in tags (-)
• Aliasing problems due to the sharing of pages (-)
• Maintaining cache coherence (-)

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Caches with Virtual Addressing Cont’d

• To resolve aliasing problems:
• Lookup in the cache with a virtual address
• Verify the data is right with a physical tag
• Look in the TLB at the same time as the cache
Virtual Address

(from Processor)

31 12 0

Virtual Address Virtual Page Number

Virtual Index

Direct-map Cache

2L Blocks

TLB

2b-byte block

31 12 0

Physical Address Physical Page Number

Page offset

Tag
==

Physical Tag

Hit/Miss Data
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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Multiple Page Tables

• Multiple page tables for different processes

OS
User1 VA1 pages

Page table

User2 VA2

Page table

User3 VA3 FREE

Page table

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Suggested Reading

• Read relevant sections of Chapter 5 of

[Patterson and Hennessy, 2021].
• Read Section 2.4 of [Patterson and Hennessy, 2019].

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

Acknowledgment

• Preparation of this material was partly supported by Lampro

Mellon Pakistan.

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Why Use Virtual Memory? Address Translation Page Table Size TLB & Virtual Cache

References

Patterson, D. and Hennessy, J. (2021).

Computer Organization and Design RISC-V Edition: The Hardware
Software Interface, 2nd Edition.
Morgan Kaufmann.

Patterson, D. and Hennessy, J. (6th Edition, 2019).

Computer Architecture: A Quantitative Approach.
Morgan Kaufmann.

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