Memory Management

Virtual Memory
 Review
• Memory Manager
– coordinate how the different types of memory are used
– keep track memory to allocate and release areas of main
memory to processes
– manage swapping between main memory and disk
• No Memory Abstractions
– Single program
• One OS, only one process
• Special register is used to protection between OS and process
• Disadvantages: slow
– Multiple program
• One OS, many processes locate in memory
• Divided into fixed size block
• Disadvantages
– Internal fragmentations
– Two programs both reference absolute physical memory
 static relocation
 Review
• Memory Abstractions
– Multiple processes locate in memory (both primary and secondary)
– Base and Limit Registers
• Multiple processes locate in memory and protection
• Base contains the first address of process in memory, Limit contains the
length of process, the process owns private address space
• Disadvantages
– External fragmentation (Defragment)
– Slow
– Swapping
• Multiple processes with ready processes locate in memory and passive
processes locate in HDD – swap file area
• Swap out/ in operator
• Disadvantages
– External fragmentation
– Process can not grow in memory and the swap area on the disk is full
 data segment upward, stack segment downward
 Review
• Memory Abstractions
– Memory Management with Bitmaps
• The memory divides units with same size that has a bit corresponding bit
in the bitmap (0: free, 1: occupied)
• Disadvantages
– Slow when searching the bitmap to find a run of k consecutive 0 bits in
the map (small)
– Internal fragment (large size)
– Memory Management with Linked Lists
• Maintain a linked list of allocated (P) and free memory (H)
• Allocating algorithms
– First, Next, Best, Worst, Quick Fit
– Virtual Memory
• Software/ Process sizes larger than memory
• Overlays
– Developer splits program to many overlays
– Disadvantages: developer‘s knowledge is important
 Objectives…
• Virtual Memory
–…
– Definitions
– Terminologies
– MMU
– Paging
– Page Tables
– Speeding up Paging
– TLBs
– Multilevel page tables
– Inverted Page tables
 Virtual Memory
Definitions
• Each program has its own address space, which is broken up
into chunks called pages
• Each page
– Is a contiguous range of addresses
– Is mapped onto physical memory, but not all pages have to be in physical
memory to run program
• When the program references a part of its address space that is in
physical memory, the hardware performs the necessary mapping
on the fly (runtime)
• When the program references a part of its address space that is
not in physical memory, the OS is alerted to go get the missing
piece and re-execute the instruction that failed (page fault)
• Is a generalization of the base and limit register idea
• Instead of having separate relocation onto physical memory and
data segments, the entire address space can be mapped onto
physical memory in fairly small units
 Virtual Memory
Terminologies
• Virtual Memory
– Is the separation of user logical memory from physical memory
– This separation allows an extremely large virtual memory to be
provided for developers when only a smaller physical memory is
available (→developer concentrates solving the problem domain)
• Virtual (logical) addresses
– Program memory addresses
• Virtual address space
– All the (virtual) addresses a program can generate
– Is given by the number of bytes used to specify an address
• Physical (real) addresses
– Addresses in main memory (on memory bus)
• Memory Management Unit (MMU)
– A mapping unit from virtual addresses into physical addresses
 Virtual Memory
Memory Management Unit (MMU)

Tanenbaum, Fig. 3-8.

 Virtual Memory
Paging
• Virtual address space
– Is divided into fixed-size units called
pages
– pages from 0 to
AddressSpaceSize / PageSize - 1
• The physical memory
– Is divided up into units of the same size
corresponding in the physical memory
called page frames
– page frames from 0 to
PhysicalMemSize / PageFrames - 1
• Pages and frames are the same size
– PageSize is typically be a value between
512 bytes and 64KB
• Transfers between RAM and disk are
in units of a page
Tanenbaum, Fig. 3-9.
 Virtual Memory
Paging
• In traditional, the paging has been handled by hardware
– The virtual (logical) address is divided into 2 parts
• a virtual page (p)
• a page offset (d)
– The p is used indexed into the page table that
maps the page frame (f) in memory
– The f is combined with d to define the physical
memory address
 Virtual Memory
Paging – General formula
• Assume
– s is a page size
– [p] = virtual address/s
→ d = virtual address – p x s
– f is a page frame mapping page p
→ physical addr = f x s + d

Tanenbaum, Fig. 3-9.

 Virtual Memory
Paging
• move REG, 0
 move REG, 8192
– virtual address 0 is sent to the MMU
• = (virtual page 0, offset 0)
– virtual page 0 mapping is page frame 2
– physical address 8192 (8K)
• = (page frames 2, offset 0)
– →Memory processes at address 8192
• move REG, 20500
 move REG, 12308
– virtual address 20500 (20K)
• = (virtual page 5, offset 20)
– virtual page 5 mapping is page frame 3
– physical address 12308 (12K)
Tanenbaum, Fig. 3-9.
• = (page frame 3, offset 20)
 Virtual Memory
Paging
• Problems
– Only some virtual pages are mapped onto physical memory (e.g
16 pages maps 8 page frames)
→ virtual address space is larger than the physical memory
• Present/Absent bit
– Keeps track of which pages are physically present in memory
• Page fault
– a trap into the OS because of a reference to an address located in
a page not in memory
– generated by the MMU
– result in a swap between physical memory and disk
– the referenced page is loaded from disk into memory
– the trapped instruction is re-executed
Virtual Memory
Paging
 Virtual Memory
Paging
• Example
– MOV REG, 32780 (32K)
• virtual address 8
– =(virtual page 8, offset 12)
• virtual address 8 is unmapped with any
page frame
• → the page fault is executed
– OS decided to evict page frame 1
– OS load page 8 at page frame 1 and
make to changes to the MMU map
– OS re-executed the instruction
• virtual address 8 mapping is page
frame 1
• physical address 4108 (4K)
– (page frame 1, offset 12)
Tanenbaum, Fig. 3-9.
 Virtual Memory
Page Tables
• The mapping of virtual addresses onto physical addresses can be
summarized as following
– The virtual address is split into a virtual page number (high-order bits) and
offset (low-order bits)
– Ex: 16 bit address and a 4KB page size, 4 bit for 16 pages and 12 bit offset (0
to 4095)
• The virtual page number is used as an index into page table to find
the entry for that virtual page
• From the page table entry, the page frame number is found
• The page frame number is attached to the high-order end of the
offset, replacing the virtual page number, to form a physical
address
• Is the function with page number is argument and the page frame as
result
• Each process needs its own page table
 Virtual Memory
Page Tables – Example
• using page size is a power of 2
• 16 bit virtual address is split
into a 4 bit page numbers (16
page) and 12 bit offset (4096
byte address)
• MOV REG, 8196
– 8196 in binary
0010000000000100
• 0010 = page number
• 000000000100 = offset
• =(virtual page 2, offset 4)
– Physical address 24580 (24K)
Tanenbaum, Fig. 3-10. • (page frame 6, offset 4)
 Virtual Memory
Speeding up Paging
• Paging issues
– The mapping from virtual address to physical address must be fast
• Avoid bottleneck
• If an instruction execution takes 1 nsec, the page table lookup must be done in
under 0.2 nsec
– If the virtual address space is large, the page table will be large
• 32 bit virtual address, 4 KB page sizes → 1 million pages (entries)
• Simplest design
– Have a single page table consisting of an array of fast registers, with one entry
for each virtual page, indexed by virtual page number
– Page table is loaded from memory into registers (at starting up)
– No more memory references needed (when processing)
– Advantages: no memory
– Disadvantages:
• Context switch is expensive (load entire table for each process)
• Can apply to the small page table
 Virtual Memory
Speeding up Paging – Example
• If there are 64 pages and the page size is 2048 words, what
is the length of logical address?
– 64 pages = 26 → 6 bits is used to manage number of page
– 2048 words = 211 → 11 bits used to manage page size
→ 17 bits are a result
• If there are 128K pages and the page size is 32 K words,
what is the length of logical address?
– 128K pages = 217 → 17 bits is used to manage number of page
– 32K words = 32.768 words = 215 → 15 bits used to manage page
size
→ 32 bits are a result
 Virtual Memory
Speeding up Paging
• Single Register
– Page table can be entirely in memory
– A single register points to the start of page table
– This register may be located in PCB
– When the process start, this register must be reloaded
– This allows the virtual to physical map to be changed at a context switch by
reloading one register
– Advantages: Context switch is fast (reloaded one register)
– Disadvantages: more references to the memory for reading page table entries
(slow)
 Virtual Memory
Translation Lookaside Buffers (TLB)
• Problem
– The CPU makes a memory access using a virtual address. It requires an
address translation to a real address
– This needs accesses to the page table which is itself in memory i.e. every
virtual memory access requires two (or more if 2 level table) real accesses
→Slow
• Observations
– Keeping the page tables in memory reduce drastically the performance
– Make large number of references to a small number of pages
• Solution: using TLB or associative memory
– A small fast hardware for mapping virtual addresses to physical addresses
without going through the page table
– This device is usually inside in MMU and consists of a small number of
entries (usually less than 64) → maps only a small number of virtual pages
– A TLB entry contains information about one page (valid bit (that presents
the page in use or not use), page number, modified bit, protection bit, page
frame)
– These fields have a one-to-one correspondence with the fields in page table,
except for the page number, which is not need in the page table
– A TLB can be also implemented in software
 Virtual Memory
Translation Lookaside Buffers (TLB)

Tanenbaum, Fig. 3-12.

 Virtual Memory
Translation Lookaside Buffers (TLB)
• How to the TLB do
 Virtual Memory
Translation Lookaside Buffers (TLB)
• How to the TLB do (cont)
– When the virtual address is presented in MMU for translation
– The hardware search entire TLB to find if the entry is matched
– If so,
• If the access does not violate the protection, the page frame is taken
without going to the page table
• Otherwise, the protection fault can occur
– Otherwise,
• The MMU detects the miss and does an ordinary page table lookup
• The MMU evicts one of the entries from the TLB and replaces it with the
page table just looked up
– After the page frame is defined, the physical memory can be
accessed
 Virtual Memory
Multilevel Page Tables
• Problem
– Most modern computer support a large logical address (2 32 to 264)
→ The page table become excessive large and the developer would not want to
allocate it in memory at a/ all time
• Solution
– Divide the page table into smaller pieces
– The multilevel Page tables is used
• To avoid keeping all the page tables in memory all the time
• The main idea is “Paging the page table”
• The virtual address is divided two part: 20 bit page number, and 12 bit offset
• Since the page table is paged again, the page number is divided two into: 10 bit page
number (PT1), and 10 bit offset (PT2)
 Virtual Memory
Multilevel Page Tables
• 32 bit virtual addresses
– 10 bits – PT1
– 10 bits – PT2
– 12 bits – offset
• Page size = 4KB
• No. of pages = 210
• Top-level page table –
1024 entries
– An entry  4MB
• Second-level page table
Tanenbaum, Fig. 3-13. – 1024 entries
– An entry  4KB
 Virtual Memory
Multilevel Page Tables
• How does it work
– First, the MMU extracts the PT1 field and uses this value as an index into the
top level page table
– The entry located by indexing into the top-level page table yields the address
or page frame number of a second-level page table
– The PT2 field is used as an index into the selected second-level page table to
find the page frame number for the page itself
• Ex:
– 32 bit virtual address 0x00403004 (=4.206.596), 12.292 bytes data

– PT1=1 → 4M:8M (=4.194.304 bytes)

– PT2=3 → 12KB:16KB(=12.288 byte : 16383 bytes)
– The virtual address is (4.194.304+12.288 = 4.206.592 to 4.210.687) and Offset = 4
→The page frame PT1 = 1, The page frame of PT2 = 0, thus the physical address is 4
• If the page is not in memory, causing a page fault
• If the page is in memory, the page frame number taken from the second level
page table combined with the offset to construct the physical address
Virtual Memory
Inverted Page Table
 Virtual Memory
Inverted Page Table
• Advantages
– 64bit virtual addresses, a 4KB page, 1GB RAM, an inverted table only
required 262,144 entries (saving vast amount of space)
• Disadvantages
– The virtual-to-physical translation becomes much harder and slower
– Searching the entire table at every memory reference
• Practically: use of TLB and hash tables (searching in software)
 Summary
• Virtual Memory

Q&A
 Next Lecture
• Page replacement Algorithms