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OPERATING SYSTEMS

MEMORY MANAGEMENT – 1

Memory
Management

Nucleus

1. OBJECTIVES: Why is Memory Management

important?

1.1 Relocation :

‹ Multiprogrammed Computers: Memory must be shared

between processors: Do not know in advance how many
other processes/programs will be in memory. Æ
Absolute memory addresses are OUT.

‹ As processes finish, their free space is allocated to other

processes. It may be necessary to move processes about
half way thro execution to compact small non-
contiguous areas into larger (more useful) single area.

z System transforms addresses into actual physical

addresses.
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1.2 Protection : Must not let one process access other

process’ addresses.
Æ Memory references used by a process are checked at run
time for:

i. Write : to avoid corruption.

ii. Read : to provide privacy.

1.3 Logical Organisation :

Software modules/procedures
Data Modifiable
Logical Unmodif’ble
Division Program

Physical Division :

‹ Segmentation of address space,

‹ Cross reference from one segment to another done by
system at run time.
‹ Give protection to each segment : read-only, execute-
only.
‹ Segment sharing among processes, - OK.
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1.4 Physical Organisation

‹ Two level storage:

a. Fast semiconductor Main memory:

b. b. slow magnetic secondary (backing store) memory.

‹ Flow of information between Main memory &

Secondary memory: Most important.

Overlay Programming: Programmer responsible for

moving sections of program/data into main memory.

Disadvantages:

i. Too complicated for programmer to work out;

ii. ii. Dynamic relocation makes programmer’s job even

more difficult/impossible,- has no idea how much
space will be available & where.
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2. VIRTUAL MEMORY

Program Physical
Addresses: Memory Locations:
Address Space Memory Space
Or Name Space M
N Address
Seen by Map Actual
Programmer f Computer
Configuration

Address Transformation Mechanism is called Address

Mapping. It is a System function. Formally stated :

f : N → M

‹ M is linear : locations are numbered sequentially from

zero. Its size = amount of main memory in computer.
‹ N need not be linear. Its size may be < , or = , or > M.

Address Map: allows programmer to use program address

range different from locations available.

It creates a ‘Virtual Memory’ convenient for programmers,

so as to achieve all/some of the Objectives.
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3. IMPLEMENTATION OF VIRTUAL MEMORY

A. BASE & LIMIT REGISTERS.

(Relocation and Protection)

‹ Put lowest address of process in ‘Base Register’ ( or

‘Datum Register’). Thus all addresses are interpreted
relative to this Base Address.

‹ Address Map: simply add program address to base

address to give memory locations. Formally:

f (a) = B + a

physical Base Program

memory Adrs Adrs
locations
of prog Adrs ‘a’

Relocation : Reset base address to new value.

Protection :

‹ Put highest address in ‘Limit Register’

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i. if a < 0, → Memory violation

ii. physical location (f (a)), n’ : = B + a
iii. if a’ > limit, then memory violation

‹ Note: address space mapped by this scheme is linear.

It’s size = (Limit – Base). It is < = M.

Physical
Memory
PROGRAM BASE REGISTER
ADDRESS B
n

B+a

LIMIT REGISTER

limit

‹ Base + Limit registers : in fast H/W

‹ Content of these reg’s need not be accurate to single bit

(memory location), - eg DEC10 reg’s accurate to 1K
portions (l.s. 10 bits of address removed from Base + Limit
reg’s, - cheaper/faster to process).
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Alternative Use of Limit Register:

‹ Store LENGTH of memory space rather than UPPER

LIMIT :

i. if a < 0, or a > Length, then memory violation.

ii. Calculate n’ : = B + a.

Advantage : Length check is independent of addition

results, - if memory violation occurs, do not do addition.

Base & Limit registers are part of the process volatile

environment : loaded & stored when process is
run/suspended. Only one pair of H/W Base & Limit
registers are provided per processor.

Re-entrant procedures : one pair for actual code (Base &

Limit), and one for Data of every process using the code.
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B. PAGING

How do we deal with the case when address space >

memory?

♦ Relieve the programmer of writing overlays → Abolish

distinction between main & secondary memory, - i.e.
One-Level Store (“Manchester Atlas” 1960), → create
VIRTUAL MEMORY.

♦ Divide address space into pages of say 512 words, and

main memory into FRAMES of same size.

♦ Share out frames among processes : each process will

have some pages in memory (ACTIVE pages), and the
rest on disc/2ndry memory (INACTIVE pages).

FUNCTIONS OF PAGING MECHANISM

1. Determine which PAGE a program address refers to,

then find which frame (if active) that page is in now.
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2. If required page is Inactive, get it from 2ndry memory.

This often means having to tranfer some pages out to 2ndry
memory to vacate a frame(s) for the required page.

FUNCTION 1:

MS LS
Address: 8
0
Enough bits for Page number 9bits=512
entire Virtual words/page
Memory Word Number

Example: Atlas, 32 Frames of 512 words, which needs a

total of 14 bits to address each word (9 bits to address each
one of 512 word in a frame plus 5 bits to address each
frame in 32 frames). IF the Virtual address is defined to be
20 bits (to address 1 million words): 9 LS bits for words in
a page plus 11 bits for number of pages, i.e. 2K pages of
virtual memory (against only 32 frames).

Remember all this is invisible to programmer.

PAGE TABLE: Translates page number of program

address to frame number in physical memory,- word
number is usually the same.
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Page Numebr Word

Numebr
p w
Program
adres
Page table Frame p’

P’
P’ + w =
physical
adrs

Frame p’ contains page p of program, e.g. frame 43 contains page 302 of

program.

Formally,
f)a) = f(p,w) = p’ + w

Physical adrs of Made up of (physical Physical location of

program location a is location) program program page p
page p and word w

If Z is page size, then

P = integer part of a/Z (i.e. whole pages)

W = remainder of a/Z
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Example:

Z Z Z W :

=3xZ+w

For a = 1700 and Z = 512, we have

p = 3 and w = 1700 – 1536 = 164.

FUNCTION 2A: Getting pages from disc.

If required program page is not in main memory, two

alternatives may be used:

i. Leave zero in the page table: this causes a ‘page

fault’ interrupt which causes the paging mechanism
to transfer the page. Current process is blocked until
transfer is complete. Separate table is used to locate
psge on disc.

ii. Put disc page adres in page table AND have a present
bit: if bit is set take adrs as main memory adrs;
otherwise Adrs is location of page on disc.
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FUNCTION 2. B Saving Pages on Disc :

Need an algorithm to decide which frame page to save on

disc to free a frame for a required page.

Page Turning Alogrithm : uses information stored in shaded

area of page table to make a decision :

i. the time the page was last referenced.

ii. how many times the page has been referenced.

iii. other info. e.g. has page been written to?

IMPLEMENTING ADDRESS MAPPING OPERATION

(Hardware) Architecture plays major role, particularly in

address mapping.

Page Turning & Page Table updates : done by software.

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Complexity of Address Map

♦ PT is address of 1st location of Page Table.

♦ Index it with page no. to get address of p’, i.e. PT(p).

♦ Use indirect addressing on the result to get 1st address of

frame p’, i.e. @[PT(p)]

♦ Index the result by w to get the physical address, ie

{@[PT(p)]}(w)

This takes too long using the normal machine code instrns.

Therefore must have special H/W page-addressing facility :

i. Make the Page Table a set of H/W fast registers to speed

up indirect/indexing operations : Expensive, we need as
many registers as virtual memory pages, - typically
several k’s.

iii. Reduce the number of special registers to no. of

frames of physical memory, - AND turn the page
‘indirect addressing’ problem inside-out:
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a) have a set of page address registers (PARs) each

corresponding to one frame address
b) each PAR contains the page number of an active
page of the program address,
c) special ‘associative’ H/W searches the content of
all PARS simultaneously to find which PAR has
the required program page number.,
d) the PAR no. is p’ which is used to find physical
memory address.

Associative store
Page 0 7 p w Program
Adrs 1 1 address
Reg’s 2 2 3 243
-PAR 3 6
4 5 Simultaneous comparison
*5 3* with all PARs to give
: PAR no.
: P’ w Memory
5 243 location
n-1

Where n is the number of (physical) frames.

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Associative Store does an address map in about 50 nS

(nano second) compared with 500 nS for a page table in
main memory.

Large Memory Systems: need large associative store:

number iof PARs = 2 x memory size in K words (512
words per page).

Compromise: hold page table in main memory, but store

Most Active page address in associative store. Frame
number is no longer the position of the PAR but must be
included as an extra field in the PAR itself.

Associative Store p w Prog adrs

P’ p Associative search for

p; when found, get
associated p’
P’ w Memory
Location
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BSC COMPUTER STUDIES (FT): YEAR 2, OPERATING SYSTEMS, QUESTIONS.

MEMORY MANAGEMENT – 1

1. List the four objectives of memory management systems

2. Explain the term Relocation and discuss why it is not feasible for the programmer
to use absolute physical addresses. Why does the MMS need to compact small
non-contiguous areas of memory?

3. Explain the term Protection and discuss its two main aspects.

4. What are the differences between ‘logical’ and ‘physical’ organisation of memory.

5. What is virtual memory? Express formally the relationship between program

address space and physical memory locations and comment on the terms ‘linear’
and ‘nonlinear’.

6. With the aid of diagrams explain how the Base and Limit registers are used by the
CPU to provide relocation and protection. Comment on an alternative use of the
Limit register and discuss its advantages.

7. Explain the terms Page and Frame distinguishing between them and commenting
on the use of ‘active’ and ‘inactive’ pages.

8. What are the two main functions of the paging mechanism? Using diagrams
explain how the first function is performed.

9. Explain how getting pages from disc is handled by MMS. What does a ‘page
turning’ algorithm do?

10. What are the four main steps in implementing the address-mapping operation?
Discuss and point out why special hardware page addressing facility is required.

11. Suggest two alternative hardware page-addressing methods and contrast their
advantages and disadvantages.

12. What are PAR and Associative Store? Explain using diagrams the page-
addressing mechanism which rely on these two facilities.

13. For large memory systems it becomes too expensive to operate the scheme in
Q12. Using diagrams develop a compromise.