Fabrication technology
A processing sequence in VLSI is repeated for each layer and consists of: Planarising and cleaning the surface of the previous layer. Deposition of new layers (semiconductors, dielectrics or metals) Patterning layers using lithography and removing any unwanted areas by etching Optimise layer characteristics by implantation or heat treatment
Aim
Introduction to state-of-the-art technology used in sub-micron CMOS processing. Familiarization with the processing steps required for CMOS fabrication.
What is CMOS?
Complementary MOSFET: series connection on wafer of an n-MOS and a pMOS Remember: n-MOS made in p-type Si p-MOS made in n-type Si
CMOS
N-MOS and P-MOS
Simple CMOS circuits
NOT
NOR
CMOS: determines fabrication technology
CMOS inverter fabrication
Take cleanroom
www.nnf.cornell.edu/2000REU/ cnfreu2k/Hoff.cleanroom.jpg crio.mi.infn.it/wig/silicini/ img.jpg/IRST-cleanroom.JPG
CMOS inverter fabrication
Take p-type wafer
Current technology:
300mm
www.atp.nist.gov/eao/sp950-2/ diamond_1lo.jpg
CMOS inverter fabrication
Bulk material: wafer
Purified melt Seed Controlled cooling at phase boundary Ingot with diameter of 300 mm
Current technology:
300mm
CMOS inverter fabrication
Bulk material: wafer
Ingot with diameter of 300 mm
Wafer dicing and polishing
Current technology:
300mm
CMOS inverter fabrication
Cross section p-type wafer Oxide growth
p-substrate
Thermal oxidation
Consumes a layer of the Si wafer
Dry oxidation
800C 1100C Si + O2 SiO2 Slow process Dense, pure, high quality oxide Gate oxide
Wet oxidation
700C 1200C Si + 2H2O SiO2 + 2H 2 Faster process Medium quality oxide Field oxide
CMOS inverter fabrication
Cross section p-type wafer Definition of n-well
SiO2 p-substrate
How do we go from this:
SiO2 p-substrate
to this?
SiO2 p-substrate
n-well
CMOS inverter fabrication
Photolithography Spin photoresist
SiO2 p-substrate
Lithography
radiation mask resist dielectric or metal
Transferring patterns on a mask, consisting of transparent and non-transparent areas, via radiation onto a radiation sensitive layer (resist) on the semiconductor.
Fig taken from: http://www.marohn.chem.cornell.edu/nanofab/images/autostep_mask.JPG
Lithography methods
Optical lithography UV irradiation phase shift masks & short wavelength irradiation: = 248nm193nm157nm EUV node =115nm 65 nm (lg=80 nm 32 nm)
Focal length of lens Wavelength light
f d = 2.44 a
Minimum spot size Diameter of lens
From: http://www.ncnanotechnology.com/public/_assets/TNLC_Semicondutor_Process.jpg
Note on phase shift mask
Normal mask
Phase shift mask
Works based on light interference effects to increase contrast in certain regions of the masked wafer.
Lithography methods
Immersion lithography
From wikipedia
High purity water rather than air between lens and wafer. H2O has a higher refractive index than air and therefore the resolution is increased 37 nm
From: www.nikon.co.jp/.../immersion_e/img/gfx01_i.gif
Lithography methods
E-beam lithography
electron wavelength 1
node < 40 nm
Taken from: http://www.prism.princeton.edu/PRISM_cleanroom/equip/Raith/Raith%20e-LiNE.JPG Taken from: http://www.hkbu.edu.hk/~csar/semdiagram.jpg
exposure mask p-substrate development wet etch: BHF
Etching
Wet etching
Liquid chemicals Atmospheric pressure Pure chemical reactions Isotropic High selectivity
HF: SiO2 Si TMAH: Si SiGe
Dry etching
Gaseous chemicals Plasma (ions) assisted Low pressure Chemical-mechanical reactions Anisotropic Poor selectivity
(mechanical bombardment)
Cleaning
RIE: polySi gate etch
CMOS inverter fabrication
Implantation
p-substrate
Dissolve photoresist
Ion implantation
Change of carrier type or density Spin-on doping Diffusion in oven:
Allows batch processing
Ion implantation
Strict control of depth and density
CMOS inverter fabrication
Anneal
n-well p-substrate
CMOS inverter fabrication
Define active areas Oxide layer growth
Photolithography
n-well p-substrate
CMOS inverter fabrication
Deposit polysilicon Grow gate oxides
n-well p-substrate
Deposition
No consumption of the Si wafer
Semiconductor & Dielectrics
Chemical Vapour deposition (CVD) Molecular Vapour epitaxy (MBE) Liquid phase epitaxy (LPE) Spin-on dielectrics
Metals
Chemical vapour deposition (CVD) Thermal evaporation Sputter coating Electro-plating
Chemical Vapour Deposition
transport of gasses to the substrate absorption of the species in the gases on the substrate chemical reaction catalyzed by the substrate surface desorption of gaseous reaction products transport of reaction residue away from the substrate
Sputter Coating
Ar plasma is generated
RF field B field (confinement)
Ar+ hit target
E field
Target atoms ejected Target atoms deposited on substrate
Angstrom sciences
Electroplating
Au3+
electrolyte
Thick metal layers Cu, Au Function of metal resistivity Additives (impurities) d I t/
CMOS inverter fabrication
PolySi gate creation Reactivelithography E-beam ion etching
Jeol
n-well p-substrate
Vacuum chamber
wafer ~ RF
plasma
CMOS inverter fabrication
A complete simplified animated pn-junction process pn junction fabrication steps A complete simplified animated CMOS process CMOS fabrication
CMOS inverter fabrication
~150 processing steps further Lithography Deposition Implantation Etch
More than one metal layer
Planarisation
Chemical-mechanical Polishing (CMP)
Chemical slurry
KOH + 10 90 nm diamond or SiO2 grit
Rotating pad Rotating wafer holder
Damascene process
Metal inlay process
- CVD dielectric - Pattern dielectric - Sputter metal - CMP metal Solves:
Metal etching Gap filling
Dual damascene process
Metal line
Via plug
Copper interconnect technology using damascene process
http://sinclair.ece.uci.edu/Useful%20educational%20pictures/
Result
www.phy.ntnu.edu.tw/.../English/ images/Silicon%20wafer.jpg
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Conclusion
All steps necessary to fabricate CMOS are introduced
State-of-the-art 50 nm Gate length MOSFET TEM cross section
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